1 /******************************************************************************
2 ** File Name: analog_reg_v3.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 03/03/2010 Tim.Luo Create. *
13 ** 05/07/2010 Mingwei.zhang Modify it for SC8800G. *
14 ******************************************************************************/
16 #ifndef _ANALOG_REG_V3_H_
17 #define _ANALOG_REG_V3_H_
20 #include "sc8810_reg_base.h"
21 /*----------------------------------------------------------------------------*
23 **-------------------------------------------------------------------------- */
25 /**---------------------------------------------------------------------------*
27 **---------------------------------------------------------------------------*/
32 /**----------------------------------------------------------------------------*
34 **----------------------------------------------------------------------------*/
36 //Analog die register define
38 //#define ANA_REG_BASE 0x82000600
39 #if defined(CONFIG_SC7710G2)
40 #define ANA_APB_CLK_EN (ANA_REG_BASE + 0x00)
41 #define ANA_RTC_CLK_EN (ANA_REG_BASE + 0x0C)
42 #define ANA_ARM_RST_EN (ANA_REG_BASE + 0x18)
43 #define ANA_ARCH_EN (ANA_REG_BASE + 0x24)
44 #define ANA_LDO_PD_SET (ANA_REG_BASE + 0x28)
45 #define ANA_LDO_PD_RST (ANA_REG_BASE + 0x2C)
46 #define ANA_LDO_PD_CTL0 (ANA_REG_BASE + 0x30)
47 #define ANA_LDO_PD_CTL1 (ANA_REG_BASE + 0x34)
48 #define ANA_LDO_VCTL0 (ANA_REG_BASE + 0x38)
49 #define ANA_LDO_VCTL1 (ANA_REG_BASE + 0x3C)
50 #define ANA_LDO_VCTL2 (ANA_REG_BASE + 0x40)
51 #define ANA_LDO_VCTL3 (ANA_REG_BASE + 0x44)
52 #define ANA_LDO_VCTL4 (ANA_REG_BASE + 0x48)
53 #define ANA_LDO_VCTL5 (ANA_REG_BASE + 0x4c)
54 #define ANA_LDO_SLP_CTL0 (ANA_REG_BASE + 0x50)
55 #define ANA_LDO_SLP_CTL1 (ANA_REG_BASE + 0x54)
56 #define ANA_LDO_SLP_CTL2 (ANA_REG_BASE + 0x58)
57 #define ANA_LDO_SLP_CTL3 (ANA_REG_BASE + 0x5c)
58 #define ANA_LDO_DP_SLP_CTL0 (ANA_REG_BASE + 0x60)
59 #define ANA_LDO_DP_SLP_CTL1 (ANA_REG_BASE + 0x64)
60 #define ANA_LDO_XTL_SLP_CTL0 (ANA_REG_BASE + 0x68)
61 #define ANA_LDO_XTL_SLP_CTL1 (ANA_REG_BASE + 0x6c)
62 #define ANA_SLP_LP_CTL0 (ANA_REG_BASE + 0x70)
63 #define ANA_SLP_LP_CTL1 (ANA_REG_BASE + 0x74)
64 #define ANA_SLP_LP_XTL_CTL0 (ANA_REG_BASE + 0x78)
65 #define ANA_SLP_LP_XTL_CTL1 (ANA_REG_BASE + 0x7C)
66 #define ANA_LDO_SLP_CTL (ANA_REG_BASE + 0x80)
67 #define ANA_AUDIO_CTL (ANA_REG_BASE + 0x88)
68 #define ANA_CHGR_CTL0 (ANA_REG_BASE + 0x8C)
69 #define ANA_CHGR_CTL1 (ANA_REG_BASE + 0x90)
70 #define ANA_VIBRATOR_CTL0 (ANA_REG_BASE + 0x94)
71 #define ANA_VIBRATOR_CTL1 (ANA_REG_BASE + 0x98)
72 #define ANA_VIBRATOR_CTL2 (ANA_REG_BASE + 0x9c)
73 #define ANA_VIBR_WR_PROT (ANA_REG_BASE + 0xa0)
74 #define ANA_MCU_WR_PROT (ANA_REG_BASE + 0xa4)
75 #define ANA_MUC_WR_STS (ANA_REG_BASE + 0xa8)
76 #define ANA_RTC_CTRL (ANA_REG_BASE + 0xac)
77 #define ANA_RTC32K_OSC_EN (ANA_REG_BASE + 0xb0)
78 #define ANA_KPLED_CTRL (ANA_REG_BASE + 0xb4)
79 #define ANA_XTL_WAIT (ANA_REG_BASE + 0xb8)
80 #define ANA_MIXED_CTRL (ANA_REG_BASE + 0xbc)
81 #define ANA_STS (ANA_REG_BASE + 0xc0)
82 #define ANA_WDG_HRST_STS (ANA_REG_BASE + 0xc4)
83 #define ANA_HWRST_STATUS (ANA_REG_BASE + 0xc8)
84 #define ANA_ALL_HRST_STS (ANA_REG_BASE + 0xcc)
85 #define ANA_INT_GPI_DBG (ANA_REG_BASE + 0xd0)
86 #define ANA_HWRST_RTC (ANA_REG_BASE + 0xd4)
87 #define ANA_IF_SPR_CTL (ANA_REG_BASE + 0xd8)
88 #define ANA_EFUSE_CTL (ANA_REG_BASE + 0xe0)
89 #define ANA_EFUSE_OUT0 (ANA_REG_BASE + 0xe4)
90 #define ANA_DLY_CNT (ANA_REG_BASE + 0xf0)
91 #define ANA_EXT_FLAG_CTL (ANA_REG_BASE + 0xf4)
92 #define ANA_POR_SRC_FLAG (ANA_REG_BASE + 0xf8)
93 #define ANA_PBINT_7S_CTL (ANA_REG_BASE + 0xfc)
94 #define ANA_DCDC_CORE_CTRL0 (ANA_REG_BASE + 0x100)
95 #define ANA_DCDC_CORE_CTRL1 (ANA_REG_BASE + 0x104)
96 #define ANA_DCDC_CORE_CTRL2 (ANA_REG_BASE + 0x108)
97 #define ANA_DCDC_CORE_CTRL3 (ANA_REG_BASE + 0x10c)
98 #define ANA_DCDC_OPT_CTL (ANA_REG_BASE + 0x114)
99 #define ANA_DCDC_ARM_CTL0 (ANA_REG_BASE + 0x118)
100 #define ANA_DCDC_ARM_CTL1 (ANA_REG_BASE + 0x11c)
101 #define ANA_DCDC_ARM_CTL2 (ANA_REG_BASE + 0x120)
102 #define ANA_DCDC_ARM_CTL3 (ANA_REG_BASE + 0x124)
103 #define ANA_DCDC_MEM_CTL0 (ANA_REG_BASE + 0x12c)
104 #define ANA_DCDC_MEM_CTL1 (ANA_REG_BASE + 0x130)
105 #define ANA_DCDC_MEM_CTL2 (ANA_REG_BASE + 0x134)
106 #define ANA_DCDC_MEM_CTL3 (ANA_REG_BASE + 0x138)
107 #define ANA_WPA_DCDC_AP_CTL0 (ANA_REG_BASE + 0x140)
108 #define ANA_WPA_DCDC_AP_CTL1 (ANA_REG_BASE + 0x144)
109 #define ANA_WPA_DCDC_AP_CTL2 (ANA_REG_BASE + 0x148)
110 #define ANA_DCDC_LP_EN (ANA_REG_BASE + 0x14c)
111 #define ANA_DCDC_SLP_V (ANA_REG_BASE + 0x150)
112 #define ANA_LDO_TRIM0 (ANA_REG_BASE + 0x154)
113 #define ANA_LDO_TRIM1 (ANA_REG_BASE + 0x158)
114 #define ANA_LDO_TRIM2 (ANA_REG_BASE + 0x15c)
115 #define ANA_LDO_TRIM3 (ANA_REG_BASE + 0x160)
116 #define ANA_LDO_TRIM4 (ANA_REG_BASE + 0x164)
117 #define ANA_LDO_TRIM5 (ANA_REG_BASE + 0x168)
118 #define ANA_LDO_TRIM6 (ANA_REG_BASE + 0x16c)
119 #define ANA_LDO_TRIM7 (ANA_REG_BASE + 0x170)
120 #define ANA_LDO_TRIM8 (ANA_REG_BASE + 0x174)
121 #define ANA_LDO_TRIM9 (ANA_REG_BASE + 0x178)
122 #define ANA_LDO_CAL (ANA_REG_BASE + 0x17c)
123 #define ANA_LDO_SWITCH (ANA_REG_BASE + 0x180)
124 #define ANA_WHTLED_CTL0 (ANA_REG_BASE + 0x188)
125 #define ANA_WHTLED_CTL1 (ANA_REG_BASE + 0x18c)
126 #define ANA_WHTLED_CTL2 (ANA_REG_BASE + 0x190)
127 #define ANA_WHTLED_CTL3 (ANA_REG_BASE + 0x194)
128 #define ANA_AFUSE_CTL (ANA_REG_BASE + 0x1a0)
129 #define ANA_AFUSE_OUT0 (ANA_REG_BASE + 0x1a4)
130 #define ANA_AFUSE_OUT1 (ANA_REG_BASE + 0x1a8)
131 #define ANA_AFUSE_OUT2 (ANA_REG_BASE + 0x1ac)
132 #define ANA_AFUSE_OUT3 (ANA_REG_BASE + 0x1b0)
133 #define ANA_SLP_AUD_PD_EN (ANA_REG_BASE + 0x1c0)
134 #define ANA_MF (ANA_REG_BASE + 0x1f4)
135 #define ANA_CHIP_ID_LOW (ANA_REG_BASE + 0x1F8)
136 #define ANA_CHIP_ID_HIGH (ANA_REG_BASE + 0x1FC)
138 #define ANA_APB_CLK_EN (ANA_REG_BASE + 0x00)
139 #define ANA_APB_ARM_RST (ANA_REG_BASE + 0x04)
140 #define ANA_LDO_PD_SET (ANA_REG_BASE + 0x08)
141 #define ANA_LDO_PD_RST (ANA_REG_BASE + 0x0C)
142 #define ANA_LDO_PD_CTL0 (ANA_REG_BASE + 0x10)
143 #define ANA_LDO_PD_CTL1 (ANA_REG_BASE + 0x14)
144 #define ANA_LDO_VCTL0 (ANA_REG_BASE + 0x18)
145 #define ANA_LDO_VCTL1 (ANA_REG_BASE + 0x1C)
146 #define ANA_LDO_VCTL2 (ANA_REG_BASE + 0x20)
147 #define ANA_LDO_VCTL3 (ANA_REG_BASE + 0x24)
148 #define ANA_LDO_VCTL4 (ANA_REG_BASE + 0x28)
149 #define ANA_LDO_SLP_CTL0 (ANA_REG_BASE + 0x2C)
150 #define ANA_LDO_SLP_CTL1 (ANA_REG_BASE + 0x30)
151 #define ANA_LDO_SLP_CTL2 (ANA_REG_BASE + 0x34)
152 #define ANA_DCDC_CTL (ANA_REG_BASE + 0x38)
153 #define ANA_DCDC_CTL_DS (ANA_REG_BASE + 0x3C)
154 #define ANA_DCDC_CTL_CAL (ANA_REG_BASE + 0x40)
155 #define ANA_DCDCARM_CTL (ANA_REG_BASE + 0x44)
156 #define ANA_DCDCARM_CTL_CAL (ANA_REG_BASE + 0x48)
157 #define ANA_PLL_CTL (ANA_REG_BASE + 0x4C)
158 #define ANA_APLLMN (ANA_REG_BASE + 0x50)
159 #define ANA_APLLWAIT (ANA_REG_BASE + 0x54)
160 #define ANA_RTC_CTL (ANA_REG_BASE + 0x58)
161 #define ANA_TRF_CTL (ANA_REG_BASE + 0x5C)
162 #define ANA_CHGR_CTL0 (ANA_REG_BASE + 0x60)
163 #define ANA_CHGR_CTL1 (ANA_REG_BASE + 0x64)
164 #define ANA_LED_CTL (ANA_REG_BASE + 0x68)
165 #define ANA_VIBRATOR_CTL0 (ANA_REG_BASE + 0x6C)
166 #define ANA_VIBRATOR_CTL1 (ANA_REG_BASE + 0x70)
167 #define ANA_AUDIO_CTL (ANA_REG_BASE + 0x74)
168 #define ANA_AUDIO_PA_CTL0 (ANA_REG_BASE + 0x78)
169 #define ANA_AUDIO_PA_CTL1 (ANA_REG_BASE + 0x7C)
170 #define ANA_MIXED_CTL (ANA_REG_BASE + 0x80)
171 #define ANA_STATUS (ANA_REG_BASE + 0x84)
172 #define ANA_HWRST_STATUS (ANA_REG_BASE + 0x88)
173 #define ANA_MCU_WR_PROT (ANA_REG_BASE + 0x8C)
174 #define ANA_VIBR_WR_PROT (ANA_REG_BASE + 0x90)
175 #define ANA_INT_GPI_DEBUG (ANA_REG_BASE + 0x94)
176 #define ANA_HWRST_RTC (ANA_REG_BASE + 0x98)
177 #define ANA_IF_SPR_CTRL (ANA_REG_BASE + 0x9C)
178 #define ANA_CHIP_ID_LOW (ANA_REG_BASE + 0xF8)
179 #define ANA_CHIP_ID_HIGH (ANA_REG_BASE + 0xFC)
182 the APB_CLK_EN register bit
185 #define CHGRWDG_EB BIT_15
186 #define CLK_AUXAD_EN BIT_14
187 #define CLK_AUXADC_EN BIT_13
188 #define RTC_TPC_EB BIT_12
189 #define RTC_EIC_EB BIT_11
190 #ifdef CONFIG_SC7710G2
191 #define RTC_WDG_EB BIT_2
193 #define RTC_WDG_EB BIT_10
195 #define RTC_RTC_EB BIT_9
196 #ifdef CONFIG_SC7710G2
197 #define RTC_ARCH_EB BIT_0
199 #define RTC_ARCH_EB BIT_8
201 #define PINREG_EB BIT_7
202 #define AGEN_RTC_EN BIT_1
203 #define AGEN_RTC_RTC_EN BIT_9
205 #define GPIO_EB BIT_6
211 #define APB_ARCH_EB BIT_0
214 the APB_ARM_RST register bit
216 #define GPIO_SOFT_RST BIT_7
217 #define EIC_SOFT_RST BIT_6
218 #define TPC_SOFT_RST BIT_5
219 #define ADC_SOFT_RST BIT_4
220 #define WDG_SOFT_RST BIT_3
221 #define CHGRWDG_SOFT_RST BIT_2
222 #define VBMC_SOFT_RST BIT_1
223 #define RTC_SOFT_RST BIT_0
225 the LDO_PD_SET register bit
227 #define DCDCAM_PD BIT_9
228 #define LDO_BPVDD25 BIT_8
229 #define LDO_BPVDD18 BIT_7
230 #define LDO_BPVDD28 BIT_6
231 #define LDO_BPAVDDBB BIT_5
232 #define LDO_BPRF1 BIT_4
233 #define LDO_BPRF0 BIT_3
234 #define LDO_BPMEM BIT_2
235 #define DCDC_PD BIT_1
238 #define ANA_LDO_PD_SET_MSK 0x3FF
240 the LDO_PD_RST register bit
242 #define DCDCAM_PD_RST BIT_9
243 #define LDO_BPVDD25_RST BIT_8
244 #define LDO_BPVDD18_RST BIT_7
245 #define LDO_BPVDD28_RST BIT_6
246 #define LDO_BPAVDDBB_RST BIT_5
247 #define LDO_BPRF1_RST BIT_4
248 #define LDO_BPRF0_RST BIT_3
249 #define LDO_BPMEM_RST BIT_2
250 #define DCDC_PD_RST BIT_1
251 #define PDBG_RST BIT_0
253 the LDO_PD_CTL0 register bit
255 #define LDO_BPVB_RST BIT_15
256 #define LDO_BPVB BIT_14
257 #define LDO_BPCAMA_RST BIT_13
258 #define LDO_BPCAMA BIT_12
259 #define LDO_BPCMAD1_RST BIT_11
260 #define LDO_BPCAMD1 BIT_10
261 #define LDO_BPCMAD0_RST BIT_9
262 #define LDO_BPCAMD0 BIT_8
263 #define LDO_BPSIM1_RST BIT_7
264 #define LDO_BPSIM1 BIT_6
265 #define LDO_BPSIM0_RST BIT_5
266 #define LDO_BPSIM0 BIT_4
267 #define LDO_BPSDIO0_RST BIT_3
268 #define LDO_BPSDIO0 BIT_2
269 #define LDO_BPUSBH_RST BIT_1
270 #define LDO_BPUSBH BIT_0
271 #define ANA_LDO_PD_CTL0_MSK 0x5555
274 the LDO_PD_CTL1 register bit
276 #define LDO_BPSIM3_RST BIT_9
277 #define LDO_BPSIM3 BIT_8
278 #define LDO_BPSIM2_RST BIT_7
279 #define LDO_BPSIM2 BIT_6
280 #define LDO_BPWIFI_RST BIT_5
281 #define LDO_BPWIF1 BIT_4
282 #define LDO_BPWIF0_RST BIT_3
283 #define LDO_BPWIF0 BIT_2
284 #define LDO_BPSDIO1_RST BIT_1
285 #define LDO_BPSDIO1 BIT_0
286 #define ANA_LDO_PD_CTL1_MSK 0x155
288 the LDO_SLP_CTL0 register bit
290 #define FSM_LDOSDIO1_BP_EN BIT_15
291 #define FSM_LDOVDD25_BP_EN BIT_13
292 #define FSM_LDOVDD18_BP_EN BIT_12
293 #define FSM_LDOVDD28_BP_EN BIT_11
295 #define FSM_LDOAVDDBB_BP_EN BIT_10
296 #define FSM_LDOSDIO0_BP_EN BIT_9
297 #define FSM_LDOVB_BP_EN BIT_8
298 #define FSM_CAMA_BP_EN BIT_7
299 #define FSM_CAMD1_BP_EN BIT_6
300 #define FSM_CAMD0_BP_EN BIT_5
301 #define FSM_USBH_BP_EN BIT_4
302 #define FSM_SIM1_BP_EN BIT_3
303 #define FSM_SIM0_BP_EN BIT_2
304 #define FSM_RF1_BP_EN BIT_1
305 #define FSM_RF0_BP_EN BIT_0
308 the LDO_SLP_CTL1 register bit
310 #define FSM_SLPPD_EN BIT_15
311 #define FSM_DCDCARM_BP_EN BIT_4
312 #define FSM_SIM3_BP_EN BIT_3
313 #define FSM_SIM2_BP_EN BIT_2
314 #define FSM_WF1_BP_EN BIT_1
315 #define FSM_WF0_BP_EN BIT_0
317 the DCDC_CTL register bit
319 #define DCDC_RESERVE_RST BIT_13
320 #define DCDC_RESERVE BIT_12
321 #define DCDC_DEDTDELAY_RST BIT_11
322 #define DCDC_DEDTDELAY BIT_10
323 #define DCDC_DEDTDEN_RST BIT_9
324 #define DCDC_DEDTDEN BIT_8
327 #define CHGR_ADAPTER_EN BIT_0
328 #define CHGR_ADAPTER_EN_RST BIT_1
329 #define CHGR_USB_500MA_EN BIT_2
330 #define CHGR_USB_500MA_EN_RST BIT_3
332 #define CHGR_USB_CHG_SHIFT 4
333 #define CHGR_USB_CHG_MSK (3 << CHGR_USB_CHG_SHIFT)
334 #define CHGR_ADAPTER_CHG_SHIFT 6
335 #define CHGR_ADAPTER_CHG_MSK (3 << CHGR_ADAPTER_CHG_SHIFT)
336 #define CHGR_PD_BIT BIT_8
337 #define PA_LDO_EN_RST BIT_9
338 #define CHGR_RECHG_BIT BIT_12
339 #define CHGR_ADATPER_EN_BIT BIT_0
340 #define CHGR_ADATPER_EN_RST_BIT BIT_1
341 #define CHGR_USB_500MA_EN_BIT BIT_2
342 #define CHGR_USB_500MA_EN_RST_BIT BIT_3
343 #define CHAR_ADAPTER_MODE_MSK (BIT_0|BIT_1|BIT_2|BIT_3)
346 #define CHAR_SW_POINT_SHIFT 0
347 #define CHAR_SW_POINT_MSK (0x1F << CHAR_SW_POINT_SHIFT)
350 the VIBRATOR_CTL0 register bit
352 #define VIBR_STABLE_V_SHIFT 12
353 #define VIBR_STABLE_V_MSK (0x0F << VIBR_STABLE_V_SHIFT)
354 #define VIBR_INIT_V_SHIFT 8
355 #define VIBR_INIT_V_MSK (0x0F << VIBR_INIT_V_SHIFT)
356 #define VIBR_V_BP_SHIFT 4
357 #define VIBR_V_BP_MSK (0x0F << VIBR_V_BP_SHIFT)
358 #define VIBR_PD_RST BIT_3
359 #define VIBR_PD_SET BIT_2
360 #define VIBR_BP_EN BIT_1
361 #define VIBR_RTC_EN BIT_0
363 the AUDIO_CTL register bit
365 #define VB_ARM_SOFT_RST BIT_15
366 #define HEADDETECT_PD BIT_7
367 #define LININRE_EN BIT_3
368 #define VBMCLK_SOURCE_SEL BIT_2
369 #define VBMCLK_ARM_ACC BIT_1
370 #define VBMCLK_ARM_EN BIT_0
372 the AUDIO_PA_CTL0 register bit
374 #define PA_OCP_I BIT_12
375 #define PA_OTP_PD BIT_11
376 #define PA_VCM_EN BIT_3
377 #define PA_STOP_EN BIT_2
378 #define PA_EN_RST BIT_5
381 the AUDIO_PA_CTL1 register bit
383 #define PA_ABOCP_PD BIT_15
384 #define PA_DOCP_PD BIT_14
385 #define PA_DEMI_EN BIT_11
386 #define PA_D_EN BIT_10
387 #define PA_LDO_EN_RST BIT_9
388 #define PA_LDO_EN BIT_8
389 #define PA_LDOOCP_PD BIT_7
390 #define PA_SWOCP_PD BIT_2
391 #define PA_SW_EN_RST BIT_1
392 #define PA_SW_EN BIT_0
394 the ANA_MIXED_CTRL register bit
396 #define PTEST_PD_SET BIT_15
397 #define VIBR_PWR_ERR_CLR BIT_7
398 #define CLKBT_EN BIT_6
399 //#define CLK26M_REGS0
400 #define UVH0_EN_RST BIT_3
401 #define UVH0_EN BIT_2
402 #define OTP_EN_RST BIT_1
405 the ANA_STATUS register bit
407 #define VIBR_PWR_ERR BIT_15
408 #define BONDOPT2 BIT_10
409 #define VIBR_PD BIT_9
410 #define WHTLED_PD BIT_8
411 #define CHGR_ON BIT_3
412 #define CHGR_STDBY BIT_2
413 #define BONDOPT1 BIT_1
414 #define BONDOPT0 BIT_0
416 the IF_SPR_CTL register bit
418 #define IF_SPR_IN BIT_2
419 #define IF_SPR_OE BIT_1
420 #define IF_SPR_OUT BIT_0
423 #define HWRST_STATUS_POWERON_MASK (0xf0)
424 #define HWRST_STATUS_RECOVERY (0x20)
425 #define HWRST_STATUS_FASTBOOT (0X30)
426 #define HWRST_STATUS_NORMAL (0X40)
427 #define HWRST_STATUS_ALARM (0X50)
428 #define HWRST_STATUS_SLEEP (0X60)
429 #define HWRST_STATUS_SPECIAL (0x70)
430 #define HWRST_STATUS_PANIC (0X80)
431 #define HWRST_STATUS_NORMAL2 (0Xf0) /* modem sets 0x1f0 (0xf0 after masking) */
433 //ryan:add for poweroff debug.
435 #define ANA_LDO_PD_SET_MSK 0x1fff
437 #define ANA_LDO_PD_CTL_MSK 0x5555
439 #define ANA_LDO_PD_RST_MSK 0x0000
440 /**----------------------------------------------------------------------------*
442 **----------------------------------------------------------------------------*/
444 /**----------------------------------------------------------------------------*
445 ** Local Function Prototype **
446 **----------------------------------------------------------------------------*/
448 /**----------------------------------------------------------------------------*
449 ** Function Prototype **
450 **----------------------------------------------------------------------------*/
453 /**----------------------------------------------------------------------------*
455 **----------------------------------------------------------------------------*/
459 /**---------------------------------------------------------------------------*/
461 #endif //_ANALOG_REG_V3_H_