arch/arm/include/asm/arch-sc8810/adc_reg_v5.h

   1 /******************************************************************************
   2  ** File Name:        adc_reg_v3.h                                            *
   3  ** Author:           Ryan.Liao                                               *
   4  ** DATE:             09/16/2009                                              *
   5  ** Copyright:        2009 Spreatrum, Incoporated. All Rights Reserved.       *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE            NAME            DESCRIPTION                               *
  12  ** 09/16/2009    Ryan.Liao           Created for SC7710G2                    *
  13  ******************************************************************************/
  14
  15 #ifndef _ADC_REG_V5_H_
  16 #define _ADC_REG_V5_H_
  17 /*----------------------------------------------------------------------------*
  18  **                         Dependencies                                      *
  19  **------------------------------------------------------------------------- */
  20
  21 /**---------------------------------------------------------------------------*
  22  **                             Compiler Flag                                 *
  23  **--------------------------------------------------------------------------*/
  24
  25 #ifdef __cplusplus
  26 extern "C" {
  27 #endif
  28
  29 #include <asm/arch/sc8810_reg_base.h>
  30
  31 #define ADC_REG_BASE    (ADC_BASE)
  32
  33 #define adc_write(val,reg) \
  34         do { \
  35                 ANA_REG_SET((u32)reg,val); \
  36 } while (0)
  37 static unsigned adc_read(unsigned addr)
  38 {
  39         return ANA_REG_GET(addr);
  40 }
  41
  42 #define ADC_CTL         (0x00)
  43 #define ADC_SW_CH_CFG           (0x04)
  44 #define ADC_FAST_HW_CHX_CFG(_X_)                ((_X_) * 0x4 + 0x8)
  45 #define ADC_SLOW_HW_CHX_CFG(_X_)                ((_X_) * 0x4 + 0x28)
  46 #define ADC_HW_CH_DELAY         (0x48)
  47
  48 #define ADC_DAT         (0x4c)
  49 #define adc_get_data(_SAMPLE_BITS_)             (adc_read(ADC_REG_BASE + ADC_DAT) & (_SAMPLE_BITS_))
  50
  51 #define ADC_IRQ_EN              (0x50)
  52 #define adc_enable_irq(_X_)     do {adc_write(((_X_) & 0x1),ADC_REG_BASE + ADC_IRQ_EN);} while(0)
  53
  54 #define ADC_IRQ_CLR             (0x54)
  55 #define adc_clear_irq()         do {adc_write(0x1, ADC_REG_BASE + ADC_IRQ_CLR);} while (0)
  56
  57 #define ADC_IRQ_STS             (0x58)
  58 #define adc_mask_irqstatus()     adc_read(ADC_REG_BASE + ADC_IRQ_STS)
  59
  60 #define ADC_IRQ_RAW             (0x5c)
  61 #define adc_raw_irqstatus()     adc_read(ADC_REG_BASE + ADC_IRQ_RAW)
  62
  63 #define ADC_DEBUG               (0x60)
  64
  65 /* adc global regs */
  66 #define ANA_REG_GLB_ANA_APB_CLK_EN                  (ANA_REG_BASE)
  67 #define BIT_ANA_CLK_AUXAD_EN                ( BIT_14 )
  68 #define BIT_ANA_CLK_AUXADC_EN               ( BIT_13 )
  69 #define BIT_ANA_ADC_EB                      ( BIT_5 )
  70
  71
  72 /*ADC_CTL */
  73 #define ADC_MAX_SAMPLE_NUM                      (0x10)
  74 #define BIT_SW_CH_RUN_NUM(_X_)          ((((_X_) - 1) & 0xf ) << 4)
  75 #define BIT_ADC_BIT_MODE(_X_)           (((_X_) & 0x1) << 2)    /*0: adc in 10bits mode, 1: adc in 12bits mode */
  76 #define BIT_ADC_BIT_MODE_MASK           BIT_ADC_BIT_MODE(1)
  77 #define BIT_SW_CH_ON                    ( BIT_1 ) /*WO*/
  78 #define BIT_ADC_EN                      ( BIT_0 )
  79
  80 /*ADC_SW_CH_CFG && ADC_FAST(SLOW)_HW_CHX_CFG*/
  81 #define BIT_CH_IN_MODE(_X_)             (((_X_) & 0x1) << 8)    /*0: resistance path, 1: capacitance path */
  82 #define BIT_CH_SLOW(_X_)                (((_X_) & 0x1) << 6)    /*0: quick mode, 1: slow mode */
  83 #define BIT_CH_SCALE(_X_)               (((_X_) & 0x1) << 5)    /*0: little scale, 1: big scale */
  84 #define BIT_CH_ID(_X_)                  ((_X_) & 0x1f)
  85
  86 /*ADC_FAST(SLOW)_HW_CHX_CFG*/
  87 #define BIT_CH_DLY_EN(_X_)              (((_X_) & 0x1) << 7)    /*0:disable, 1:enable */
  88
  89 /*ADC_HW_CH_DELAY*/
  90 #define BIT_HW_CH_DELAY(_X_)            ((_X_) & 0xff)  /*its unit is ADC clock */
  91 #define BIT_ADC_EB                  ( BIT_5 )
  92 #define BIT_CLK_AUXADC_EN           ( BIT_13 )
  93 #define BIT_CLK_AUXAD_EN                        ( BIT_14 )
  94
  95 #ifdef __cplusplus
  96 }
  97 #endif
  98 #endif