arch/arm/include/asm/arch-sc8800x/regs_global.h

   1 #ifndef _SC8800H_REG_GLOBAL_H_
   2     #define _SC8800H_REG_GLOBAL_H_
   3
   4 #ifdef   __cplusplus
   5     extern   "C"
   6     {
   7 #endif
   8
   9 /*----------Interrupt Control Registers----------*/
  10 #define GREG_BASE                               0x8B000000
  11
  12
  13
  14 /*----------Global Registers----------*/
  15 //GREG_BASE     0x8B000000
  16 #define GR_ADCC                                 (GREG_BASE + 0x0000)
  17 #define GR_ADCR                                 (GREG_BASE + 0x0004)
  18 #define GR_GEN0                                 (GREG_BASE + 0x0008)
  19 #define GR_PCTL                                 (GREG_BASE + 0x000C)
  20 #define GR_IRQ                                  (GREG_BASE + 0x0010)
  21 #define GR_ICLR                                 (GREG_BASE + 0x0014)
  22 #define GR_GEN1                                 (GREG_BASE + 0x0018)
  23 #define GR_GEN3                                         (GREG_BASE + 0x001C)
  24 #define GR_HWRST                                                (GREG_BASE + 0x0020)
  25 #define GR_HWRST1                               0x201007E0
  26 #define GR_MPLL_MN                              (GREG_BASE + 0x0024)
  27 #define GR_LDO_CTL0                             (GREG_BASE + 0x0028)
  28 #define GR_GEN2                                 (GREG_BASE + 0x002C)
  29 #define GR_ARM_BOOT_ADDR                        (GREG_BASE + 0x0030)
  30 #define GR_STC_STSTE                            (GREG_BASE + 0x0034)
  31 #define GR_LDO_CTL2                             (GREG_BASE + 0x0038)
  32 #define GR_ANATST_CTL                           (GREG_BASE + 0x003C)
  33 #define GR_SYS_ALM                              (GREG_BASE + 0x0040)
  34 #define GR_BUSCLK_ALM                           (GREG_BASE + 0x0044)
  35 #define GR_CLK_IIS1                                     (GREG_BASE + 0x0048)
  36 #define GR_SOFT_RST                         (GREG_BASE + 0x004C)
  37 #define GR_NFC_MEM_DLY                                  (GREG_BASE + 0x0058)
  38 #define GR_CLK_DLY                                              (GREG_BASE + 0x005C)
  39 #define GR_GEN4                         (GREG_BASE + 0x0060)
  40 #define GR_APLL_MN                                              (GREG_BASE + 0x0064)
  41 #define GR_VPLL_MN                                              (GREG_BASE + 0x0068)
  42 #define GR_LDO_CTL3                                             (GREG_BASE + 0x006C)
  43 #define GR_PLL_SCR                      (GREG_BASE + 0x0070)
  44 #define GR_CLK_EN                       (GREG_BASE + 0x0074)
  45 #define GR_TDPLL_MN                     (GREG_BASE + 0x0078)
  46 #define GR_CLK_GEN5                     (GREG_BASE + 0x007C)
  47 #define GR_DCDC_CTL                     (GREG_BASE + 0x0080)
  48 /*
  49  *   the GEN0 register bit
  50  *   */
  51 #define GEN0_WDG_EN                                     BIT_0
  52 #define GEN0_PWMC                               BIT_1
  53 #define GEN0_TIMER_EN                           BIT_2
  54 #define GEN0_SIM                                                BIT_3   //SIM module enable bit
  55 #define GEN0_I2C                                BIT_4
  56 #define GEN0_PWMB                               BIT_5
  57 #define GEN0_PWMA                               BIT_6
  58 #define GEN0_RTC                                BIT_7
  59 #define GEN0_KPD                                BIT_8
  60 #define GEN0_PWME                               BIT_9
  61 #define GEN0_MCU_DSP_RST                        BIT_10
  62 #define GEN0_MCU_SOFT_RST                       BIT_11
  63 #define GEN0_PLLPD_EN                           BIT_12
  64 #define GEN0_PWMD                                       BIT_13
  65 #define GEN0_CCIR_MCLK_EN                   BIT_14  //CCIR MCLK enable bit
  66 #define GEN0_CCIR_MCLK_SEL                      BIT_15  //CCIR MCLK select bit 1:PLL
  67 #define GEN0_EPT_EN                     BIT_15
  68 #define GEN0_SIM1_EN                    BIT_16
  69
  70
  71 /*
  72  *   the GEN1 register bit
  73  *   */
  74 #define GEN1_GEA_EN                             BIT_8
  75 #define GEN1_MPLLMN_WN                          BIT_9
  76 #define GEN1_CLK_AUX0_EN                        BIT_10
  77 #define GEN1_CLK_AUX1_EN                        BIT_11
  78 #define GEN1_TEST_MODEP_MCU                     BIT_12
  79 #define GEN1_SYSCLK_EN                          BIT_13
  80 #define GEN1_SERCLK_EB3                         BIT_14
  81 #define GEN1_CLK_26MHZ_EN                       BIT_15
  82 #define GEN1_TDPLL_MN_WE                BIT_19
  83 #define GEN1_VPLLMN_WE                  BIT_20
  84 #define GEN1_APLLMN_WE                  BIT_21
  85 #define GEN1_SERCLK_EB0                                 BIT_22
  86 #define GEN1_SERCLK_EB1                                 BIT_23
  87 #define GEN1_SERCLK_EB2                                 BIT_24
  88 #define GEN1_ARM_BOOT_MD0                               BIT_25
  89 #define GEN1_ARM_BOOT_MD1                               BIT_26
  90 #define GEN1_ARM_BOOT_MD2                               BIT_27
  91 #define GEN1_ARM_BOOT_MD3                               BIT_28
  92 #define GEN1_ARM_BOOT_MD4                               BIT_29
  93 #define GEN1_ARM_BOOT_MD5                               BIT_30
  94
  95
  96 /*MPLL related macro definition */
  97 #define PLLMN_N_MAX     0xFFF
  98 #define PLLMN_M_MAX     0xFFF
  99 #define PLLMN_N_SHIFT   16
 100 #define PLLMN_M_SHIFT   0
 101 /*
 102  *   the PCMCIA ctl register bit
 103  *   */
 104 #define PCM_EN                                                  BIT_4
 105
 106 /*
 107  *   the BUSCLK ALM register bit
 108  *   */
 109 #define ARM_VB_DA0ON                    BIT_2
 110 #define ARM_VB_DA1ON                                    BIT_3
 111 #define ARM_VB_AD0ON                                    BIT_4
 112 #define ARM_VB_AD1ON                                    BIT_5
 113 #define ARM_VB_ANAON                                    BIT_6
 114 #define ARM_VB_ACC                                              BIT_7
 115 #define ARM_VPLL_FORCE_PD               BIT_14
 116 #define ARM_APLL_FORCE_PD               BIT_15
 117
 118
 119 //UART0, UART1, UART2, UART3 registers
 120 #define ARM_UART0_BASE        0x83000000
 121 #define ARM_UART1_BASE        0x84000000
 122 #define ARM_UART2_BASE        0x8E000000
 123 #define ARM_UART3_BASE        0x8F000000
 124
 125 //NAND flash controller
 126 #define ARM_NAND_BASE         0x60000000
 127
 128 #define REG32(x) (*(volatile uint32_t *)(x))
 129
 130
 131 #ifdef   __cplusplus
 132     }
 133 #endif
 134 #endif
 135 // End