tizen 2.4 release
[kernel/u-boot-tm1.git] / arch / arm / include / asm / arch-sc8800x / regs_emc.h
1 #ifndef _SC8800H_REG_EMC_H_
2     #define _SC8800H_REG_EMC_H_
3
4 #ifdef   __cplusplus
5     extern   "C" 
6     {
7 #endif
8
9 #define EXT_MEM_CTL_BASE                0x20000000
10
11
12 #define EXT_MEM_CFG0                    (EXT_MEM_CTL_BASE + 0x0000)
13 #define EXT_MEM_CFG1                    (EXT_MEM_CTL_BASE + 0x0004)
14 #define EXT_MEM_CFG2                    (EXT_MEM_CTL_BASE + 0x0008)
15 #define EXT_MEM_CFG3                    (EXT_MEM_CTL_BASE + 0x000C)
16 #define EXT_MEM_CFG4                    (EXT_MEM_CTL_BASE + 0x0010)
17 #define EXT_MEM_STS0                    (EXT_MEM_CTL_BASE + 0x0014)
18 #define EXT_MEM_STS1                    (EXT_MEM_CTL_BASE + 0x0018)
19 #define EXT_MEM_STS2                    (EXT_MEM_CTL_BASE + 0x001C)
20
21 #define EXT_MEM_DCFG0                   (EXT_MEM_CTL_BASE + 0x0020)
22 #define EXT_MEM_DCFG1                   (EXT_MEM_CTL_BASE + 0x0024)
23 #define EXT_MEM_DCFG2                   (EXT_MEM_CTL_BASE + 0x0028)
24 #define EXT_MEM_DCFG3                   (EXT_MEM_CTL_BASE + 0x002c)
25 #define EXT_MEM_DCFG4                   (EXT_MEM_CTL_BASE + 0x0030)
26 #define EXT_MEM_DCFG5                   (EXT_MEM_CTL_BASE + 0x0034)
27 #define EXT_MEM_DCFG6                   (EXT_MEM_CTL_BASE + 0x0038)
28
29 #define EXT_MEM_SCFG0                   (EXT_MEM_CTL_BASE + 0x0040)
30 #define EXT_MEM_SCFG0_CS0               (EXT_MEM_CTL_BASE + 0x0060)
31 #define EXT_MEM_SCFG1_CS0               (EXT_MEM_CTL_BASE + 0x0064)
32 #define EXT_MEM_SCFG0_CS1               (EXT_MEM_CTL_BASE + 0x0068)
33 #define EXT_MEM_SCFG1_CS1               (EXT_MEM_CTL_BASE + 0x006C)
34 #define EXT_MEM_SCFG0_CS2               (EXT_MEM_CTL_BASE + 0x0070)
35 #define EXT_MEM_SCFG1_CS2               (EXT_MEM_CTL_BASE + 0x0074)
36 #define EXT_MEM_SCFG0_CS3               (EXT_MEM_CTL_BASE + 0x0078)
37 #define EXT_MEM_SCFG1_CS3               (EXT_MEM_CTL_BASE + 0x007C)
38
39
40 #define EXT_MEM_DL0                     (EXT_MEM_CTL_BASE + 0x0080)
41 #define EXT_MEM_DL1                     (EXT_MEM_CTL_BASE + 0x0084)
42 #define EXT_MEM_DL2                     (EXT_MEM_CTL_BASE + 0x0088)
43 #define EXT_MEM_DL3                     (EXT_MEM_CTL_BASE + 0x008C)
44 #define EXT_MEM_DL4                     (EXT_MEM_CTL_BASE + 0x0090)
45 #define EXT_MEM_DL5                     (EXT_MEM_CTL_BASE + 0x0094)
46 #define EXT_MEM_DL6                     (EXT_MEM_CTL_BASE + 0x0098)
47 #define EXT_MEM_DL7                     (EXT_MEM_CTL_BASE + 0x009C)
48 #define EXT_MEM_DL8                     (EXT_MEM_CTL_BASE + 0x00A0)
49 #define EXT_MEM_DL9                     (EXT_MEM_CTL_BASE + 0x00A4)
50 #define EXT_MEM_DL10                    (EXT_MEM_CTL_BASE + 0x00A8)
51 #define EXT_MEM_DL11                    (EXT_MEM_CTL_BASE + 0x00AC)
52 #define EXT_MEM_DL12                    (EXT_MEM_CTL_BASE + 0x00B0)
53 #define EXT_MEM_DL13                    (EXT_MEM_CTL_BASE + 0x00B4)
54 #define EXT_MEM_DL14                    (EXT_MEM_CTL_BASE + 0x00B8)
55 #define EXT_MEM_DL15                    (EXT_MEM_CTL_BASE + 0x00BC)
56 #define EXT_MEM_DL16                    (EXT_MEM_CTL_BASE + 0x00C0)
57 #define EXT_MEM_DL17                    (EXT_MEM_CTL_BASE + 0x00C4)
58 #define EXT_MEM_DL18                    (EXT_MEM_CTL_BASE + 0x00C8)
59 #define EXT_MEM_DL19                    (EXT_MEM_CTL_BASE + 0x00CC)
60 #define EXT_MEM_DL20                    (EXT_MEM_CTL_BASE + 0x00D0)
61 #define EXT_MEM_DL21                    (EXT_MEM_CTL_BASE + 0x00D4)
62 #define EXT_MEM_DL22                    (EXT_MEM_CTL_BASE + 0x00D8)
63 #define EXT_MEM_DL23                    (EXT_MEM_CTL_BASE + 0x00DC)
64 #define EXT_MEM_DL24                    (EXT_MEM_CTL_BASE + 0x00E0)
65 #define EXT_MEM_DL25                    (EXT_MEM_CTL_BASE + 0x00E4)
66 #define EXT_MEM_DL26                    (EXT_MEM_CTL_BASE + 0x00E8)
67 #define EXT_MEM_DL27                    (EXT_MEM_CTL_BASE + 0x00EC)
68 #define EXT_MEM_DL28                    (EXT_MEM_CTL_BASE + 0x00F0)
69 #define EXT_MEM_DL29                    (EXT_MEM_CTL_BASE + 0x00F4)
70 #define EXT_MEM_DL30                    (EXT_MEM_CTL_BASE + 0x00F8)
71 #define EXT_MEM_DL31                    (EXT_MEM_CTL_BASE + 0x00FC)
72
73
74 //the extenal memory control register setting under different frequency
75 #define MCU13M_ECS0_VALUE                       0x08020008
76 #define MCU13M_ECS1_VALUE                       0x08020008
77
78 #define MCU26M_ECS0_VALUE                       0x08021108
79 #define MCU26M_ECS1_VALUE                       0x08021108
80
81 #define MCU39M_ECS0_VALUE                       0x08021208
82 #define MCU39M_ECS1_VALUE                       0x08021208
83
84 #define MCU52M_ECS0_VALUE                       0x08022308
85 #define MCU52M_ECS1_VALUE                       0x08022308
86
87 #define MCU71M_ECS0_VALUE                       0x08024508
88 #define MCU71M_ECS1_VALUE                       0x08024508
89
90 #define MCU78M_ECS0_VALUE                       0x08024508
91 #define MCU78M_ECS1_VALUE                       0x08024508
92
93 #define MCU104M_ECS0_VALUE                      0x08026708
94 #define MCU104M_ECS1_VALUE                      0x08026708
95
96 #define MCU_MAX_ECS0_VALUE                      MCU104M_ECS0_VALUE
97 #define MCU_MAX_ECS1_VALUE                      MCU104M_ECS1_VALUE
98
99 #define DEFAULT_ECS_VALUE                               0x0803eeef
100 #define ECS_MAX_SUPPORT_NUMBER                  8
101
102 #define DEFAULT_INT_MEM_CTL                     0xF                     //ARM only use 0x4000_8000 - 0x4000_FFFF
103
104
105 //External Memory (8 CHIP Select).
106 #define EXTM_XCSN0_START                        0x00000000
107 #define EXTM_XCSN0_END                          0x03FFFFFF
108 #define EXTM_XCSN1_START                        0x04000000
109 #define EXTM_XCSN1_END                          0x07FFFFFF
110
111 #define EXTM_XCSN2_START                        0x08000000
112 #define EXTM_XCSN2_END                          0x0BFFFFFF
113 #define EXTM_XCSN3_START                        0x0C000000
114 #define EXTM_XCSN3_END                          0x0FFFFFFF
115
116 #define EXTM_XCSN4_START                        0x50000000
117 #define EXTM_XCSN4_END                          0x53FFFFFF
118 #define EXTM_XCSN5_START                        0x54000000
119 #define EXTM_XCSN5_END                          0x57FFFFFF
120 #define EXTM_XCSN6_START                        0x58000000
121 #define EXTM_XCSN6_END                          0x5BFFFFFF
122 #define EXTM_XCSN7_START                        0x5C000000
123 #define EXTM_XCSN7_END                          0x5FFFFFFF
124
125 #ifdef   __cplusplus
126     }
127 #endif
128 #endif
129 // End