1 #ifndef _SC8800H_REG_CPC_H_
2 #define _SC8800H_REG_CPC_H_
9 #define PIN_CTL_BASE 0x8C000000
11 #define CPC_SIMCLK0_REG (PIN_CTL_BASE + 0x0000)
12 #define CPC_SIMDA0_REG (PIN_CTL_BASE + 0x0004)
13 #define CPC_SIMRST0_REG (PIN_CTL_BASE + 0x0008)
14 #define CPC_SIMCLK1_REG (PIN_CTL_BASE + 0x000C)
15 #define CPC_SIMDA1_REG (PIN_CTL_BASE + 0x0010)
16 #define CPC_SIMRST1_REG (PIN_CTL_BASE + 0x0014)
18 #define CPC_SD0_CLK_REG (PIN_CTL_BASE + 0x0018)
19 #define CPC_SD0_CMD_REG (PIN_CTL_BASE + 0x001C)
20 #define CPC_SD0_D0_REG (PIN_CTL_BASE + 0x0020)
21 #define CPC_SD0_D1_REG (PIN_CTL_BASE + 0x0024)
22 #define CPC_SD0_D2_REG (PIN_CTL_BASE + 0x0028)
23 #define CPC_SD0_D3_REG (PIN_CTL_BASE + 0x002C)
24 #define CPC_SD1_CLK_REG (PIN_CTL_BASE + 0x0030)
25 #define CPC_SD1_CMD_REG (PIN_CTL_BASE + 0x0034)
26 #define CPC_SD1_D0_REG (PIN_CTL_BASE + 0x0038)
27 #define CPC_SD1_D1_REG (PIN_CTL_BASE + 0x003C)
28 #define CPC_SD1_D2_REG (PIN_CTL_BASE + 0x0040)
29 #define CPC_SD1_D3_REG (PIN_CTL_BASE + 0x0044)
31 #define CPC_KEYOUT0_REG (PIN_CTL_BASE + 0x0048)
32 #define CPC_KEYOUT1_REG (PIN_CTL_BASE + 0x004C)
33 #define CPC_KEYOUT2_REG (PIN_CTL_BASE + 0x0050)
34 #define CPC_KEYOUT3_REG (PIN_CTL_BASE + 0x0054)
35 #define CPC_KEYOUT4_REG (PIN_CTL_BASE + 0x0058)
36 #define CPC_KEYOUT5_REG (PIN_CTL_BASE + 0x005C)
37 #define CPC_KEYIN0_REG (PIN_CTL_BASE + 0x0060)
38 #define CPC_KEYIN1_REG (PIN_CTL_BASE + 0x0064)
39 #define CPC_KEYIN2_REG (PIN_CTL_BASE + 0x0068)
40 #define CPC_KEYIN3_REG (PIN_CTL_BASE + 0x006C)
41 #define CPC_KEYIN4_REG (PIN_CTL_BASE + 0x0070)
43 #define CPC_XTLEN_REG (PIN_CTL_BASE + 0x0074)
45 #define CPC_MTDO_REG (PIN_CTL_BASE + 0x0078)
46 #define CPC_MTDI_REG (PIN_CTL_BASE + 0x007C)
47 #define CPC_MTCK_REG (PIN_CTL_BASE + 0x0080)
48 #define CPC_MTMS_REG (PIN_CTL_BASE + 0x0084)
49 #define CPC_MTRST_REG (PIN_CTL_BASE + 0x0088)
51 #define CPC_ARMCLK_REG (PIN_CTL_BASE + 0x008C)
53 #define CPC_U0TXD_REG (PIN_CTL_BASE + 0x0090)
54 #define CPC_U0RXD_REG (PIN_CTL_BASE + 0x0094)
56 #define CPC_SCL_REG (PIN_CTL_BASE + 0x0098)
57 #define CPC_SDA_REG (PIN_CTL_BASE + 0x009C)
59 #define CPC_U1TXD_REG (PIN_CTL_BASE + 0x00A0)
60 #define CPC_U1RXD_REG (PIN_CTL_BASE + 0x00A4)
62 #define CPC_IISDI0_REG (PIN_CTL_BASE + 0x00B0)
63 #define CPC_IISDO0_REG (PIN_CTL_BASE + 0x00B4)
64 #define CPC_IISCLK0_REG (PIN_CTL_BASE + 0x00B8)
65 #define CPC_IISLRCK0_REG (PIN_CTL_BASE + 0x00BC)
66 #define CPC_IISMCK0_REG (PIN_CTL_BASE + 0x00C0)
67 #define CPC_IISDI1_REG (PIN_CTL_BASE + 0x00C4)
68 #define CPC_IISDO1_REG (PIN_CTL_BASE + 0x00C8)
69 #define CPC_IISCLK1_REG (PIN_CTL_BASE + 0x00CC)
70 #define CPC_IISLRCK1_REG (PIN_CTL_BASE + 0x00D0)
71 #define CPC_IISMCK1_REG (PIN_CTL_BASE + 0x00D4)
73 #define CPC_PBINT_REG (PIN_CTL_BASE + 0x00D8)
75 #define CPC_EMA0_REG (PIN_CTL_BASE + 0x00EC)
76 #define CPC_EMA1_REG (PIN_CTL_BASE + 0x00F0)
77 #define CPC_EMA2_REG (PIN_CTL_BASE + 0x00F4)
78 #define CPC_EMA3_REG (PIN_CTL_BASE + 0x00F8)
79 #define CPC_EMA4_REG (PIN_CTL_BASE + 0x00FC)
80 #define CPC_EMA5_REG (PIN_CTL_BASE + 0x0100)
81 #define CPC_EMA6_REG (PIN_CTL_BASE + 0x0104)
82 #define CPC_EMA7_REG (PIN_CTL_BASE + 0x0108)
83 #define CPC_EMA8_REG (PIN_CTL_BASE + 0x010C)
84 #define CPC_EMA9_REG (PIN_CTL_BASE + 0x0110)
85 #define CPC_EMA10_REG (PIN_CTL_BASE + 0x0114)
86 #define CPC_EMA11_REG (PIN_CTL_BASE + 0x0118)
87 #define CPC_EMA12_REG (PIN_CTL_BASE + 0x011C)
88 #define CPC_EMD16_REG (PIN_CTL_BASE + 0x0120)
89 #define CPC_EMD17_REG (PIN_CTL_BASE + 0x0124)
90 #define CPC_EMD18_REG (PIN_CTL_BASE + 0x0128)
91 #define CPC_EMD19_REG (PIN_CTL_BASE + 0x012C)
92 #define CPC_EMD20_REG (PIN_CTL_BASE + 0x0130)
93 #define CPC_EMD21_REG (PIN_CTL_BASE + 0x0134)
94 #define CPC_EMD22_REG (PIN_CTL_BASE + 0x0138)
95 #define CPC_EMD23_REG (PIN_CTL_BASE + 0x013C)
96 #define CPC_EMD24_REG (PIN_CTL_BASE + 0x0140)
97 #define CPC_EMD25_REG (PIN_CTL_BASE + 0x0144)
98 #define CPC_EMD26_REG (PIN_CTL_BASE + 0x0148)
99 #define CPC_EMD27_REG (PIN_CTL_BASE + 0x014C)
100 #define CPC_EMD28_REG (PIN_CTL_BASE + 0x0150)
101 #define CPC_EMD29_REG (PIN_CTL_BASE + 0x0154)
102 #define CPC_EMD30_REG (PIN_CTL_BASE + 0x0158)
103 #define CPC_EMD31_REG (PIN_CTL_BASE + 0x015C)
104 #define CPC_EMRAS_N_REG (PIN_CTL_BASE + 0x0160)
105 #define CPC_EMCAS_N_REG (PIN_CTL_BASE + 0x0164)
106 #define CPC_EMWE_N_REG (PIN_CTL_BASE + 0x0168)
107 #define CPC_CLKDPMEM_REG (PIN_CTL_BASE + 0x016C)
108 #define CPC_CLKDMMEM_REG (PIN_CTL_BASE + 0x0170)
109 #define CPC_EMDQM0_REG (PIN_CTL_BASE + 0x0174)
110 #define CPC_EMDQM1_REG (PIN_CTL_BASE + 0x0178)
111 #define CPC_EMDQM2_REG (PIN_CTL_BASE + 0x017C)
112 #define CPC_EMDQM3_REG (PIN_CTL_BASE + 0x0180)
113 #define CPC_EMCS_N0_REG (PIN_CTL_BASE + 0x0184)
114 #define CPC_EMCS_N1_REG (PIN_CTL_BASE + 0x0188)
115 #define CPC_EMCS_N2_REG (PIN_CTL_BASE + 0x018C)
116 #define CPC_EMCS_N3_REG (PIN_CTL_BASE + 0x0190)
117 #define CPC_EMCKE0_REG (PIN_CTL_BASE + 0x0194)
118 #define CPC_EMCKE1_REG (PIN_CTL_BASE + 0x0198)
119 #define CPC_EMBA0_REG (PIN_CTL_BASE + 0x019C)
120 #define CPC_EMBA1_REG (PIN_CTL_BASE + 0x01A0)
121 #define CPC_EMDQS0_REG (PIN_CTL_BASE + 0x01A4)
122 #define CPC_EMDQS1_REG (PIN_CTL_BASE + 0x01A8)
123 #define CPC_EMDQS2_REG (PIN_CTL_BASE + 0x01AC)
124 #define CPC_EMDQS3_REG (PIN_CTL_BASE + 0x01B0)
125 #define CPC_EMD0_REG (PIN_CTL_BASE + 0x01B4)
126 #define CPC_EMD1_REG (PIN_CTL_BASE + 0x01B8)
127 #define CPC_EMD2_REG (PIN_CTL_BASE + 0x01BC)
128 #define CPC_EMD3_REG (PIN_CTL_BASE + 0x01C0)
129 #define CPC_EMD4_REG (PIN_CTL_BASE + 0x01C4)
130 #define CPC_EMD5_REG (PIN_CTL_BASE + 0x01C8)
131 #define CPC_EMD6_REG (PIN_CTL_BASE + 0x01CC)
132 #define CPC_EMD7_REG (PIN_CTL_BASE + 0x01D0)
133 #define CPC_EMD8_REG (PIN_CTL_BASE + 0x01D4)
134 #define CPC_EMD9_REG (PIN_CTL_BASE + 0x01D8)
135 #define CPC_EMD10_REG (PIN_CTL_BASE + 0x01DC)
136 #define CPC_EMD11_REG (PIN_CTL_BASE + 0x01E0)
137 #define CPC_EMD12_REG (PIN_CTL_BASE + 0x01E4)
138 #define CPC_EMD13_REG (PIN_CTL_BASE + 0x01E8)
139 #define CPC_EMD14_REG (PIN_CTL_BASE + 0x01EC)
140 #define CPC_EMD15_REG (PIN_CTL_BASE + 0x01F0)
142 #define CPC_NFWPN_REG (PIN_CTL_BASE + 0x01F4)
143 #define CPC_LCMRSTN_REG (PIN_CTL_BASE + 0x01F8)
144 #define CPC_NFRB_REG (PIN_CTL_BASE + 0x01FC)
145 #define CPC_LCMCD_REG (PIN_CTL_BASE + 0x0200)
146 #define CPC_NFCLE_REG (PIN_CTL_BASE + 0x0204)
147 #define CPC_NFALE_REG (PIN_CTL_BASE + 0x0208)
148 #define CPC_NFCEN_REG (PIN_CTL_BASE + 0x020C)
149 #define CPC_NFWEN_REG (PIN_CTL_BASE + 0x0210)
150 #define CPC_NFREN_REG (PIN_CTL_BASE + 0x0214)
151 #define CPC_NFD0_REG (PIN_CTL_BASE + 0x0218)
152 #define CPC_NFD1_REG (PIN_CTL_BASE + 0x021C)
153 #define CPC_NFD2_REG (PIN_CTL_BASE + 0x0220)
154 #define CPC_NFD3_REG (PIN_CTL_BASE + 0x0224)
155 #define CPC_NFD4_REG (PIN_CTL_BASE + 0x0228)
156 #define CPC_NFD5_REG (PIN_CTL_BASE + 0x022C)
157 #define CPC_NFD6_REG (PIN_CTL_BASE + 0x0230)
158 #define CPC_NFD7_REG (PIN_CTL_BASE + 0x0234)
159 #define CPC_NFD8_REG (PIN_CTL_BASE + 0x0238)
161 #define CPC_LCMCSN0_REG (PIN_CTL_BASE + 0x023C)
162 #define CPC_LCMCSN1_REG (PIN_CTL_BASE + 0x0240)
163 #define CPC_LCD_RSTN_REG (PIN_CTL_BASE + 0x0244)
164 #define CPC_LCD_EN_REG (PIN_CTL_BASE + 0x0248)
165 #define CPC_LCD_D0_REG (PIN_CTL_BASE + 0x024C)
166 #define CPC_LCD_D1_REG (PIN_CTL_BASE + 0x0250)
167 #define CPC_LCD_D2_REG (PIN_CTL_BASE + 0x0254)
168 #define CPC_LCD_D3_REG (PIN_CTL_BASE + 0x0258)
169 #define CPC_LCD_D4_REG (PIN_CTL_BASE + 0x025C)
170 #define CPC_LCD_D5_REG (PIN_CTL_BASE + 0x0260)
171 #define CPC_LCD_D6_REG (PIN_CTL_BASE + 0x0264)
172 #define CPC_LCD_D7_REG (PIN_CTL_BASE + 0x0268)
173 #define CPC_LCD_D8_REG (PIN_CTL_BASE + 0x026C)
174 #define CPC_LCD_HS_REG (PIN_CTL_BASE + 0x0270)
175 #define CPC_LCD_VS_REG (PIN_CTL_BASE + 0x0274)
176 #define CPC_CLK_LCD_REG (PIN_CTL_BASE + 0x0278)
178 #define CPC_CCIRCK_REG (PIN_CTL_BASE + 0x0280)
179 #define CPC_CCIRHS_REG (PIN_CTL_BASE + 0x0284)
180 #define CPC_CCIRVS_REG (PIN_CTL_BASE + 0x0288)
181 #define CPC_CCIRD0_REG (PIN_CTL_BASE + 0x028C)
182 #define CPC_CCIRD1_REG (PIN_CTL_BASE + 0x0290)
183 #define CPC_CCIRD2_REG (PIN_CTL_BASE + 0x0294)
184 #define CPC_CCIRD3_REG (PIN_CTL_BASE + 0x0298)
185 #define CPC_CCIRD4_REG (PIN_CTL_BASE + 0x029C)
186 #define CPC_CCIRD5_REG (PIN_CTL_BASE + 0x02A0)
187 #define CPC_CCIRD6_REG (PIN_CTL_BASE + 0x02A4)
188 #define CPC_CCIRD7_REG (PIN_CTL_BASE + 0x02A8)
189 #define CPC_CCIRD8_REG (PIN_CTL_BASE + 0x02AC)
190 #define CPC_CCIRD9_REG (PIN_CTL_BASE + 0x02B0)
191 #define CPC_CCIRRST_REG (PIN_CTL_BASE + 0x02B4)
192 #define CPC_CCIRPD_REG (PIN_CTL_BASE + 0x02B8)
194 #define CPC_HRESET_N_REG (PIN_CTL_BASE + 0x02BC)
196 #define CPC_RFSDA0_REG (PIN_CTL_BASE + 0x02C0)
197 #define CPC_RFSCK0_REG (PIN_CTL_BASE + 0x02C4)
198 #define CPC_RFSEN0_0_REG (PIN_CTL_BASE + 0x02C8)
199 #define CPC_RFSEN0_1_REG (PIN_CTL_BASE + 0x02CC)
200 #define CPC_RFSDA1_REG (PIN_CTL_BASE + 0x02D0)
201 #define CPC_RFSCK1_REG (PIN_CTL_BASE + 0x02D4)
202 #define CPC_RFSEN1_0_REG (PIN_CTL_BASE + 0x02D8)
203 #define CPC_RFSEN1_1_REG (PIN_CTL_BASE + 0x02DC)
204 #define CPC_RFCTL0_REG (PIN_CTL_BASE + 0x02E0)
205 #define CPC_RFCTL1_REG (PIN_CTL_BASE + 0x02E4)
206 #define CPC_RFCTL2_REG (PIN_CTL_BASE + 0x02E8)
207 #define CPC_RFCTL3_REG (PIN_CTL_BASE + 0x02EC)
208 #define CPC_RFCTL4_REG (PIN_CTL_BASE + 0x02F0)
209 #define CPC_RFCTL5_REG (PIN_CTL_BASE + 0x02F4)
210 #define CPC_RFCTL6_REG (PIN_CTL_BASE + 0x02F8)
211 #define CPC_RFCTL7_REG (PIN_CTL_BASE + 0x02FC)
212 #define CPC_RFCTL8_REG (PIN_CTL_BASE + 0x0300)
213 #define CPC_RFCTL9_REG (PIN_CTL_BASE + 0x0304)
214 #define CPC_RFCTL10_REG (PIN_CTL_BASE + 0x0308)
215 #define CPC_RFCTL11_REG (PIN_CTL_BASE + 0x030C)
216 #define CPC_RFCTL12_REG (PIN_CTL_BASE + 0x0310)
217 #define CPC_RFCTL13_REG (PIN_CTL_BASE + 0x0314)
218 #define CPC_RFCTL14_REG (PIN_CTL_BASE + 0x0318)
219 #define CPC_RFCTL15_REG (PIN_CTL_BASE + 0x031C)
221 #define CPC_CCIR_SEL_REG (PIN_CTL_BASE + 0x0320)
223 #define CPC_SD_SEL_REG (PIN_CTL_BASE + 0x0324)
225 #define CPC_KEYOUT6_REG (PIN_CTL_BASE + 0x0328)
226 #define CPC_KEYOUT7_REG (PIN_CTL_BASE + 0x032C)
228 #define CPC_LCD_D9_REG (PIN_CTL_BASE + 0x0338)
229 #define CPC_LCD_D10_REG (PIN_CTL_BASE + 0x033C)
230 #define CPC_LCD_D11_REG (PIN_CTL_BASE + 0x0340)
231 #define CPC_LCD_D12_REG (PIN_CTL_BASE + 0x0344)
232 #define CPC_LCD_D13_REG (PIN_CTL_BASE + 0x0348)
233 #define CPC_LCD_D14_REG (PIN_CTL_BASE + 0x034C)
234 #define CPC_LCD_D15_REG (PIN_CTL_BASE + 0x0350)
235 #define CPC_LCD_D16_REG (PIN_CTL_BASE + 0x0354)
236 #define CPC_LCD_D17_REG (PIN_CTL_BASE + 0x0358)
237 #define CPC_SD1_D4_REG (PIN_CTL_BASE + 0x035C)
238 #define CPC_SD1_D5_REG (PIN_CTL_BASE + 0x0360)
239 #define CPC_SD1_D6_REG (PIN_CTL_BASE + 0x0364)
240 #define CPC_SD1_D7_REG (PIN_CTL_BASE + 0x0368)
242 #define CPC_NFD9_REG CPC_LCD_D9_REG
243 #define CPC_NFD10_REG CPC_LCD_D10_REG
244 #define CPC_NFD11_REG CPC_LCD_D11_REG
245 #define CPC_NFD12_REG CPC_LCD_D12_REG
246 #define CPC_NFD13_REG CPC_LCD_D13_REG
247 #define CPC_NFD14_REG CPC_LCD_D14_REG
248 #define CPC_NFD15_REG CPC_LCD_D15_REG
projects / kernel / u-boot-tm1.git / blob