1 #ifndef _SC8800H_REG_AHB_H_
2 #define _SC8800H_REG_AHB_H_
9 #define AHB_REG_BASE 0x20900200
11 #define AHB_CTL0 (AHB_REG_BASE + 0x00)
12 #define AHB_CTL1 (AHB_REG_BASE + 0x04)
13 #define AHB_CTL2 (AHB_REG_BASE + 0x08)
14 #define AHB_RESERVED (AHB_REG_BASE + 0x0c)
15 #define AHB_SOFT_RST (AHB_REG_BASE + 0x10)
16 #define AHB_STOP_CTL (AHB_REG_BASE + 0x14)
17 #define AHB_REMAP (AHB_REG_BASE + 0x18)
18 #define AHB_INT_STS (AHB_REG_BASE + 0x1c)
19 #define AHB_INT_CLR (AHB_REG_BASE + 0x20)
20 #define AHB_AHB_ARM_CLK (AHB_REG_BASE + 0x24)
21 #define AHB_BOND_OPT (AHB_REG_BASE + 0x28)
22 #define AHB_TD_CLK (AHB_REG_BASE + 0x2c)
23 #define AHB_RFT_CLK (AHB_REG_BASE + 0x30)
24 #define AHB_DSP_WAKEUP (AHB_REG_BASE + 0x80)
25 #define AHB_DSP_BOOT_EN (AHB_REG_BASE + 0x84)
26 #define AHB_DSP_BOOT_VECTOR (AHB_REG_BASE + 0x88)
27 #define AHB_DSP_RESET (AHB_REG_BASE + 0x8C)
28 #define AHB_ARM_POWERDOWN_EN (AHB_REG_BASE + 0x40)
30 #define AHB_DMA_SOFT_RST BIT_0
32 #define CHIP_TYPE 0x209003FC
34 /* AHB_AHB_ARM_CLK related macro definition */
35 #define AHB_CLK_DIV_MAX 0x1F
36 #define ARM_CLK_DIV_MAX 0x1F
37 #define EMC_CLK_DIV_MAX 0x1F
38 #define XAHB_CLK_DIV_MAX 0x7
39 #define AHB_CLK_DIV_SHIFT 5
40 #define ARM_CLK_DIV_SHIFT 0
41 #define EMC_CLK_DIV_SHIFT 10
42 #define XAHB_CLK_DIV_SHIFT 15
45 typedef union _ahb_ctl0_reg_tag {
46 struct _ahb_ctl0_reg_map {
47 volatile unsigned int clk_apb_div :5; //BIT_31-27
48 volatile unsigned int reserved1 :7; //BIT_26-20
49 volatile unsigned int usb_sdio_priority :1; //BIT_19
50 volatile unsigned int drm_eb :1; //BIT_18
51 volatile unsigned int em_no_tr :1; //BIT_17
52 volatile unsigned int ahb_sleep_bypass :1; //BIT_16
53 volatile unsigned int reserved2 :1; //BIT_15
54 volatile unsigned int rot_eb :1; //BIT_14
55 volatile unsigned int mea_eb :1; //BIT_13
56 volatile unsigned int dct_eb :1; //BIT_12
57 volatile unsigned int mon1_eb :1; //BIT_11
58 volatile unsigned int tic_eb :1; //BIT_10
59 volatile unsigned int lcm_eb :1; //BIT_9
60 volatile unsigned int nfc_eb :1; //BIT_8
61 volatile unsigned int mon0_eb :1; //BIT_7
62 volatile unsigned int dma_eb :1; //BIT_6
63 volatile unsigned int usbd_eb :1; //BIT_5
64 volatile unsigned int tve_eb :1; //BIT_4
65 volatile unsigned int lcdc_eb :1; //BIT_3
66 volatile unsigned int ccir_eb :1; //BIT_2
67 volatile unsigned int isp_eb :1; //BIT_1
68 volatile unsigned int apb_stop :1; //BIT_0
70 volatile unsigned int dwValue ;
73 typedef union _ahb_soft_rst_reg_tag {
74 struct _ahb_soft_rst_reg_map {
75 volatile unsigned int reserved1 :16;//reserved
76 volatile unsigned int mea_soft_rst :1; //BIT_15
77 volatile unsigned int dct_soft_rst :1; //BIT_14
78 volatile unsigned int drm_soft_rst :1; //BIT_13
79 volatile unsigned int sd_soft_rst :1; //BIT_12
80 volatile unsigned int emc_soft_rst :1; //BIT_11
81 volatile unsigned int rot_soft_rst :1; //BIT_10
82 volatile unsigned int reserved :2; //BIT_8/9
83 volatile unsigned int usbd48m_soft_rst :1; //BIT_7
84 volatile unsigned int usbd12m_soft_rst :1; //BIT_6
85 volatile unsigned int nfc_soft_rst :1; //BIT_5
86 volatile unsigned int tve_soft_rst :1; //BIT_4
87 volatile unsigned int lcdc_soft_rst :1; //BIT_3
88 volatile unsigned int ccir_soft_rst :1; //BIT_2
89 volatile unsigned int isp_soft_rst :1; //BIT_1
90 volatile unsigned int dma_soft_rst :1; //BIT_0
92 volatile unsigned int dwValue;