arch/arm/include/asm/arch-sc8800g/sc8800g_reg_base.h

   1 /******************************************************************************
   2  ** File Name:      sc8800g_reg_base.h                                            *
   3  ** Author:         Tim.Luo                                                   *
   4  ** DATE:           07/08/2010                                                *
   5  ** Copyright:      2010 Spreadtrum, Incoporated. All Rights Reserved.        *
   6  ** Description:                                                              *
   7  **                                                                           *
   8  ******************************************************************************
   9
  10  ******************************************************************************
  11  **                        Edit History                                       *
  12  ** ------------------------------------------------------------------------- *
  13  ** DATE           NAME             DESCRIPTION                               *
  14  ** 07/08/2010     Tim.Luo          Create.                                   *
  15   ******************************************************************************/
  16
  17 #ifndef _SC8800G_REG_BASE_H_
  18 #define _SC8800G_REG_BASE_H_
  19
  20 #ifdef   __cplusplus
  21 extern   "C"
  22 {
  23 #endif
  24 /**---------------------------------------------------------------------------*
  25  **                         Constant Variables                                *
  26  **---------------------------------------------------------------------------*/
  27 /*----------memory map address----------*/
  28 //Memory Address Map.
  29
  30 #define SHARE_MEM_BEGIN                 0x50000000    //Internal Shared Memory.
  31 #define SHARE_MEM_END                   0x50000fff    //The address of the last byte
  32
  33 #define INTER_RAM_BEGIN                 0x40000000    //Internal ram
  34 #define INTER_RAM_END                   0x4000A7FF    //The address of the last byte
  35
  36 #define DSP_MEM_BEGIN                   0x00400000    //DSP memory base address.
  37 #define DSP_MEM_LEN                     0x00400000    //length unit:byte.
  38
  39
  40 //CONTROL REGISTER
  41 #define EXTERNAL_MEM_CTL_BEGIN          0x20000000    //External Memory Control registers.
  42 #define EXTERNAL_MEM_CTL_END            0x200001FC
  43
  44 #define DMA_GEN_CTL_BEGIN               0x20100000    //DMA General Control registers.
  45 #define DMA_GEN_CTL_END                 0x201000C4
  46
  47 #define DMA_CHA_CTL_BEGIN               0x20100400    //DMA Channel Control registers.
  48 #define DMA_CHA_CTL_END                 0x201007FC
  49
  50 #define DCAM_CTL_BEGIN                  0x20200000    //DCAM Control registers.
  51 #define DCAM_CTL_END                    0x202027FF    //the begin address of the last word
  52
  53 #define ROTATION_CTL_BEGIN              0x20800200    //ROTATION Device Space.
  54 #define ROTATION_CTL_END                0x2080022C    //length unit:word.
  55
  56 #define USB_CTL_BEGIN                   0x20300000    //USB Device Space.
  57 #define USB_CTL_END                     0x20300E00    //the begin address of the last word
  58
  59 #define BUS_MON0_CTL_BEGIN              0x20400000    //Bus Monitor 0 Control registers.
  60 #define BUS_MON0_CTL_END                0x20400024    //The address of the last byte
  61
  62 #define BUS_MON1_CTL_BEGIN              0x20401000    //Bus Monitor 1 Control registers.
  63 #define BUS_MON1_CTL_END                0x20401024    //The address of the last byte
  64
  65
  66 #define AHB_GEN_CTL_BEGIN               0x20900200    //Bus Monitor Control registers.
  67 #define AHB_GEN_CTL_END                 0x209002A0
  68
  69 #define CHIP_ID_BEGIN                   0x209003FC    //CHIP ID registers.
  70 #define CHIP_ID_END                     0x209003FC
  71
  72 #define NAND_LCM_CTL_BEGIN              0x60001C00    //NAND Flash and LCM Control Registers
  73 #define NAND_LCM_CTL_END                0x60001D44
  74
  75 #define LCDC_CTL_BEGIN                  0x20700000    //LCDC Control Registers
  76 #define LCDC_CTL_END                    0x2070012C    //length unit:word.
  77
  78 #define LCDC_LCM_CTL_BEGIN              0x20700140    //LCDC/LCM Control Registers
  79 #define LCDC_LCM_CTL_END                0x20700194    //length unit:word.
  80
  81 #define INT_CTL_BEGIN                   0x80003000    //Interrupt Control Registers
  82 #define INT_CTL_END                     0x80000040    //the begin address of the last word
  83
  84 #define TIMER_CNT_BEGIN                 0x81000000    //tiemr counter Registers
  85 #define TIMER_CNT_END                   0x8100004C    //the begin address of the last word
  86
  87 #define ADI_CTL_BEGAIN                  0x82000000  //adi master control registers
  88 #define ADI_CTL_END                     0x82000034
  89
  90 #define UART0_CTL_BEGIN                 0x83000000    //UART0,SPI0 Control Registers
  91 #define UART0_CTL_END                   0x8300002C    //the begin address of the last word
  92
  93 #define UART1_CTL_BEGIN                 0x84000000    //UART1,SPI1 Control Registers
  94 #define UART1_CTL_END                   0x8400002C    //the begin address of the last word
  95
  96 #define UART2_CTL_BEGIN                 0x8E000000    //UART2,SPI2 Control Registers
  97 #define UART2_CTL_END                   0x8E00002C    //the begin address of the last word
  98
  99 #define SIM0_CTL_BEGIN                  0x85000000    //SIMCARD Control Registers
 100 #define SIM0_CTL_END                    0x85000038    //the begin address of the last word
 101
 102 #define SIM1_CTL_BEGIN                  0x85003000    //SIMCARD Control Registers
 103 #define SIM1_CTL_END                    0x85003038    //the begin address of the last word
 104
 105
 106 #define I2C_CTL_BEGIN                   0x86000000    //I2C Control Registers
 107 #define I2C_CTL_END                     0x86000014    //the begin address of the last word
 108
 109 #define KEYPAD_CTL_BEGIN                0x87000000    //Keypad Control Registers
 110 #define KEYPAD_CTL_END                  0x87000038    //the begin address of the last word
 111
 112 #define SYS_CNT_BEGIN                   0x87003000    //system counter Registers
 113 #define SYS_CNT_END                     0x87003008    //the begin address of the last word
 114
 115 #define PWM_CTL_BEGIN                   0x88000000    //Keypad Control Registers
 116 #define PWM_CTL_END                     0x88000070    //the begin address of the last word
 117
 118 #define RTC_CTL_BEGIN                   0x82000080    //RTC Control Registers
 119 #define RTC_CTL_END                     0x820000BC    //the begin address of the last word
 120
 121 #define WATDOG_CTL_BEGIN                0x82000040    //watchdog Control Registers
 122 #define WATDOG_CTL_END                  0x82000060    //the begin address of the last word
 123
 124 #define GPIO_CTL_BEGIN                  0x8A000000    //GPIO Control Registers              ///digital die
 125 #define GPIO_CTL_END                    0x8A0004A4
 126
 127 #define GLOBAL_CTL_BEGIN                0x8B000000    //GLOBAL Control Registers
 128 #define GLOBAL_CTL_END                  0x8B000080    //the begin address of the last word
 129
 130 #define CHIPPIN_CTL_BEGIN               0x8C000000    //ChipPin Control Registers
 131 #define CHIPPIN_CTL_END                 0x8C0003EC
 132
 133 #define VOICE_BAND_CODEC_BEGIN          0x82000100    //Voice Band Codec register       ///digital die
 134 #define VOICE_BAND_CODEC_END            0x82000154
 135
 136
 137 /*----------Peripheral Address Space------------*/
 138 #define INTC_BASE                       0x80003000
 139 #define TIMER_CTL_BASE                  0x81000000  //Timer0 (RTC)
 140 #define ADI_BASE                        0x82000000  //ADI master
 141 #define WDG_BASE                        0x82000040  //Analog die register
 142 #define RTC_BASE                        0x82000080
 143 #define ANA_DOLPHIN_BASE                0x82000100  //Analog die register
 144 #define ANA_PINMAP_BASE                 0x82000180
 145 #define TPC_BASE                        0x82000280
 146 #define ADC_BASE                        0x82000300
 147 #define ANA_INTC_BASE                   0x82000380
 148 #define ANA_REG_BASE                    0x82000480
 149 #define ANA_GPIO_BASE                   0x82000600
 150 #define ARM_VBC_BASE                    0x82003000
 151 #define ARM_UART0_BASE                  0x83000000
 152 #define ARM_UART1_BASE                  0x84000000
 153 #define ARM_UART2_BASE                  0x8E000000
 154 #define SIM0_BASE                       0x85000000  //SIM0
 155 #define SIM1_BASE                       0x85003000  //SIM1
 156 #define I2C_BASE                        0x86000000
 157 #define KPD_BASE                        0x87000000
 158 #define SYSTIMER_BASE                   0x87003000  //System timer
 159 #define PWM_BASE                        0x88000000
 160 #define EFUSE_BASE                      0x89000000  //efuse
 161 #define GPIO_BASE                       0x8A000000
 162 #define GREG_BASE                       0x8B000000  //Global Registers
 163 #define PIN_CTL_BASE                    0x8C000000
 164 #define ANA_PIN_CTL_BASE                0x82000180
 165 #define EPT_BASE                        0x8D000000
 166 #define PCM_CTL_BASE                    0x8E001000
 167 #define SPI_BASE                        0x8E002000
 168
 169
 170 #define INT_REG_BASE                    INTC_BASE
 171 #define EXT_MEM_CTL_BASE                0x20000000
 172 #define DMA_REG_BASE                    0x20100000
 173 #define DCAM_BASE                       0x20200000
 174 #define USB_REG_BASE                    0x20300000
 175 #define BUS_MONx_CTL_BASE               0x20400000
 176 #define BUS_MON0_CTL_BASE               0x20400000
 177 #define BUS_MON1_CTL_BASE               0x20401000
 178 #define BUS_MON2_CTL_BASE               0x20402000
 179 #define BUS_MON_CTL_BASE                BUS_MON0_CTL_BASE
 180
 181 #define SDIO0_BASE_ADDR                 0x20500000
 182 #define SDIO1_BASE_ADDR                 0x20500100
 183 #define REG_LCDC_REG_BASE               0x20700000
 184 #define LCM_REG_BASE                    0x20700140
 185 #define ROT_REG_BASE                    0x20800200
 186 #define NAND_CTL_BASE                   0x60001c00
 187 #define NF_LCM_CTL_BEGIN                0x60000000      //NAND Flash and LCM Control Registers
 188
 189
 190
 191 #define GEA_BASE    EPT_BASE
 192 #ifdef   __cplusplus
 193 }
 194 #endif
 195
 196 #endif  //_SC6800H_REG_H_
 197