1 /******************************************************************************
2 ** File Name: emc_reg_v3.h *
3 ** Author: haiyang.hu *
5 ** Copyright: 2009 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 06/15/2007 Daniel.Ding Create. *
13 ** 05/07/2010 Mingwei.zhang Modify it for SC8800G. *
14 ******************************************************************************/
15 #ifndef _EMC_REG_V3_H_
16 #define _EMC_REG_V3_H_
17 /*----------------------------------------------------------------------------*
19 **-------------------------------------------------------------------------- */
21 /**---------------------------------------------------------------------------*
23 **---------------------------------------------------------------------------*/
28 /**----------------------------------------------------------------------------*
30 **----------------------------------------------------------------------------*/
31 #define BIT_RANGE(_bit_h,_bit_l) ((_bit_h)-(_bit_l)+1)
33 /*----------external memory cotnrol registers----------*/
35 #define EXT_MEM_CFG0 (EXT_MEM_CTL_BASE + 0x0000)
36 #define EXT_MEM_CFG1 (EXT_MEM_CTL_BASE + 0x0004)
37 //temp for nor_fdl and driver_export and asm_cvt
38 #define EXT_MEM_CTL0 (EXT_MEM_CTL_BASE + 0x0000)
39 #define EXT_MEM_CTL1 (EXT_MEM_CTL_BASE + 0x0004)
41 #define EMC_REG_STS0_ADDR (EXT_MEM_CTL_BASE + 0x0008)
43 #define EXT_MEM_CFG0_CS0 (EXT_MEM_CTL_BASE + 0x0010)
44 #define EXT_MEM_CFG0_CS1 (EXT_MEM_CTL_BASE + 0x0014)
45 #define EXT_MEM_CFG0_CS2 (EXT_MEM_CTL_BASE + 0x0018)
46 #define EXT_MEM_CFG0_CS3 (EXT_MEM_CTL_BASE + 0x001c)
48 #define EXT_MEM_INI (EXT_MEM_CTL_BASE + 0x0020)
50 #define EXT_MEM_CFG0_CH0 (EXT_MEM_CTL_BASE + 0x0030)
51 #define EXT_MEM_CFG0_CH1 (EXT_MEM_CTL_BASE + 0x0034)
52 #define EXT_MEM_CFG0_CH2 (EXT_MEM_CTL_BASE + 0x0038)
53 #define EXT_MEM_CFG0_CH3 (EXT_MEM_CTL_BASE + 0x003c)
54 #define EXT_MEM_CFG0_CH4 (EXT_MEM_CTL_BASE + 0x0040)
55 #define EXT_MEM_CFG0_CH5 (EXT_MEM_CTL_BASE + 0x0044)
56 #define EXT_MEM_CFG0_CH6 (EXT_MEM_CTL_BASE + 0x0048)
57 #define EXT_MEM_CFG0_CH7 (EXT_MEM_CTL_BASE + 0x004c)
58 #define EXT_MEM_CFG0_CH8 (EXT_MEM_CTL_BASE + 0x0050)
59 #define EXT_MEM_CFG0_CH9 (EXT_MEM_CTL_BASE + 0x0054)
60 #define EXT_MEM_CFG0_CH10 (EXT_MEM_CTL_BASE + 0x0058)
61 #define EXT_MEM_CFG0_CH11 (EXT_MEM_CTL_BASE + 0x005c)
62 #define EXT_MEM_CFG0_CH12 (EXT_MEM_CTL_BASE + 0x0060)
63 #define EXT_MEM_CFG0_CH13 (EXT_MEM_CTL_BASE + 0x0064)
64 #define EXT_MEM_CFG0_CH14 (EXT_MEM_CTL_BASE + 0x0068)
65 #define EXT_MEM_CFG0_CH15 (EXT_MEM_CTL_BASE + 0x006c)
68 #define EXT_MEM_STS2 (EXT_MEM_CTL_BASE + 0x0078)
69 #define EXT_MEM_STS3 (EXT_MEM_CTL_BASE + 0x007c)
73 #define EXT_MEM_DL0 (EXT_MEM_CTL_BASE + 0x00c0)
74 #define EXT_MEM_DL1 (EXT_MEM_CTL_BASE + 0x00c4)
75 #define EXT_MEM_DL2 (EXT_MEM_CTL_BASE + 0x00c8)
76 #define EXT_MEM_DL3 (EXT_MEM_CTL_BASE + 0x00cC)
77 #define EXT_MEM_DL4 (EXT_MEM_CTL_BASE + 0x00d0)
78 #define EXT_MEM_DL5 (EXT_MEM_CTL_BASE + 0x00d4)
79 #define EXT_MEM_DL6 (EXT_MEM_CTL_BASE + 0x00d8)
80 #define EXT_MEM_DL7 (EXT_MEM_CTL_BASE + 0x00dC)
82 #define EXT_MEM_DL16 (EXT_MEM_CTL_BASE + 0x0100)
83 #define EXT_MEM_DL17 (EXT_MEM_CTL_BASE + 0x0104)
84 #define EXT_MEM_DL18 (EXT_MEM_CTL_BASE + 0x0108)
85 #define EXT_MEM_DL19 (EXT_MEM_CTL_BASE + 0x010C)
86 #define EXT_MEM_DL20 (EXT_MEM_CTL_BASE + 0x0110)
87 #define EXT_MEM_DL21 (EXT_MEM_CTL_BASE + 0x0114)
88 #define EXT_MEM_DL22 (EXT_MEM_CTL_BASE + 0x0118)
89 #define EXT_MEM_DL23 (EXT_MEM_CTL_BASE + 0x011c)
90 #define EXT_MEM_DL24 (EXT_MEM_CTL_BASE + 0x0120)
91 #define EXT_MEM_DL25 (EXT_MEM_CTL_BASE + 0x0124)
92 #define EXT_MEM_DL26 (EXT_MEM_CTL_BASE + 0x0128)
93 #define EXT_MEM_DL27 (EXT_MEM_CTL_BASE + 0x012c)
97 #define EXT_MEM_DCFG0 (EXT_MEM_CTL_BASE + 0x0140)
98 #define EXT_MEM_DCFG1 (EXT_MEM_CTL_BASE + 0x0144)
99 #define EXT_MEM_DCFG2 (EXT_MEM_CTL_BASE + 0x0148)
100 #define EXT_MEM_DCFG3 (EXT_MEM_CTL_BASE + 0x014c)
101 #define EXT_MEM_DCFG4 (EXT_MEM_CTL_BASE + 0x0150)
102 #define EXT_MEM_DCFG5 (EXT_MEM_CTL_BASE + 0x0154)
103 #define EXT_MEM_DCFG6 (EXT_MEM_CTL_BASE + 0x0158)
104 #define EXT_MEM_DCFG7 (EXT_MEM_CTL_BASE + 0x015c)
108 #define EXT_MEM_SCFG0 (EXT_MEM_CTL_BASE + 0x0170)
109 #define EXT_MEM_SCFG1 (EXT_MEM_CTL_BASE + 0x0174)
111 #define EXT_MEM_SCFG0_CS0 (EXT_MEM_CTL_BASE + 0x0180)
112 #define EXT_MEM_SCFG0_CS1 (EXT_MEM_CTL_BASE + 0x0190)
113 #define EXT_MEM_SCFG0_CS2 (EXT_MEM_CTL_BASE + 0x01A0)
114 #define EXT_MEM_SCFG0_CS3 (EXT_MEM_CTL_BASE + 0x01B0)
116 #define EXT_MEM_SCFG1_CS0 (EXT_MEM_CTL_BASE + 0x0184)
117 #define EXT_MEM_SCFG1_CS1 (EXT_MEM_CTL_BASE + 0x0194)
118 #define EXT_MEM_SCFG1_CS2 (EXT_MEM_CTL_BASE + 0x01A4)
119 #define EXT_MEM_SCFG1_CS3 (EXT_MEM_CTL_BASE + 0x01B4)
121 #define EXT_MEM_SCFG2_CS0 (EXT_MEM_CTL_BASE + 0x0188)
122 #define EXT_MEM_SCFG2_CS1 (EXT_MEM_CTL_BASE + 0x0198)
123 #define EXT_MEM_SCFG2_CS2 (EXT_MEM_CTL_BASE + 0x01A8)
124 #define EXT_MEM_SCFG2_CS3 (EXT_MEM_CTL_BASE + 0x01B8)
126 #define EXT_MEM_SCFG3_CS0 (EXT_MEM_CTL_BASE + 0x018C)
127 #define EXT_MEM_SCFG3_CS1 (EXT_MEM_CTL_BASE + 0x019C)
128 #define EXT_MEM_SCFG3_CS2 (EXT_MEM_CTL_BASE + 0x01AC)
129 #define EXT_MEM_SCFG3_CS3 (EXT_MEM_CTL_BASE + 0x01BC)
131 #define EMC_REG_CFG0_BASE_VALUE (0x00000141)
132 #define EMC_REG_CFG1_BASE_VALUE (0x0000000C)
133 #define EMC_REG_SCFG0_BASE_VALUE (0x00FF0000)
134 #define EMC_REG_SCFG1_BASE_VALUE (0x00001111)
135 #define EMC_REG_CS_CFG_BASE_VALUE (0x00000000)
136 #define EMC_REG_CS_SCFG0_BASE_VALUE (0x00100030)
137 #define EMC_REG_CS_SCFG1_BASE_VALUE (0x00007F7F)
138 #define EMC_REG_CS_SCFG2_BASE_VALUE (0x00A0744F)
139 #define EMC_REG_CS_SCFG3_BASE_VALUE (0x01224112)
140 #define EMC_CS_ADDR_SIZE (0x4000000)
141 #define EMC_DELAY_IN_CHIP (10)
142 #define EMC_CLK_MAX (192) /*MHZ*/
143 #define EMC_CS_NUM_MAX_SUPPORT (EMC_CS4) /*3 is temp code for iram limit */
146 /**----------------------------------------------------------------------------*
148 **----------------------------------------------------------------------------*/
149 #if defined(CHIP_ENDIAN_LITTLE)
154 volatile uint mode_r :
156 volatile uint mode_w :
158 volatile uint single_split_r :
160 volatile uint single_split_w :
162 volatile uint clk_mode :
164 volatile uint reserved1 :
166 volatile uint wait_en_r :
168 volatile uint wait_en_w :
170 volatile uint wait_pol :
172 volatile uint cre_pol :
174 volatile uint cre_mode :
176 volatile uint cre_en :
178 volatile uint row_detect_en_r :
180 volatile uint row_detect_en_w :
182 volatile uint row_length :
184 volatile uint admux_en :
186 volatile uint reserved2 :
189 volatile uint32 reg_value;
196 volatile uint t_first_r :
198 volatile uint t_next_r :
200 volatile uint reserved1 :
202 volatile uint t_first_w :
204 volatile uint t_next_w :
206 volatile uint reserved2 :
209 volatile uint32 reg_value;
216 volatile uint t_adswt_r :
218 volatile uint t_adswt_w :
220 volatile uint t_oe_stp_r :
222 volatile uint reserved1 :
224 volatile uint t_we_stp_w :
226 volatile uint reserved2 :
228 volatile uint t_we_wdt_w :
230 volatile uint t_ce_stp_r :
232 volatile uint t_ce_stp_w :
234 volatile uint t_adv_stp_r :
236 volatile uint t_adv_stp_w :
238 volatile uint t_adv_wdt_r :
240 volatile uint t_adv_wdt_w :
242 volatile uint t_adv_mode_r :
244 volatile uint t_adv_mode_w :
246 volatile uint reserved3 :
249 volatile uint32 reg_value;
256 volatile uint t_sample_stp :
258 volatile uint t_sample_dly_r :
260 volatile uint t_sample_phase_r :
262 volatile uint t_sample_dly_w :
264 volatile uint t_sample_phase_w :
266 volatile uint t_wait_ie_stp :
268 volatile uint t_wait_mask_dly_r :
270 volatile uint reserved1 :
272 volatile uint t_wait_mask_dly_w :
274 volatile uint reserved2 :
276 volatile uint t_wait_dly_r :
278 volatile uint t_wait_dly_w :
280 volatile uint t_valid_phase_r :
282 volatile uint t_valid_phase_w :
285 volatile uint32 reg_value;
292 volatile uint hburst_ren :
294 volatile uint hburst_wen :
296 volatile uint dburst_rmode :
298 volatile uint dburst_wmode :
300 volatile uint dburst_rlength :
302 volatile uint reserved1 :
304 volatile uint dburst_wlength :
306 volatile uint reserved2 :
308 volatile uint mem_sel :
310 volatile uint reserved3 :
313 volatile uint32 reg_value;
320 volatile uint clksmem0_out_en :
322 volatile uint clksmem1_out_en :
324 volatile uint clksmem0_out_mode :
326 volatile uint clksmem1_out_mode :
328 volatile uint clksmem0_out_sel :
330 volatile uint clksmem1_out_sel :
332 volatile uint clksmem0_out_pol :
334 volatile uint clksmem1_out_pol :
336 volatile uint clksmem0_out_gate_en :
338 volatile uint clksmem1_out_gate_en :
340 volatile uint clksmem0_out_gate_mode :
342 volatile uint clksmem1_out_gate_mode :
344 volatile uint sample_auto_rst_en :
346 volatile uint sample_rst :
348 volatile uint wait_timeout_thr :
350 volatile uint wait_timeout_en :
352 volatile uint smem_wait_timeout_reg :
354 volatile uint reserved :
357 volatile uint32 reg_value;
364 volatile uint reserved2 :
366 volatile uint admux_en :
368 volatile uint row_length :
370 volatile uint row_detect_en_w :
372 volatile uint row_detect_en_r :
374 volatile uint cre_en :
376 volatile uint cre_mode :
378 volatile uint cre_pol :
380 volatile uint wait_pol :
382 volatile uint wait_en_w :
384 volatile uint wait_en_r :
386 volatile uint reserved1 :
388 volatile uint clk_mode :
390 volatile uint single_split_w :
392 volatile uint single_split_r :
394 volatile uint mode_w :
396 volatile uint mode_r :
399 volatile uint32 reg_value;
406 volatile uint reserved2 :
408 volatile uint t_next_w :
410 volatile uint t_first_w :
412 volatile uint reserved1 :
414 volatile uint t_next_r :
416 volatile uint t_first_r :
419 volatile uint32 reg_value;
426 volatile uint reserved3 :
428 volatile uint t_adv_mode_w :
430 volatile uint t_adv_mode_r :
432 volatile uint t_adv_wdt_w :
434 volatile uint t_adv_wdt_r :
436 volatile uint t_adv_stp_w :
438 volatile uint t_adv_stp_r :
440 volatile uint t_ce_stp_w :
442 volatile uint t_ce_stp_r :
444 volatile uint t_we_wdt_w :
446 volatile uint reserved2 :
448 volatile uint t_we_stp_w :
450 volatile uint reserved1 :
452 volatile uint t_oe_stp_r :
454 volatile uint t_adswt_w :
456 volatile uint t_adswt_r :
459 volatile uint32 reg_value;
466 volatile uint t_valid_phase_w :
468 volatile uint t_valid_phase_r :
470 volatile uint t_wait_dly_w :
472 volatile uint t_wait_dly_r :
474 volatile uint reserved2 :
476 volatile uint t_wait_mask_dly_w :
478 volatile uint reserved1 :
480 volatile uint t_wait_mask_dly_r :
482 volatile uint t_wait_ie_stp :
484 volatile uint t_sample_phase_w :
486 volatile uint t_sample_dly_w :
488 volatile uint t_sample_phase_r :
490 volatile uint t_sample_dly_r :
492 volatile uint t_sample_stp :
495 volatile uint32 reg_value;
502 volatile uint reserved3 :
504 volatile uint mem_sel :
506 volatile uint reserved2 :
508 volatile uint dburst_wlength :
510 volatile uint reserved1 :
512 volatile uint dburst_rlength :
514 volatile uint dburst_wmode :
516 volatile uint dburst_rmode :
518 volatile uint hburst_wen :
520 volatile uint hburst_ren :
523 volatile uint32 reg_value;
530 volatile uint reserved :
532 volatile uint smem_wait_timeout_reg :
534 volatile uint wait_timeout_en :
536 volatile uint wait_timeout_thr :
538 volatile uint sample_rst :
540 volatile uint sample_auto_rst_en :
542 volatile uint clksmem1_out_gate_mode :
544 volatile uint clksmem0_out_gate_mode :
546 volatile uint clksmem1_out_gate_en :
548 volatile uint clksmem0_out_gate_en :
550 volatile uint clksmem1_out_pol :
552 volatile uint clksmem0_out_pol :
554 volatile uint clksmem1_out_sel :
556 volatile uint clksmem0_out_sel :
558 volatile uint clksmem1_out_mode :
560 volatile uint clksmem0_out_mode :
562 volatile uint clksmem1_out_en :
564 volatile uint clksmem0_out_en :
567 volatile uint32 reg_value;
571 /**----------------------------------------------------------------------------*
572 ** Local Function Prototype **
573 **----------------------------------------------------------------------------*/
574 #define EMC_WAIT_WRITEBUFFER_DONE while(REG32(EMC_REG_STS0_ADDR) & BIT_0);
575 /**----------------------------------------------------------------------------*
576 ** Function Prototype **
577 **----------------------------------------------------------------------------*/
580 /**----------------------------------------------------------------------------*
582 **----------------------------------------------------------------------------*/
586 /**---------------------------------------------------------------------------*/
587 #endif //_EMC_REG_V3_H_