2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
37 #if defined CONFIG_SC8830
38 #define SVC_STACK_TEMP 0x5000CFF0 //for shark
39 #define SPL_STACK 0x808f0000
40 #elif defined CONFIG_SC8825
41 #define SVC_STACK_TEMP 0x00027F60 //for tiger
42 #define SPL_STACK 0x808f0000
44 #define SVC_STACK_TEMP 0x40008000
45 #define SPL_STACK 0x008f0000
49 #ifdef CONFIG_PRELOADER
50 /* No exception handlers in preloader */
82 #ifdef CONFIG_NAND_SC7710G2
110 /* pad to 64 byte boundary */
119 ldr pc, _undefined_instruction
120 ldr pc, _software_interrupt
121 ldr pc, _prefetch_abort
127 _undefined_instruction: .word undefined_instruction
128 _software_interrupt: .word software_interrupt
129 _prefetch_abort: .word prefetch_abort
130 _data_abort: .word data_abort
131 _not_used: .word not_used
134 _pad: .word 0x12345678 /* now 16*4=64 */
138 #endif /* CONFIG_PRELOADER */
140 .balignl 16,0xdeadbeef
141 /*************************************************************************
143 * Startup Code (reset vector)
145 * do important init only if we don't start from memory!
146 * setup Memory and board specific bits prior to relocation.
147 * relocate armboot to ram
150 *************************************************************************/
154 .word CONFIG_SYS_TEXT_BASE
157 * These are defined in the board-specific linker script.
159 .globl _bss_start_ofs
161 .word __bss_start - _start
167 #ifdef CONFIG_USE_IRQ
168 /* IRQ stack memory (calculated at run-time) */
169 .globl IRQ_STACK_START
173 /* IRQ stack memory (calculated at run-time) */
174 .globl FIQ_STACK_START
179 /* IRQ stack memory (calculated at run-time) + 8 bytes */
180 .globl IRQ_STACK_START_IN
185 * the actual reset code
190 * set the cpu to SVC32 mode
192 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
193 #ifdef SPRD_EVM_TAG_ON
194 ldr r0,=SPRD_EVM_ADDR_START
205 /* the mask ROM code should have PLL and others stable */
207 #ifndef CONFIG_NAND_SPL
210 time: subs r1,r1,#0x1
214 mrc p15, 0, r1, c1, c0, 0
216 mcr p15, 0, r1, c1, c0, 0
226 mcr p15, 0, r0, c12, c0, 0
227 #if !defined(CONFIG_FPGA)
229 * Enable coherent requested to the processor.
231 mrc p15, 0, r0, c1, c0, 1
233 mcr p15, 0, r0, c1, c0, 1 @write aux control register
234 #endif /* CONFIG_ARCH_SCX35L*/
236 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
239 /*set up temp stack*/
240 LDR sp, =SVC_STACK_TEMP
246 The sp here must be in the reserved region
252 /* Set stackpointer in internal RAM to call board_init_f */
254 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
255 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
256 #ifndef CONFIG_NAND_SPL
260 ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
262 ldr r2, =(CONFIG_SYS_TEXT_BASE)
266 /*------------------------------------------------------------------------------*/
269 * void relocate_code (addr_sp, gd, addr_moni)
271 * This "function" does not return, instead it continues in RAM
272 * after relocating the monitor code.
277 mov r4, r0 /* save addr_sp */
278 mov r5, r1 /* save addr of gd */
279 mov r6, r2 /* save addr of destination */
281 /* Set up the stack */
286 ldr r6, =(CONFIG_SYS_TEXT_BASE)
289 beq clear_bss /* skip relocation */
290 mov r1, r6 /* r1 <- scratch for copy loop */
292 ldr r3, _bss_start_ofs
293 add r2, r0, r3 /* r2 <- source end address */
296 ldmia r0!, {r9-r10} /* copy from source address [r0] */
297 stmia r1!, {r9-r10} /* copy to target address [r1] */
298 cmp r0, r2 /* until source end address [r2] */
301 #ifndef CONFIG_PRELOADER
303 * fix .rel.dyn relocations
305 ldr r0, _TEXT_BASE /* r0 <- Text base */
306 sub r9, r6, r0 /* r9 <- relocation offset */
307 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
308 add r10, r10, r0 /* r10 <- sym table in FLASH */
309 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
310 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
311 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
312 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
314 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
315 add r0, r0, r9 /* r0 <- location to fix up in RAM */
318 cmp r7, #23 /* relative fixup? */
320 cmp r7, #2 /* absolute fixup? */
322 /* ignore unknown type of fixup */
325 /* absolute fix: set location to (offset) symbol value */
326 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
327 add r1, r10, r1 /* r1 <- address of symbol in table */
328 ldr r1, [r1, #4] /* r1 <- symbol value */
329 add r1, r1, r9 /* r1 <- relocated sym addr */
332 /* relative fix: increase location by offset */
337 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
343 #ifndef CONFIG_PRELOADER
344 ldr r0, _bss_start_ofs
346 ldr r3, _TEXT_BASE /* Text base */
347 mov r4, r6 /* reloc addr */
350 mov r2, #0x00000000 /* clear */
352 clbss_l:str r2, [r0] /* clear loop... */
362 * We are done. Do not return, instead branch to second part of board
363 * initialization, now running from RAM.
366 #ifdef CONFIG_NAND_SPL
367 ldr r0, _nand_boot_ofs
373 ldr r0, _board_init_r_ofs
377 /* setup parameters for board_init_r */
378 mov r0, r5 /* gd_t */
379 mov r1, r6 /* dest_addr */
384 .word board_init_r - _start
388 .word __rel_dyn_start - _start
390 .word __rel_dyn_end - _start
392 .word __dynsym_start - _start
394 /*************************************************************************
396 * CPU_init_critical registers
398 * setup important registers
399 * setup memory timing
401 *************************************************************************/
406 mov r0, #0 @ set up for MCR
407 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
408 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
411 * disable MMU stuff and caches
413 mrc p15, 0, r0, c1, c0, 0
414 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
415 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
416 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
417 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
418 mcr p15, 0, r0, c1, c0, 0
421 * Jump to board specific initialization...
422 * The Mask ROM will have already initialized
423 * basic memory. Go here to bump up clock rate and handle
424 * wake up conditions.
426 mov ip, lr @ persevere link reg across call
427 @ bl lowlevel_init @ go setup pll,mux,memory
428 mov lr, ip @ restore link
429 mov pc, lr @ back to my caller
432 *************************************************************************
436 *************************************************************************
441 #define S_FRAME_SIZE 72
463 #define MODE_SVC 0x13
467 * use bad_save_user_regs for abort/prefetch/undef/swi ...
468 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
471 .macro bad_save_user_regs
472 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
474 stmia sp, {r0 - r12} @ Save user registers (now in
476 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
478 ldmia r2, {r2 - r3} @ get values for "aborted" pc
479 @ and cpsr (into parm regs)
480 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
484 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
485 mov r0, sp @ save current stack into r0
489 .macro irq_save_user_regs
490 sub sp, sp, #S_FRAME_SIZE
491 stmia sp, {r0 - r12} @ Calling r0-r12
492 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
493 @ a reserved stack spot would
495 stmdb r8, {sp, lr}^ @ Calling SP, LR
496 str lr, [r8, #0] @ Save calling PC
498 str r6, [r8, #4] @ Save CPSR
499 str r0, [r8, #8] @ Save OLD_R0
503 .macro irq_restore_user_regs
504 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
506 ldr lr, [sp, #S_PC] @ Get PC
507 add sp, sp, #S_FRAME_SIZE
508 subs pc, lr, #4 @ return & move spsr_svc into
513 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
516 str lr, [r13] @ save caller lr in position 0
518 mrs lr, spsr @ get the spsr
519 str lr, [r13, #4] @ save spsr in position 1 of
522 mov r13, #MODE_SVC @ prepare SVC-Mode
524 msr spsr, r13 @ switch modes, make sure
526 mov lr, pc @ capture return pc
527 movs pc, lr @ jump to next instruction &
531 .macro get_bad_stack_swi
532 sub r13, r13, #4 @ space on current stack for
534 str r0, [r13] @ save R0's value.
535 ldr r0, IRQ_STACK_START_IN @ get data regions start
536 @ spots for abort stack
537 str lr, [r0] @ save caller lr in position 0
539 mrs r0, spsr @ get the spsr
540 str lr, [r0, #4] @ save spsr in position 1 of
542 ldr r0, [r13] @ restore r0
543 add r13, r13, #4 @ pop stack entry
546 .macro get_irq_stack @ setup IRQ stack
547 ldr sp, IRQ_STACK_START
550 .macro get_fiq_stack @ setup FIQ stack
551 ldr sp, FIQ_STACK_START
557 #ifdef CONFIG_PRELOADER
560 ldr sp, _TEXT_BASE /* switch to abort stack */
562 bl 1b /* hang and never return */
563 #else /* !CONFIG_PRELOADER */
565 undefined_instruction:
568 bl do_undefined_instruction
574 bl do_software_interrupt
594 #ifdef CONFIG_USE_IRQ
601 irq_restore_user_regs
606 /* someone ought to write a more effective fiq_save_user_regs */
609 irq_restore_user_regs
626 #endif /* CONFIG_PRELOADER */