arch/arm/cpu/armv7/sc9630/misc.c

   1 #include <common.h>
   2 #include <asm/io.h>
   3 #include <asm/arch/sprd_reg.h>
   4 #include <asm/arch/sci_types.h>
   5 #include <asm/arch/adi_hal_internal.h>
   6 /*
   7         REG_AON_APB_BOND_OPT0  ==> romcode set
   8         REG_AON_APB_BOND_OPT1  ==> set it later
   9
  10         !!! notice: these two registers can be set only one time!!!
  11
  12         B1[0] : B0[0]
  13         0     : 0     Jtag enable
  14         0     : 1     Jtag disable
  15         1     : 0     Jtag enable
  16         1     : 1     Jtag enable
  17 */
  18
  19 /*************************************************
  20 * 1 : enable jtag success                        *
  21 * 0 : enable jtag fail                           *
  22 *************************************************/
  23 int sprd_jtag_enable()
  24 {
  25         if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)
  26         {
  27                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 1;
  28                 if (!((*(volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1))
  29                         return 0;
  30         }
  31         return 1;
  32 }
  33
  34 /*************************************************
  35 * 1 : disable jtag success                       *
  36 * 0 : disable jtag fail                          *
  37 *************************************************/
  38 int sprd_jtag_disable()
  39 {
  40         if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1))
  41         {
  42                 return 0;
  43         }
  44         else
  45         {
  46                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 0;
  47                 if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1)
  48                         return 0;
  49                 else
  50                         return 1;
  51         }
  52 }
  53
  54 static void ap_slp_cp_dbg_cfg()
  55 {
  56         *((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug
  57 }
  58
  59 static void ap_cpll_rel_cfg()
  60 {
  61 #if !defined(CONFIG_ARCH_SCX35L)
  62         *((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL;
  63 #endif
  64 }
  65
  66 static void bb_bg_auto_en()
  67 {
  68         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
  69 }
  70
  71
  72 static void ap_close_wpll_en()
  73 {
  74 #if !defined(CONFIG_ARCH_SCX35L)
  75        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN;
  76 #endif
  77 }
  78
  79 static void ap_close_cpll_en()
  80 {
  81 #if !defined(CONFIG_ARCH_SCX35L)
  82        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN;
  83 #endif
  84 }
  85
  86 static void ap_close_wifipll_en()
  87 {
  88 #if !defined(CONFIG_ARCH_SCX35L)
  89        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN;
  90 #endif
  91 }
  92
  93
  94 static void bb_ldo_auto_en()
  95 {
  96         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9;
  97 }
  98
  99 #ifdef CONFIG_PBINT_7S_RESET_V1
 100
 101 #define PBINT_7S_HW_FLAG (BIT(7))
 102 #define PBINT_7S_SW_FLAG (BIT(12))
 103
 104 #define CONFIG_7S_RESET_SW_FLAG
 105 #ifdef CONFIG_7S_RESET_SW_FLAG
 106 static u32 pbint_7s_flag = 0;
 107 #endif
 108 int is_7s_reset(void)
 109 {
 110 #ifdef CONFIG_7S_RESET_SW_FLAG
 111         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 112 #else
 113         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 114 #endif
 115 }
 116
 117 int is_7s_reset_for_systemdump(void)
 118 {
 119         int val;
 120         /* FIXME flag? */
 121         int mask = PBINT_7S_SW_FLAG | PBINT_7S_HW_FLAG;
 122         /* some chip just care software flag */
 123         int chip_id = ANA_GET_CHIP_ID();
 124         if (((chip_id >> 16) & 0xFFFF) == 0x2711) {
 125                 if ((chip_id & 0xFFFF) <= 0xA100) {
 126                         mask = PBINT_7S_SW_FLAG;
 127                 }
 128         }
 129 #ifdef CONFIG_7S_RESET_SW_FLAG
 130         val = pbint_7s_flag & mask;
 131 #else
 132         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 133 #endif
 134         return (val == PBINT_7S_SW_FLAG);
 135 }
 136
 137 static inline int pbint_7s_rst_disable(uint32 disable)
 138 {
 139         if (disable) {
 140                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 141         } else {
 142                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 143         }
 144         return 0;
 145 }
 146 static inline int pbint_7s_rst_set_2keymode(uint32 mode)
 147 {
 148 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 149         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xA000) {
 150                 if (!mode) {
 151                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 152                 } else {
 153                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 154                 }
 155         } else {
 156                 if (!mode) {
 157                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 158                 } else {
 159                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 160                 }
 161         }
 162 #else
 163 #error "please check pbint_7s_rst_set_2keymode reg"
 164 #endif
 165         return 0;
 166 }
 167 static inline int pbint_7s_rst_set_sw(uint32 mode)
 168 {
 169         if (mode) {
 170                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 171         } else {
 172                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 173         }
 174         return 0;
 175 }
 176
 177 static inline int pbint_7s_rst_set_swmode(uint32 mode)
 178 {
 179         if (mode) {
 180                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 181         } else {
 182                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 183         }
 184         return 0;
 185 }
 186
 187 static inline int pbint_7s_rst_set_threshold(uint32 th)
 188 {
 189         int mask = BITS_PBINT_7S_RST_THRESHOLD(-1);
 190         int shift = ffs(mask) - 1;
 191
 192         if (th>0) th--;
 193         sci_adi_write(ANA_REG_GLB_POR_7S_CTRL, (th << shift) & mask, mask);
 194         return 0;
 195 }
 196
 197 int pbint_7s_rst_cfg(uint32 en, uint32 sw_rst, uint32 short_rst)
 198 {
 199 #ifdef CONFIG_7S_RESET_SW_FLAG
 200         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 201         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 202         udelay(10);
 203         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 204 #endif
 205         /* ignore sw_rst, please refer to config.h */
 206         if (en) {
 207                 pbint_7s_rst_set_threshold(CONFIG_7S_RST_THRESHOLD);
 208                 pbint_7s_rst_set_sw(!sw_rst);
 209
 210                 pbint_7s_rst_set_swmode(short_rst);
 211
 212                 pbint_7s_rst_set_2keymode(CONFIG_7S_RST_2KEY_MODE);
 213         }
 214         return pbint_7s_rst_disable(!en);
 215 }
 216 #elif defined CONFIG_PBINT_7S_RESET_V0
 217
 218 #define PBINT_7S_HW_FLAG (BIT(7))
 219 #define PBINT_7S_SW_FLAG (BIT(12))
 220
 221 #define CONFIG_7S_RESET_SW_FLAG
 222 #ifdef CONFIG_7S_RESET_SW_FLAG
 223 static u32 pbint_7s_flag = 0;
 224 #endif
 225 int is_7s_reset(void)
 226 {
 227 #ifdef CONFIG_7S_RESET_SW_FLAG
 228         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 229 #else
 230         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 231 #endif
 232 }
 233
 234 int is_7s_reset_for_systemdump(void)
 235 {
 236         int val;
 237         int mask = PBINT_7S_SW_FLAG;
 238 #ifdef CONFIG_7S_RESET_SW_FLAG
 239         val = pbint_7s_flag & mask;
 240 #else
 241         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 242 #endif
 243         return (val == mask);
 244 }
 245
 246 void pbint_7s_rst_cfg(uint32 en_rst, uint32 sw_rst, uint32 short_rst)
 247 {
 248         uint16 reg_data = ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL);
 249
 250 #ifdef CONFIG_7S_RESET_SW_FLAG
 251         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 252         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 253         udelay(10);
 254         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 255 #endif
 256
 257         if (!en_rst)
 258         {
 259                 reg_data |=  BIT_PBINT_7S_RST_DISABLE;
 260         }
 261         else
 262         {
 263                 reg_data &= ~BIT_PBINT_7S_RST_DISABLE;
 264                 /* software reset */
 265                 if (!sw_rst)
 266                 {
 267                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCSET;
 268                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCCLR;
 269                 }
 270                 else
 271                 {
 272                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCSET;
 273                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCCLR;
 274                 }
 275                 /* 7s short reset */
 276                 if (short_rst)
 277                 {
 278                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCSET;
 279                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 280                 }
 281                 else
 282                 {
 283                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCSET;
 284                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 285                 }
 286         }
 287         ANA_REG_SET(ANA_REG_GLB_POR_7S_CTRL, reg_data);
 288         printf("ANA_REG_GLB_POR_7S_CTRL:%04X\r\n", ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL));
 289 }
 290 #endif
 291
 292 #ifdef CONFIG_OF_LIBFDT
 293 void scx35_pmu_reconfig(void)
 294 {
 295         /* FIXME:
 296          * turn on gpu/mm domain for clock device initcall, and then turn off asap.
 297          */
 298         __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
 299                      & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
 300                      REG_PMU_APB_PD_MM_TOP_CFG);
 301 #ifndef CONFIG_FPGA
 302     while (__raw_readl(REG_PMU_APB_PWR_STATUS0_DBG) & 0xf0000000) {};
 303 #endif
 304         __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
 305                      & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
 306                      REG_PMU_APB_PD_GPU_TOP_CFG);
 307 #ifndef CONFIG_FPGA
 308     while (__raw_readl(REG_PMU_APB_PWR_STATUS0_DBG) & 0x0f000000) {};
 309 #endif
 310         __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB |
 311                      BIT_GPU_EB, REG_AON_APB_APB_EB0);
 312 #ifndef CONFIG_FPGA
 313         __raw_writel(__raw_readl(REG_MM_AHB_RF_AHB_EB) | BIT_CKG_EB,
 314                      REG_MM_AHB_RF_AHB_EB);
 315         __raw_writel(__raw_readl(REG_MM_AHB_RF_GEN_CKG_CFG)
 316                      | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
 317                      REG_MM_AHB_RF_GEN_CKG_CFG);
 318 #endif
 319
 320 #ifndef CONFIG_FPGA
 321         __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
 322                      REG_MM_CLK_MM_AHB_CFG);
 323 #endif
 324 }
 325
 326 #else
 327 void scx35_pmu_reconfig(void) {}
 328 #endif
 329 inline int is_hw_smpl_enable(void)
 330 {
 331 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 332         return !!(sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_EN);
 333 #endif
 334         return 0;
 335 }
 336
 337 #ifdef CONFIG_SMPL_MODE
 338 #define CONFIG_SMPL_SW_FLAG
 339 #ifdef CONFIG_SMPL_SW_FLAG
 340 static u32 smpl_flag = 0;
 341 #endif
 342 int is_smpl_bootup(void)
 343 {
 344 #ifdef CONFIG_SMPL_SW_FLAG
 345         if( 0x2723A090 == ANA_GET_CHIP_ID() ){
 346                 return smpl_flag & BIT_SMPL_PWR_ON_FLAG;
 347         }
 348         else{
 349             return 0;
 350         }
 351 #else
 352         return sci_adi_read(ANA_REG_GLB_BA_CTRL1) & BIT_IS_SMPL_ON;
 353 #endif
 354 }
 355
 356 #define SMPL_MODE_ENABLE_SET    (0x1935)
 357 static int smpl_config(void)
 358 {
 359         u32 val;
 360         if( 0x2723A090 != ANA_GET_CHIP_ID() ){
 361            return 0;
 362         }
 363         val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
 364 #ifdef CONFIG_SMPL_THRESHOLD
 365         val |= BITS_SMPL_THRESHOLD(CONFIG_SMPL_THRESHOLD);
 366 #endif
 367 #ifdef CONFIG_SMPL_SW_FLAG
 368         smpl_flag = sci_adi_read(ANA_REG_GLB_SMPL_CTRL1);
 369         sci_adi_set(ANA_REG_GLB_SMPL_CTRL1, BIT_SMPL_PWR_ON_FLAG_CLR);
 370 #endif
 371         return sci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
 372 }
 373 #else
 374 inline int is_smpl_bootup(void)
 375 {
 376         return 0;
 377 }
 378
 379 inline static int smpl_config(void)
 380 {
 381         return 0;
 382 }
 383 #endif
 384
 385 void pmic_init(void)
 386 {
 387         pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN,
 388                                 CONFIG_7S_RST_SW_MODE,
 389                                 CONFIG_7S_RST_SHORT_MODE);
 390         smpl_config();
 391         sci_adi_set(ANA_REG_GLB_LDO_SHPT_PD2, BIT_LDO_VIBR_SHPT_PD);    //close vibr short protection
 392 }
 393 void misc_init()
 394 {
 395         scx35_pmu_reconfig();
 396         ap_slp_cp_dbg_cfg();
 397         ap_cpll_rel_cfg();
 398 #ifndef  CONFIG_SPX15
 399         ap_close_wpll_en();
 400         ap_close_cpll_en();
 401         ap_close_wifipll_en();
 402 #endif
 403         bb_bg_auto_en();
 404         bb_ldo_auto_en();
 405
 406         pmic_init();
 407 }
 408
 409 typedef struct mem_cs_info
 410 {
 411         uint32 cs_number;
 412         uint32 cs0_size;//bytes
 413         uint32 cs1_size;//bytes
 414 }mem_cs_info_t;
 415 PUBLIC int get_dram_cs_number(void)
 416 {
 417         mem_cs_info_t *cs_info_ptr = 0x1C00;
 418         return cs_info_ptr->cs_number;
 419 }
 420 PUBLIC int get_dram_cs0_size(void)
 421 {
 422         mem_cs_info_t *cs_info_ptr = 0x1C00;
 423         return cs_info_ptr->cs0_size;
 424 }