arch/arm/cpu/armv7/sc8830/umctl_fpga.c

   1 /******************************************************************************
   2  ** File Name:      umctl2.c                                                  *
   3  ** Author:         changde                                                   *
   4  ** DATE:           01/06/2013                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    Refer to uMCTL2 databook for detail                       *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 01/06/2013     changde.li       Create.                                   *
  14  ******************************************************************************/
  15
  16 #include <asm/arch-sc8830/umctl2_reg_fpga.h>
  17 #include <asm/arch-sc8830/dram_phy_fpga.h>
  18
  19 /*With unit of Mhz*/
  20 #define          SDRAM_CORE_CLK 200
  21 /**---------------------------------------------------------------------------*
  22  **                            Macro Define
  23  **---------------------------------------------------------------------------*/
  24 #define REG32(x)                           (*((volatile uint32 *)(x)))
  25 #define UMCTL_REG_GET(reg_addr)             (*((volatile uint32 *)(reg_addr)))
  26 #define UMCTL_REG_SET( reg_addr, value )    *(volatile uint32 *)(reg_addr) = value
  27
  28 #define OPERATION_MODE_INIT 0x01
  29 #define OPERATION_MODE_NORMAL 0x02
  30 #define OPERATION_MODE_PD 0x03
  31 #define OPERATION_MODE_SR 0x04
  32 #define OPERATION_MODE_DPD 0x05
  33
  34 #define NS2CLK(x_ns) ((SDRAM_CORE_CLK*x_ns)/1000 + 1)
  35
  36 /**---------------------------------------------------------------------------*
  37  **                            Extern Declare
  38  **---------------------------------------------------------------------------*/
  39 extern MEM_IODS_E IO_DS;
  40 extern DRAM_BURSTTYPE_E BURST_TYPE;
  41 const uint32 SDRAM_BASE = 0x80000000;
  42 /**---------------------------------------------------------------------------*
  43  **                            Local Variables
  44  **---------------------------------------------------------------------------*/
  45
  46 /**---------------------------------------------------------------------------*
  47  **                            Local Functions
  48  **---------------------------------------------------------------------------*/
  49
  50 static uint32 reg_bits_set(uint32 addr,
  51                            uint8 start_bitpos, uint8 bit_num, uint32 value)
  52 {
  53         /*create bit mask according to input param */
  54         uint32 bit_mask = (1 << bit_num) - 1;
  55         uint32 reg_data = *((volatile uint32 *)(addr));
  56
  57         reg_data &= ~(bit_mask << start_bitpos);
  58         reg_data |= ((value & bit_mask) << start_bitpos);
  59
  60         *((volatile uint32 *)(addr)) = reg_data;
  61 }
  62
  63 static uint32 ns_to_xclock(uint32 time_ns)
  64 {
  65         uint32 clk_num = (SDRAM_CORE_CLK * time_ns) / 1000 + 1;
  66         return (clk_num);
  67 }
  68
  69 static uint32 us_to_xclock(uint32 time_us)
  70 {
  71         uint32 clk_num = (SDRAM_CORE_CLK * time_us);
  72         return (clk_num);
  73 }
  74
  75 static uint32 ns_to_x1024(uint32 time_ns)
  76 {
  77         uint32 clk_num = (SDRAM_CORE_CLK * time_ns) / 1000 + 1;
  78         return (clk_num / 1024 + 1);
  79 }
  80
  81 static uint32 us_to_x1024(uint32 time_us)
  82 {
  83         uint32 clk_num = (SDRAM_CORE_CLK * time_us);
  84         return (clk_num / 1024 + 1);
  85 }
  86
  87 static uint32 ms_to_x1024(uint32 time_ms)
  88 {
  89         uint32 clk_num = (SDRAM_CORE_CLK * time_ms) * 1000;
  90         return (clk_num / 1024 + 1);
  91 }
  92
  93 static uint32 ns_to_x32(uint32 time_ns)
  94 {
  95         uint32 clk_num = (SDRAM_CORE_CLK * time_ns) / 1000 + 1;
  96         return (clk_num / 32 + 1);
  97 }
  98
  99 static uint32 us_to_x32(uint32 time_us)
 100 {
 101         uint32 clk_num = (SDRAM_CORE_CLK * time_us);
 102         return (clk_num / 32 + 1);
 103 }
 104
 105 /*
 106  *Read/write mode register in ddr memory.
 107  *Refer to uMCTL2 databook Chapter2.18 "Mode Register Reads and Writes"
 108 */
 109 static uint32 mr_rw(uint32 dram_type, uint32 mr_ranks, uint32 rw_flag,
 110                     uint32 mr_addr, uint32 mr_data)
 111 {
 112 #if 0
 113 //changde
 114         uint32 mrctrl0 = 0, mrctrl1 = 0;
 115
 116         /* checking that there is no outstanding MR tansacton.MCTL_MRSTAT.[mr_wr_busy] */
 117         while (UMCTL_REG_GET(UMCTL_MRSTAT) & BIT_0) ;
 118
 119         mrctrl0 = (mr_addr << 12) | ((((mr_ranks == MR_RANKS_0ONLY) ? 0x01 : 0x00) | ((mr_ranks == MR_RANKS_1ONLY) ? 0x02 : 0x00) | ((mr_ranks == MR_RANKS_0AND2) ? 0x05 : 0x00) | ((mr_ranks == MR_RANKS_1AND3) ? 0x0A : 0x00) | ((mr_ranks == MR_RANKS_ALL) ? 0x0F : 0x00)) << 4) | (((rw_flag == MR_READ) ? 1 : 0) << 0);    /* Only used for LPDDR2/LPDDR3 */
 120         /* mr_addr:Don't care for LPDDR2/LPDDR3 */
 121         mrctrl0 &= ~((((dram_type == DRAM_LPDDR2)
 122                        || (dram_type == DRAM_LPDDR3)) ? 0x07 : 0x00) << 12);
 123         UMCTL_REG_SET(UMCTL_MRCTRL0, mrctrl0);
 124
 125         mrctrl1 = (((dram_type == DRAM_LPDDR2)
 126                     || (dram_type ==
 127                         DRAM_LPDDR3)) ? mr_addr : 0x00) << 8) | (mr_data << 0);
 128         UMCTL_REG_SET(UMCTL_MRCTRL1, mrctrl1);
 129
 130         /* tirger the MR transaction in BIT_31 MRCTRL0.[mr_wr] */
 131         reg_bits_set(UMCTL_MRCTRL0, 31, 1, 0x01);
 132         /* checking that there is no outstanding MR tansacton.MCTL_MRSTAT.[mr_wr_busy] */
 133         while (UMCTL_REG_GET(UMCTL_MRSTAT) & BIT_0) ;
 134 #endif
 135 }
 136
 137 void umctl_soft_reset(BOOLEAN is_en) {
 138         uint32 reg_value = 0, i = 0;
 139         /*soft reset for uMCTL2 in user interface. */
 140         if (is_en) {
 141                 // Assert soft reset
 142                 reg_value = UMCTL_REG_GET(0x402b00c8);
 143                 reg_value &= ~(0x03 << 11);
 144                 reg_value |= ((0x1 << 8) | (0x1 << 10));
 145                 UMCTL_REG_SET(0x402b00c8, reg_value);
 146                 reg_value = UMCTL_REG_GET(0x402b0128);
 147                 reg_value |= (0x1 << 16);
 148                 UMCTL_REG_SET(0x402b0128, reg_value);
 149                 for (i = 0; i <= 1000; i++) ;
 150         } else {
 151                 // dessert soft reset
 152                 reg_value = UMCTL_REG_GET(0x402b00c8);
 153                 reg_value &= ~((0x1 << 8) | (0x1 << 10));
 154                 UMCTL_REG_SET(0x402b00c8, reg_value);
 155                 reg_value = UMCTL_REG_GET(0x402b0128);
 156                 reg_value &= ~(0x1 << 16);
 157                 UMCTL_REG_SET(0x402b0128, reg_value);
 158
 159                 for (i = 0; i <= 1000; i++) ;
 160         }
 161 }
 162
 163 void umctl_core_init(DRAM_DESC * dram) {
 164         uint8 dram_type = dram->dram_type;
 165         uint8 BL = dram->bl;
 166         uint8 CL = dram->rl;
 167         uint8 RL = dram->rl;
 168         uint8 WL = dram->wl;
 169         uint8 ranks = dram->cs_num;
 170         uint8 width = dram->io_width;
 171
 172         /* master register config */
 173         reg_bits_set(UMCTL_MSTR, 24, 4, ((ranks == 1) ? 0x01 : 0) |
 174                      ((ranks == 2) ? 0x03 : 0) |
 175                      ((ranks == 3) ? 0x07 : 0) | ((ranks == 4) ? 0x0F : 0));
 176         reg_bits_set(UMCTL_MSTR, 16, 4, ((BL == 2) ? 0x01 : 0) |
 177                      ((BL == 4) ? 0x02 : 0) |
 178                      ((BL == 8) ? 0x04 : 0) | ((BL == 16) ? 0x08 : 0));
 179         /*data_bus_width:2'b00--Full DQ buswidth.2'b01--Half DQ buswidth.
 180          *               2'b10--Quater DQ buswidth.2'b11--Reserved
 181          */
 182         reg_bits_set(UMCTL_MSTR, 12, 2, ((width == 32) ? 0x00 : 0x00) |
 183                      ((width == 16) ? 0x01 : 0x00) |
 184                      ((width == 8) ? 0x02 : 0x00));
 185         /*disable en_2t_timing_mode,use 1T timing as default. */
 186         reg_bits_set(UMCTL_MSTR, 10, 1, 0x00);
 187         /*burst_mode, 0--Sequential burst mode;1--Interleaved burst mode. */
 188         reg_bits_set(UMCTL_MSTR, 8, 1,
 189                      ((BURST_TYPE ==
 190                        DRAM_BT_SEQ) ? 0x00 : 0x00) | ((BURST_TYPE ==
 191                                                        DRAM_BT_INTER) ? 0x01 :
 192                                                       0x00));
 193         /*SDRAM selection for ddr2/ddr3/lpddr/lpddr2/lpddr3 */
 194         reg_bits_set(UMCTL_MSTR, 0, 4,
 195                      ((dram_type == DRAM_DDR2) ? 0x00 : 0x00) | ((dram_type ==
 196                                                                   DRAM_DDR3) ?
 197                                                                  0x01 : 0x00) |
 198                      ((dram_type == DRAM_LPDDR1) ? 0x02 : 0x00) | ((dram_type ==
 199                                                                     DRAM_LPDDR2)
 200                                                                    ? 0x04 :
 201                                                                    0x00) |
 202                      ((dram_type == DRAM_LPDDR3) ? 0x08 : 0x00));
 203 }
 204
 205 /*
 206  *[2:0]operation mode status
 207  *0x00-init
 208  *0x01-normal
 209  *0x02-power-down
 210  *0x03-SelfRefresh
 211  *0x04-DeepPowerdown,only support for mDDDR/LPDDR2/LPDDR3
 212 */
 213 uint32 umctl_wait_status(uint32 state) {
 214         uint32 poll_data = ((state == OPERATION_MODE_INIT) ? 0x00 : 0x00) |
 215             ((state == OPERATION_MODE_NORMAL) ? 0x01 : 0x00) |
 216             ((state == OPERATION_MODE_PD) ? 0x02 : 0x00) |
 217             ((state == OPERATION_MODE_SR) ? 0x03 : 0x00) |
 218             ((state == OPERATION_MODE_DPD) ? 0x04 : 0x00);
 219
 220         while ((UMCTL_REG_GET(UMCTL_STAT) & 0x07) != poll_data) ;
 221 }
 222
 223 /*
 224  *Refer to uMCTL2 databook Chapter5.4.45~5.4.53.
 225  *Set sdram timing parameters,refer to SDRAM spec for details.
 226 */
 227 void umctl_sdram_timing(DRAM_DESC * dram) {
 228         uint8 dram_type = dram->dram_type;
 229         uint8 BL = dram->bl;
 230         uint8 CL = dram->rl;
 231         uint8 RL = dram->rl;
 232         uint8 WL = dram->wl;
 233         uint8 AL = dram->al;
 234
 235         /*Get the timing we used. */
 236         LPDDR_ACTIMING *lpddr1_timing = (LPDDR_ACTIMING *) (dram->ac_timing);
 237         LPDDR2_ACTIMING *lpddr2_timing = (LPDDR2_ACTIMING *) (dram->ac_timing);
 238         DDR2_ACTIMING *ddr2_timing = (DDR2_ACTIMING *) (dram->ac_timing);
 239         DDR3_ACTIMING *ddr3_timing = (DDR3_ACTIMING *) (dram->ac_timing);
 240
 241         uint8 tWR = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tWR) : 0x00) |
 242             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tWR) : 0x00) |
 243             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tWR) : 0x00);
 244         uint8 tCKESR =
 245             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tCKESR) : 0x00);
 246         uint8 tCKSRX =
 247             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tCKSRX) : 0x00);
 248         uint8 tMOD = (dram_type == DRAM_DDR3) ? (ddr3_timing->tMOD) : 0x00;     /*DDR3 only */
 249         uint8 tMRD = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tMRD) : 0x00) | ((dram_type == DRAM_DDR2) ? (ddr2_timing->tMRD) : 0x00) |    /*DDR3/2 only */
 250             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tMRD) : 0x00);
 251         uint8 tRTP =
 252             ((dram_type ==
 253               DRAM_LPDDR2) ? (lpddr2_timing->tRTP) : 0x00) | ((dram_type ==
 254                                                                DRAM_DDR3)
 255                                                               ?
 256                                                               (ddr3_timing->tRTP)
 257                                                               : 0x00);
 258         uint8 tWTR =
 259             ((dram_type ==
 260               DRAM_LPDDR1) ? (lpddr1_timing->tWTR) : 0x00) | ((dram_type ==
 261                                                                DRAM_LPDDR2)
 262                                                               ?
 263                                                               (lpddr2_timing->tWTR)
 264                                                               : 0x00) |
 265             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tWTR) : 0x00);
 266         uint8 tRP =
 267             ((dram_type ==
 268               DRAM_LPDDR1) ? (lpddr1_timing->tRP) : 0x00) | ((dram_type ==
 269                                                               DRAM_LPDDR2)
 270                                                              ?
 271                                                              (lpddr2_timing->tRP)
 272                                                              : 0x00) |
 273             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRP) : 0x00);
 274         uint8 tRCD =
 275             ((dram_type ==
 276               DRAM_LPDDR1) ? (lpddr1_timing->tRCD) : 0x00) | ((dram_type ==
 277                                                                DRAM_LPDDR2)
 278                                                               ?
 279                                                               (lpddr2_timing->tRCD)
 280                                                               : 0x00) |
 281             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRCD) : 0x00);
 282         uint8 tRAS =
 283             ((dram_type ==
 284               DRAM_LPDDR1) ? (lpddr1_timing->tRAS) : 0x00) | ((dram_type ==
 285                                                                DRAM_LPDDR2)
 286                                                               ?
 287                                                               (lpddr2_timing->tRAS)
 288                                                               : 0x00) |
 289             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRAS) : 0x00);
 290         uint8 tRRD =
 291             ((dram_type ==
 292               DRAM_LPDDR1) ? (lpddr1_timing->tRRD) : 0x00) | ((dram_type ==
 293                                                                DRAM_LPDDR2)
 294                                                               ?
 295                                                               (lpddr2_timing->tRRD)
 296                                                               : 0x00) |
 297             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRRD) : 0x00);
 298         uint8 tRC =
 299             ((dram_type ==
 300               DRAM_LPDDR1) ? (lpddr1_timing->tRC) : 0x00) | ((dram_type ==
 301                                                               DRAM_LPDDR2)
 302                                                              ?
 303                                                              (lpddr2_timing->tRC)
 304                                                              : 0x00) |
 305             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRC) : 0x00);
 306         uint8 tCCD =
 307             ((dram_type ==
 308               DRAM_LPDDR2) ? (lpddr2_timing->tCCD) : 0x00) | ((dram_type ==
 309                                                                DRAM_DDR3)
 310                                                               ?
 311                                                               (ddr3_timing->tCCD)
 312                                                               : 0x00);
 313         uint8 tFAW =
 314             ((dram_type ==
 315               DRAM_LPDDR2) ? (lpddr2_timing->tFAW) : 0x00) | ((dram_type ==
 316                                                                DRAM_DDR3)
 317                                                               ?
 318                                                               (ddr3_timing->tFAW)
 319                                                               : 0x00);
 320         uint8 tRFC =
 321             ((dram_type ==
 322               DRAM_LPDDR1) ? (lpddr1_timing->tRFC) : 0x00) | ((dram_type ==
 323                                                                DRAM_LPDDR2)
 324                                                               ?
 325                                                               (lpddr2_timing->tRFC)
 326                                                               : 0x00) |
 327             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRFC) : 0x00);
 328         uint8 tDQSCK = (dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tDQSCK) : 0x00;     /*LPDDR2 only */
 329         uint8 tXS = ((dram_type == DRAM_DDR2) ? (ddr2_timing->tXS) : 200) |     /*for DDR2/DDR3,default200 */
 330             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tXS) : 200);
 331         uint8 tXP = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tXP) : 0x00) |
 332             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tXP) : 0x00) |
 333             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tXP) : 0x00);
 334         uint8 tCKE =
 335             ((dram_type ==
 336               DRAM_LPDDR1) ? (lpddr1_timing->tCKE) : 0x00) | ((dram_type ==
 337                                                                DRAM_LPDDR2)
 338                                                               ?
 339                                                               (lpddr2_timing->tCKE)
 340                                                               : 0x00) |
 341             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tCKE) : 0x00);
 342         /*tDLLK:Dll locking time.Valid value are 2 to 1023 */
 343         uint8 tDLLK = (dram_type == DRAM_DDR3) ? (ddr3_timing->tDLLK) : 0x00;
 344         uint8 tDQSCKmax =
 345             (dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tDQSCKmax) : 0x00;
 346         /*tAOND:ODT turnon/turnoff delays,DDR2 only */
 347         uint8 tAOND = ((dram_type == DRAM_DDR2) ? (ddr2_timing->tAOND) : 0x00);
 348         /*tRTODT:Read to ODT delay,DDR3 only
 349          *0--ODT maybe turned on immediately after read post-amble
 350          *1--ODT maybe not turned on until one clock after read post-amble
 351          */
 352         uint8 tRTODT = 0x00;
 353         /*Get the timing we used. */
 354
 355         reg_bits_set(UMCTL_DRAMTMG0, 24, 6, (WL + (BL >> 1) + tWR));    /*wr2pre */
 356         reg_bits_set(UMCTL_DRAMTMG0, 16, 6, tFAW);      /*t_FAW */
 357         reg_bits_set(UMCTL_DRAMTMG0, 13, 6, tRAS + ns_to_xclock(70000));        /*t_ras_max,Maxinum time of tRAS,clocks */
 358         reg_bits_set(UMCTL_DRAMTMG0, 0, 6, tRAS);       /*t_ras_min,Mininum time of tRAS,clocks */
 359
 360         reg_bits_set(UMCTL_DRAMTMG1, 16, 6, tXP);
 361         /*Minimun from read to precharge of same bank */
 362         reg_bits_set(UMCTL_DRAMTMG1, 8, 5,
 363                      ((dram_type ==
 364                        DRAM_DDR2) ? (AL + (BL >> 1) + MAX(tRTP,
 365                                                           2) -
 366                                      2) : 0x00) | ((dram_type ==
 367                                                     DRAM_DDR3) ? (AL + MAX(tRTP,
 368                                                                            4)) :
 369                                                    0x00) | ((dram_type ==
 370                                                              DRAM_LPDDR1) ? (BL
 371                                                                              >>
 372                                                                              1)
 373                                                             : 0x00) |
 374                      ((dram_type ==
 375                        DRAM_LPDDR2) ? ((BL >> 1) + MAX(tRTP, 2) - 2) : 0x00) |
 376                      /*((dram_type==DRAM_LPDDR2_S2)?((BL>>1)+tRTP-1):0x00) | changde
 377                         ((dram_type==DRAM_LPDDR2_S4)?((BL>>1)+MAX(tRTP,2)-2):0x00) |
 378                       */
 379                      ((dram_type ==
 380                        DRAM_LPDDR3) ? ((BL >> 1) + MAX(tRTP, 4) - 4) : 0x00));
 381         reg_bits_set(UMCTL_DRAMTMG1, 0, 6, tRC);        /*Active-to-Active command period */
 382
 383         reg_bits_set(UMCTL_DRAMTMG2, 24, 6, WL);
 384         reg_bits_set(UMCTL_DRAMTMG2, 16, 5, RL);
 385         /*Minimam time from read command to write command */
 386         reg_bits_set(UMCTL_DRAMTMG2, 8, 5,
 387                      (((dram_type == DRAM_DDR2) || (dram_type == DRAM_DDR3)
 388                        || (dram_type ==
 389                            DRAM_LPDDR1)) ? (RL + (BL >> 1) + 2 -
 390                                             WL) : 0x00) | (((dram_type ==
 391                                                              DRAM_LPDDR2)
 392                                                             || (dram_type ==
 393                                                                 DRAM_LPDDR3))
 394                                                            ? (RL + (BL >> 2) +
 395                                                               tDQSCKmax + 1 -
 396                                                               WL) : 0x00));
 397         reg_bits_set(UMCTL_DRAMTMG2, 0, 6, (WL + (BL >> 1) + tWTR));
 398
 399         /*tMRW, time to wait during load mode register writes. */
 400         reg_bits_set(UMCTL_DRAMTMG3, 26, 6,
 401                      ((dram_type == DRAM_LPDDR2) ? 0x05 : 0x00) | ((dram_type ==
 402                                                                     DRAM_LPDDR3)
 403                                                                    ? 0x0A :
 404                                                                    0x00));
 405         reg_bits_set(UMCTL_DRAMTMG3, 12, 3, tMRD);
 406         reg_bits_set(UMCTL_DRAMTMG3, 0, 10, tMOD);
 407
 408         reg_bits_set(UMCTL_DRAMTMG4, 24, 5, tRCD);
 409         reg_bits_set(UMCTL_DRAMTMG4, 16, 3, tCCD);
 410         reg_bits_set(UMCTL_DRAMTMG4, 8, 4, tRRD);
 411         reg_bits_set(UMCTL_DRAMTMG4, 0, 5, tRP);
 412
 413         /*tCKSRX,the time before SelfRefreshExit that CK is maintained as a valid clock. */
 414         /*Specifies the clock stable time before SRX. */
 415         reg_bits_set(UMCTL_DRAMTMG5, 24, 4,
 416                      ((dram_type == DRAM_LPDDR1) ? 0x01 : 0x00) | ((dram_type ==
 417                                                                     DRAM_LPDDR2)
 418                                                                    ? 0x02 :
 419                                                                    0x00) |
 420                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00) | ((dram_type ==
 421                                                                     DRAM_DDR2) ?
 422                                                                    0x01 : 0x00)
 423                      | ((dram_type == DRAM_DDR3) ? tCKSRX : 0x00));
 424         /*tCKSRE,the time after SelfRefreshDownEntry that CK is maintained as a valid clock. */
 425         /*Specifies the clock disable delay after SRE. */
 426         reg_bits_set(UMCTL_DRAMTMG5, 16, 4,
 427                      ((dram_type == DRAM_LPDDR1) ? 0x00 : 0x00) | ((dram_type ==
 428                                                                     DRAM_LPDDR2)
 429                                                                    ? 0x02 :
 430                                                                    0x00) |
 431                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00) | ((dram_type ==
 432                                                                     DRAM_DDR2) ?
 433                                                                    0x01 : 0x00)
 434                      | ((dram_type == DRAM_DDR3) ? 0x05 : 0x00));
 435         /*tCKESR,Minimum CKE low width for selfrefresh entry to exit timing in clock cycles. */
 436         reg_bits_set(UMCTL_DRAMTMG5, 8, 6,
 437                      ((dram_type == DRAM_LPDDR1) ? tRFC : 0x00) | ((dram_type ==
 438                                                                     DRAM_LPDDR2)
 439                                                                    ? tCKESR :
 440                                                                    0x00) |
 441                      ((dram_type ==
 442                        DRAM_LPDDR3) ? tCKESR : 0x00) | ((dram_type ==
 443                                                          DRAM_DDR2) ? tCKE :
 444                                                         0x00) | ((dram_type ==
 445                                                                   DRAM_DDR3)
 446                                                                  ? (tCKE +
 447                                                                     1) : 0x00));
 448         /*tCKE,Minimum number of cycles of CKE HIGH/LOW during power-down and selfRefresh. */
 449         reg_bits_set(UMCTL_DRAMTMG5, 8, 6, tCKE);
 450
 451         /*tCKDPDE,time after DeepPowerDownEntry that CK is maintained as a valid clock. */
 452         reg_bits_set(UMCTL_DRAMTMG6, 24, 4,
 453                      ((dram_type == DRAM_LPDDR1) ? 0x00 : 0x00) | ((dram_type ==
 454                                                                     DRAM_LPDDR2)
 455                                                                    ? 0x02 :
 456                                                                    0x00) |
 457                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00));
 458         /*tCKDPDX,time before DeepPowerDownExit that CK is maintained as a valid clock before issuing DPDX. */
 459         reg_bits_set(UMCTL_DRAMTMG6, 16, 4,
 460                      ((dram_type == DRAM_LPDDR1) ? 0x01 : 0x00) | ((dram_type ==
 461                                                                     DRAM_LPDDR2)
 462                                                                    ? 0x02 :
 463                                                                    0x00) |
 464                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00));
 465         /*tCKCSX,time before ClockStopExit that CK is maintained as a valid clock before issuing DPDX. */
 466         reg_bits_set(UMCTL_DRAMTMG6, 0, 4,
 467                      ((dram_type == DRAM_LPDDR1) ? 0x01 : 0x00) | ((dram_type ==
 468                                                                     DRAM_LPDDR2)
 469                                                                    ? (tXP +
 470                                                                       0x02) :
 471                                                                    0x00) |
 472                      ((dram_type == DRAM_LPDDR3) ? (tXP + 0x02) : 0x00));
 473
 474         /*tCKPDE,time after PowerDownEntry that CK is maintained as a valid clock before issuing PDE. */
 475         reg_bits_set(UMCTL_DRAMTMG7, 8, 4,
 476                      ((dram_type == DRAM_LPDDR1) ? 0x00 : 0x00) | ((dram_type ==
 477                                                                     DRAM_LPDDR2)
 478                                                                    ? 0x02 :
 479                                                                    0x00) |
 480                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00));
 481         /*tCKPDX,time before PowerDownExit that CK is maintained as a valid clock before issuing PDX. */
 482         reg_bits_set(UMCTL_DRAMTMG7, 0, 4,
 483                      ((dram_type == DRAM_LPDDR1) ? 0x00 : 0x00) | ((dram_type ==
 484                                                                     DRAM_LPDDR2)
 485                                                                    ? 0x02 :
 486                                                                    0x00) |
 487                      ((dram_type == DRAM_LPDDR3) ? 0x02 : 0x00));
 488
 489         /*post_selfref_gap_x32,time after coming out of selfref before doing anything.Default:0x44
 490            //reg_bits_set(MCTL_DRAMTMG8,  0, 4, max(tXSNR,max(tXSRD,tXSDLL))); */
 491         reg_bits_set(UMCTL_DRAMTMG8, 0, 32, 0x00000014);
 492 }
 493
 494 /*
 495  *Refer to uMCTL2 databook for detail.
 496  *Set sdram timing parameters according to EDA simulation.
 497  *including DFI/ZQ/ADDR_MAPPING/PCFGR_x
 498 */
 499 void umctl_other_init(DRAM_DESC * dram) {
 500         uint8 dram_type = dram->dram_type;
 501
 502         reg_bits_set(UMCTL_RFSHTMG, 0, 32, 0x620038);   //yanbin
 503
 504 /*FPGA_TEST xiaohui in Beijing*/
 505         reg_bits_set(UMCTL_ZQCTL0, 0, 32, 0x00900024);
 506         reg_bits_set(UMCTL_ZQCTL1, 0, 32, 0x01400070);
 507         reg_bits_set(UMCTL_ZQCTL2, 0, 32, 0x00000000);
 508
 509         reg_bits_set(UMCTL_DFITMG0, 0, 32,
 510                      ((dram_type ==
 511                        DRAM_LPDDR1) ? 0x02010100 : 0x00) | ((dram_type ==
 512                                                              DRAM_LPDDR2) ?
 513                                                             0x02050103 : 0x00));
 514         reg_bits_set(UMCTL_DFITMG1, 0, 32, 0x00300202);
 515         reg_bits_set(UMCTL_DFILPCFG0, 0, 32, 0x07812120);       //yanbin   0x07813120
 516
 517         reg_bits_set(UMCTL_DFIUPD0, 0, 32, 0x80400003); //yanbin   0x00400003
 518         reg_bits_set(UMCTL_DFIUPD1, 0, 32, 0x001A0021);
 519         reg_bits_set(UMCTL_DFIUPD2, 0, 32, 0x026904C9);
 520         reg_bits_set(UMCTL_DFIUPD3, 0, 32, 0x030E051F);
 521
 522         /*Phy initialization complete enable
 523          *We asserted the MCTL_DFIMISC.[dfi_init_complete] to trigger SDRAM initialization.
 524          */
 525         reg_bits_set(UMCTL_DFIMISC, 0, 32, 0x00000001);
 526
 527         /*address mapping */
 528         if (DRAM_LPDDR2 == dram_type) {
 529                 reg_bits_set(UMCTL_ADDRMAP0, 0, 32, 0x0000001f);        //cs_bit_0 = 0
 530                 reg_bits_set(UMCTL_ADDRMAP1, 0, 32, 0x00070707);        //bank_bit_2 = 11, bank_bit_1 = 10, bank_bit_0 = 9
 531                 reg_bits_set(UMCTL_ADDRMAP2, 0, 32, 0x00000000);        //col_bit_5 = 5, col_bit_4 = 4, col_bit_3 = 3, col_bit_2 = 2
 532                 reg_bits_set(UMCTL_ADDRMAP3, 0, 32, 0x0f000000);        //col_bit_9 = 0, col_bit_8 = 8, col_bit_7 = 7, col_bit_6 = 6
 533                 reg_bits_set(UMCTL_ADDRMAP4, 0, 32, 0x00000f0f);        //col_bit_11 = 0, col_bit_10 = 0
 534                 reg_bits_set(UMCTL_ADDRMAP5, 0, 32, 0x06060606);        //row_bit_11 = 23, row_bit_10:2 = 22:14, row_bit_1 = 13, row_bit_0 = 12
 535                 reg_bits_set(UMCTL_ADDRMAP6, 0, 32, 0x0f0f0f06);        //row_bit_15 = 0, row_bit_14 = 0, row_bit_13 = 0, row_bit_12 = 24
 536         } else {                /*DRAM_LPDDR1 */
 537                 reg_bits_set(UMCTL_ADDRMAP0, 0, 32, 0x00000013);
 538                 reg_bits_set(UMCTL_ADDRMAP1, 0, 32, 0x000f0707);
 539                 reg_bits_set(UMCTL_ADDRMAP2, 0, 32, 0x00000000);
 540                 reg_bits_set(UMCTL_ADDRMAP3, 0, 32, 0x0f000000);
 541                 reg_bits_set(UMCTL_ADDRMAP4, 0, 32, 0x00000F0F);
 542                 reg_bits_set(UMCTL_ADDRMAP5, 0, 32, 0x05050505);
 543                 reg_bits_set(UMCTL_ADDRMAP6, 0, 32, 0x0F0F0505);
 544         }
 545
 546         reg_bits_set(UMCTL_ODTCFG, 0, 32, 0x02010205);
 547         reg_bits_set(UMCTL_ODTMAP, 0, 32, 0x00000312);
 548
 549         reg_bits_set(UMCTL_SCHED, 0, 32, 0x00070C01);
 550         reg_bits_set(UMCTL_PERFHPR0, 0, 32, 0x00000000);
 551         reg_bits_set(UMCTL_PERFHPR1, 0, 32, 0x10000000);
 552         reg_bits_set(UMCTL_PERFLPR0, 0, 32, 0x00000100);
 553         reg_bits_set(UMCTL_PERFLPR1, 0, 32, 0x40000100);
 554         reg_bits_set(UMCTL_PERFWR0, 0, 32, 0x00000000);
 555         reg_bits_set(UMCTL_PERFWR1, 0, 32, 0x10000000);
 556
 557         /*port common configuration register
 558          *[4]:pagematch_limit
 559          *[0]:go2critical_en
 560          */
 561         reg_bits_set(UMCTL_PCCFG, 0, 32, 0x00000011);
 562         /*Port n configuration Read/Write register setting */
 563         reg_bits_set(UMCTL_PCFGR_0, 0, 32, 0x0001F000);
 564         reg_bits_set(UMCTL_PCFGW_0, 0, 32, 0x00004005);
 565         reg_bits_set(UMCTL_PORT_EN_0, 0, 32, 0x00000001);
 566         reg_bits_set(UMCTL_PCFGR_1, 0, 32, 0x0001F000);
 567         reg_bits_set(UMCTL_PCFGW_1, 0, 32, 0x00004005);
 568         reg_bits_set(UMCTL_PORT_EN_1, 0, 32, 0x00000001);
 569         reg_bits_set(UMCTL_PCFGR_2, 0, 32, 0x0001F000);
 570         reg_bits_set(UMCTL_PCFGW_2, 0, 32, 0x00004005);
 571         reg_bits_set(UMCTL_PORT_EN_2, 0, 32, 0x00000001);
 572         reg_bits_set(UMCTL_PCFGR_3, 0, 32, 0x0001F000);
 573         reg_bits_set(UMCTL_PCFGW_3, 0, 32, 0x00004005);
 574         reg_bits_set(UMCTL_PORT_EN_3, 0, 32, 0x00000001);
 575         reg_bits_set(UMCTL_PCFGR_4, 0, 32, 0x0001F000);
 576         reg_bits_set(UMCTL_PCFGW_4, 0, 32, 0x00004005);
 577         reg_bits_set(UMCTL_PORT_EN_4, 0, 32, 0x00000001);
 578         reg_bits_set(UMCTL_PCFGR_5, 0, 32, 0x0001F000);
 579         reg_bits_set(UMCTL_PCFGW_5, 0, 32, 0x00004005);
 580         reg_bits_set(UMCTL_PORT_EN_5, 0, 32, 0x00000001);
 581         reg_bits_set(UMCTL_PCFGR_6, 0, 32, 0x0001F000);
 582         reg_bits_set(UMCTL_PCFGW_6, 0, 32, 0x00004005);
 583         reg_bits_set(UMCTL_PORT_EN_6, 0, 32, 0x00000001);
 584         reg_bits_set(UMCTL_PCFGR_7, 0, 32, 0x0001F000);
 585         reg_bits_set(UMCTL_PCFGW_7, 0, 32, 0x00004005);
 586         reg_bits_set(UMCTL_PORT_EN_7, 0, 32, 0x00000001);
 587         reg_bits_set(UMCTL_PCFGR_8, 0, 32, 0x0001F000);
 588         reg_bits_set(UMCTL_PCFGW_8, 0, 32, 0x00004005);
 589         reg_bits_set(UMCTL_PORT_EN_8, 0, 32, 0x00000001);
 590         reg_bits_set(UMCTL_PCFGR_9, 0, 32, 0x0001F000);
 591         reg_bits_set(UMCTL_PCFGW_9, 0, 32, 0x00004005);
 592         reg_bits_set(UMCTL_PORT_EN_9, 0, 32, 0x00000001);
 593 }
 594
 595 /*
 596  *Power-up timing initialization and Mode Register Setting for sdram.
 597 */
 598 void umctl_poweron_init(DRAM_DESC * dram) {
 599         uint8 dram_type = dram->dram_type;
 600         uint8 BL = dram->bl;
 601         uint8 CL = dram->rl;
 602         uint8 RL = dram->rl;
 603         uint8 WL = dram->wl;
 604         uint8 AL = dram->al;
 605         uint8 mr = 0, emr = 0, mr2 = 0, mr3 = 0;
 606
 607         /*Get the timing we used. */
 608         LPDDR_ACTIMING *lpddr1_timing = (LPDDR_ACTIMING *) (dram->ac_timing);
 609         LPDDR2_ACTIMING *lpddr2_timing = (LPDDR2_ACTIMING *) (dram->ac_timing);
 610         DDR2_ACTIMING *ddr2_timing = (DDR2_ACTIMING *) (dram->ac_timing);
 611         DDR3_ACTIMING *ddr3_timing = (DDR3_ACTIMING *) (dram->ac_timing);
 612
 613         /* tINIT0:(-~20)ms  Maximum voltage ramp time */
 614         uint32 tINIT0 = 15;
 615         /* tINIT1:(100~-)ns Minimum CKE LOW time after completion of voltage ramp */
 616         uint32 tINIT1 = 200;
 617         /* tINIT2:(5~-)tCK  Minimum stable clock before first CKE HIGH */
 618         uint32 tINIT2 = 10;
 619         /* tINIT3:(200~-)us Minimum idle time after first CKE assertion */
 620         uint32 tINIT3 = 300;
 621         /* tINIT4:(001~-)us Minimum idle time after RESET command */
 622         uint32 tINIT4 = 10;
 623         /* tINIT5:(-~10)us  Maximum duration of device auto initialization */
 624         uint32 tINIT5 = 8;
 625         /* tZQINIT:(1~-)us  ZQ initial calibration (S4 devices only) */
 626         uint32 tZQINIT = 5;
 627         /* tCKb:(18~100)ns  Clock cycle time during boot */
 628         uint32 tCKb = 50;
 629
 630         /*post_cle_x1024,cycles to wait after driving CKE high to start the SDRAM init sequence. */
 631         reg_bits_set(UMCTL_INIT0, 16, 10,
 632                      ((dram_type ==
 633                        DRAM_DDR2) ? ns_to_x1024(400) : 0x00) | ((dram_type ==
 634                                                                  DRAM_LPDDR2) ?
 635                                                                 us_to_x1024(200)
 636                                                                 : 0x00) |
 637                      ((dram_type == DRAM_LPDDR3) ? us_to_x1024(200) : 0x00));
 638         /*pre_cle_x1024,cycles to wait after reset before driving CKE high to start the SDRAM init sequence. */
 639         reg_bits_set(UMCTL_INIT0, 0, 10, ((dram_type == DRAM_DDR2) ? us_to_x1024(200) : 0x00) | /*>=200us */
 640                      /*tINIT0 of 20ms(max) + tINIT1 of 100ns(min) */
 641                      ((dram_type ==
 642                        DRAM_LPDDR2) ? (ms_to_x1024(tINIT0) +
 643                                        ns_to_x1024(tINIT1)) : 0x00) |
 644                      ((dram_type ==
 645                        DRAM_LPDDR3) ? (ms_to_x1024(tINIT0) +
 646                                        ns_to_x1024(tINIT1)) : 0x00));
 647
 648         /*dram_rstn_x1024,cycles to assert SDRAM reset signal during init sequence. */
 649         reg_bits_set(UMCTL_INIT1, 16, 8, ((dram_type == DRAM_DDR3) ? 0x02 : 0x00));     /*>=1tCK */
 650         /*final_wait_x32,cycles to wait after completing the SDRAM init sequence. */
 651         reg_bits_set(UMCTL_INIT1, 8, 7, 0x01);  /*>=0tCK */
 652         /*pre_ocd_x32,cycles to wait before driving the OCD complete command to SDRAM. */
 653         reg_bits_set(UMCTL_INIT1, 0, 5, 0x01);  /*>=0tCK */
 654
 655         /*idle_after_reset_x32,idle time after the reset command,tINT4. */
 656         reg_bits_set(UMCTL_INIT2, 8, 8,
 657                      ((dram_type == DRAM_LPDDR2) ? us_to_x32(tINIT4) : 0x00));
 658         /*min_stable_clock_x1,time to wait after the first CKE high,tINT2. */
 659         reg_bits_set(UMCTL_INIT2, 0, 4,
 660                      ((dram_type ==
 661                        DRAM_LPDDR2) ? tINIT2 : 0x00) | ((dram_type ==
 662                                                          DRAM_LPDDR3) ? tINIT2 :
 663                                                         0x00));
 664
 665         /*Note:
 666          *    Set Mode register 0~3 for SDRAM memory.
 667          *    Refer to JESD spec for detail.
 668          */
 669         switch (dram_type) {
 670         case DRAM_LPDDR1:
 671                 {
 672                         /*mr store the value to write to MR register */
 673                         mr = (BL << 0) |        /*burst_length:BL2/4/8/16 */
 674                             (0x00 << 3) |       /*0:Sequentia;1:interleavel */
 675                             (CL << 4);  /*cas_latency:2/3/4 optional */
 676                         /*emr store the value to write to EMR register */
 677                         emr = (0x00 << 0) |     /*PASR:0:AllBanks;1:HalfArray;2:QuarterArray,etc */
 678                             (0x00 << 3) |       /*TCSR:0:70'C;1:45'C;2:15'C;3:85'C; */
 679                             ((((IO_DS == DS_FULL) ? 0x00 : 0x00) |
 680                               ((IO_DS == DS_HALF) ? 0x01 : 0x00) |
 681                               ((IO_DS == DS_QUARTER) ? 0x02 : 0x00) |
 682                               ((IO_DS == DS_OCTANT) ? 0x03 : 0x00) |
 683                               ((IO_DS == DS_THREE_QUATERS) ? 0x04 : 0x00)
 684                              ) << 5);   /*DS:0:FullDriverStrength;1:HalfDS;2:QuarterDS;3:OctantDS;4:Three-Quater */
 685
 686                         /*mr2 unused for MDDR */
 687                         /*mr3 unused for MDDR/LPDDR2/LPDDR3 */
 688                         break;
 689                 }
 690         case DRAM_LPDDR2:
 691                 {
 692                         uint8 tWR = lpddr2_timing->tWR;
 693                         /*mr store the value to write to MR1 register */
 694                         /*Set sequential burst-type with wrap */
 695                         mr = ((BL == 4) ? 0x02 : 0x00) |        /*burst_length:2:BL4(default;3:BL8;4:BL16) */
 696                             ((BL == 8) ? 0x03 : 0x00) | ((BL == 16) ? 0x04 : 0x00) | (( /*0:Sequential(default);1:interleavel(allow for SDRAM only) */
 697                                                                                               ((BURST_TYPE == DRAM_BT_SEQ) ? 0x00 : 0x00) | ((BURST_TYPE == DRAM_BT_INTER) ? 0x01 : 0x00)
 698                                                                                       ) << 3) | (0x00 << 4) |   /*0:Wrap(default);1:No wrap(allow for SDRAM BL4 only) */
 699                             ((  /*WriteRecovery,Default(0x01) */
 700                                      ((tWR == 3) ? 0x01 : 0x00) |
 701                                      ((tWR == 4) ? 0x02 : 0x00) |
 702                                      ((tWR == 5) ? 0x03 : 0x00) |
 703                                      ((tWR == 6) ? 0x04 : 0x00) |
 704                                      ((tWR == 7) ? 0x05 : 0x00) |
 705                                      ((tWR == 8) ? 0x06 : 0x00)
 706                              ) << 5);
 707                         /*emr store the value to write to MR2 register,Default:0x01 */
 708                         emr = (((RL == 3) && (WL == 1)) ? 0x01 : 0x00) |
 709                             (((RL == 4) && (WL == 2)) ? 0x02 : 0x00) |
 710                             (((RL == 5) && (WL == 2)) ? 0x03 : 0x00) |
 711                             (((RL == 6) && (WL == 3)) ? 0x04 : 0x00) |
 712                             (((RL == 7) && (WL == 4)) ? 0x05 : 0x00) |
 713                             (((RL == 8) && (WL == 4)) ? 0x06 : 0x00);
 714                         /*mr2 store the value to write to MR3 register */
 715                         /*DS,driver strength configuration.Default:40ohm */
 716                         mr2 = ((IO_DS == DS_34R3) ? 0x01 : 0x00) |
 717                             ((IO_DS == DS_40R) ? 0x02 : 0x00) |
 718                             ((IO_DS == DS_48R) ? 0x03 : 0x00) |
 719                             ((IO_DS == DS_60R) ? 0x04 : 0x00) |
 720                             ((IO_DS == DS_68R6) ? 0x05 : 0x00) |
 721                             ((IO_DS == DS_80R) ? 0x06 : 0x00) |
 722                             ((IO_DS == DS_120R) ? 0x07 : 0x00);
 723                         /*mr3 unused for MDDR/LPDDR2/LPDDR3 */
 724                         break;
 725                 }
 726         case DRAM_DDR2:
 727                 {
 728                         /*mr2 store the value to write to EMR2 register */
 729                         /*mr3 store the value to write to EMR3 register */
 730                         break;
 731                 }
 732         case DRAM_DDR3:
 733                 {
 734                         DDR3_ACTIMING *ddr3_timing =
 735                             (DDR3_ACTIMING *) (dram->ac_timing);
 736                         uint8 tWR = ddr3_timing->tWR;
 737                         uint8 CWL = (WL - AL) ? (WL - AL) : 0x00;
 738                         /*mr store the value to write to MR1 register */
 739                         /*Set sequential burst-type with wrap */
 740                         mr = ((BL == 8) ? 0x00 : 0x00) |        /*Fixed on 8 */
 741                             ((BL == 4) ? 0x01 : 0x00) | /*4or8 on the fly */
 742                             ((BL == 4) ? 0x02 : 0x00) | /*Fixed on 4 */
 743                             ((  /*0:Sequential(default);1:interleavel(allow for SDRAM only) */
 744                                      ((BURST_TYPE ==
 745                                        DRAM_BT_SEQ) ? 0x00 : 0x00) |
 746                                      ((BURST_TYPE ==
 747                                        DRAM_BT_INTER) ? 0x01 : 0x00)
 748                              ) << 3) | ((((CL == 5) ? 0x01 : 0x00) |    /*Bit[6:4],CAS Latency */
 749                                          ((CL == 6) ? 0x02 : 0x00) | ((CL == 7) ? 0x03 : 0x00) | ((CL == 8) ? 0x04 : 0x00) | ((CL == 9) ? 0x05 : 0x00) | ((CL == 10) ? 0x06 : 0x00) | ((CL == 11) ? 0x07 : 0x00)) << 4) | ((((tWR <= 5) ? 0x01 : 0x00) |        /*Bit[11:9],Write recovery for autoprecharge */
 750                                                                                                                                                                                                                             ((tWR == 6) ? 0x02 : 0x00) | ((tWR == 7) ? 0x03 : 0x00) | ((tWR == 8) ? 0x04 : 0x00) | ((tWR == 10) ? 0x05 : 0x00) | ((tWR == 12) ? 0x06 : 0x00) | ((tWR == 14) ? 0x07 : 0x00) | ((tWR == 16) ? 0x00 : 0x00)) << 9);
 751
 752                         /*emr store the value to write to MR1 register */
 753                         /*A0:0-DLL Enable;1-DLL Disable */
 754                         reg_bits_set((uint32) & emr, 0, 1, 0);
 755                         /*Output Driver Impedance Control
 756                            [A5,A1]:00-RZQ/6;01-RZQ/7;10/11-RZQ/TBD;Note: RZQ=240ohm */
 757                         reg_bits_set((uint32) & emr, 1, 1, 0);
 758                         reg_bits_set((uint32) & emr, 5, 1, 0);
 759                         /*[A4:A3]:Additive Latency. */
 760                         reg_bits_set((uint32) & emr, 3, 2,
 761                                      ((AL == 0) ? 0x00 : 0x00) | ((AL ==
 762                                                                    CL -
 763                                                                    1) ? 0x01 :
 764                                                                   0x00) | ((AL
 765                                                                             ==
 766                                                                             CL -
 767                                                                             2) ?
 768                                                                            0x02
 769                                                                            :
 770                                                                            0x00)
 771                             );
 772                         /*[A7]:1-Write leveling enable;0-Disabled */
 773                         reg_bits_set((uint32) & emr, 7, 1, 1);
 774
 775                         /*mr2 store the value to write to MR2 register */
 776                         /*Partial Array Self-Refresh (Optional),[A2:A0]
 777                          */
 778                         /*CAS write Latency (CWL),WL=CWL+AL
 779                            [A5:A3]:5~12 tCK
 780                          */
 781                         reg_bits_set((uint32) & mr2, 3, 3,
 782                                      ((CWL == 5) ? 0x00 : 0x00) | ((CWL ==
 783                                                                     6) ? 0x01 :
 784                                                                    0x00) | ((CWL
 785                                                                              ==
 786                                                                              7)
 787                                                                             ?
 788                                                                             0x02
 789                                                                             :
 790                                                                             0x00)
 791                                      | ((CWL == 8) ? 0x03 : 0x00) | ((CWL == 9)
 792                                                                      ? 0x04 :
 793                                                                      0x00) |
 794                                      ((CWL == 10) ? 0x05 : 0x00) | ((CWL ==
 795                                                                      11) ? 0x06
 796                                                                     : 0x00) |
 797                                      ((CWL == 12) ? 0x07 : 0x00)
 798                             );
 799
 800                         /*mr3 store the value to write to MR3 register */
 801                         /*[A1:A0],MPR location */
 802                         /*[A2],MPR */
 803                         break;
 804                 }
 805         case DRAM_LPDDR3:
 806                 {
 807                         /*mr store the value to write to MR1 register */
 808                         /*mr2 store the value to write to MR3 register */
 809                         /*mr3 unused for MDDR/LPDDR2/LPDDR3 */
 810                         break;
 811                 }
 812         }
 813         reg_bits_set(UMCTL_INIT3, 16, 16, mr);
 814         reg_bits_set(UMCTL_INIT3, 0, 16, emr);
 815         reg_bits_set(UMCTL_INIT4, 16, 16, mr2);
 816         reg_bits_set(UMCTL_INIT4, 0, 16, mr3);
 817
 818         /*dev_zqinit_x32,ZQ initial calibration,tZQINIT. */
 819         reg_bits_set(UMCTL_INIT5, 16, 8,
 820                      ((dram_type ==
 821                        DRAM_DDR3) ? us_to_x32(tZQINIT) : 0x00) | ((dram_type ==
 822                                                                    DRAM_LPDDR2)
 823                                                                   ?
 824                                                                   us_to_x32
 825                                                                   (tZQINIT) :
 826                                                                   0x00) |
 827                      ((dram_type == DRAM_LPDDR3) ? us_to_x32(tZQINIT) : 0x00));
 828         /*max_auto_init_x1024,max duration of the auto initialization,tINIT5. */
 829         reg_bits_set(UMCTL_INIT5, 0, 10,
 830                      ((dram_type ==
 831                        DRAM_LPDDR2) ? us_to_x1024(tINIT5) : 0x00) | ((dram_type
 832                                                                       ==
 833                                                                       DRAM_LPDDR3)
 834                                                                      ?
 835                                                                      us_to_x1024
 836                                                                      (tINIT5) :
 837                                                                      0x00));
 838
 839         /*Only present for multi-rank configurations.
 840          *[11:8]:rank_wr_gap,clks of gap in data responses when performing consecutive writes to different ranks.
 841          *[07:4]:rank_rd_gap,clks of gap in data responses when performing consecutive reads to different ranks.
 842          *[03:0]:max_rank_rd,This param represents the max number of 64B reads(or 32B in some short read cases)
 843          *       that can bescheduled consecutively to the same rank.
 844          */
 845         reg_bits_set(UMCTL_RANKCTL, 0, 32, (0x06 << 8) |
 846                      (0x06 << 4) | (0x03 << 0));
 847 }
 848
 849 /*
 850  *Refer to uMCTL2 databook Chapter2.15.1 "DDR2 initialization sequence"
 851  *Also you can use PUBL build-in-test init sequence.
 852 */
 853 void umctl_ddr2_init(DRAM_DESC * dram, void *init_timing) {
 854
 855 }
 856 /*
 857  *Refer to uMCTL2 databook Chapter2.15.2 "DDR3 initialization sequence"
 858  *Also you can use PUBL build-in-test init sequence.
 859 */ void umctl_ddr3_init(DRAM_DESC * dram, void *init_timing) {
 860
 861 }
 862 /*
 863  *Refer to uMCTL2 databook Chapter2.15.3 "Mobile ddr initialization sequence"
 864  *Also you can use PUBL build-in-test init sequence.
 865 */ void umctl_mddr_init(DRAM_DESC * dram, void *init_timing) {
 866 #if 0
 867 //changde
 868         uint8 i = 0;
 869         uint8 dram_type = dram->dram_type;
 870         uint8 mr_ranks = dram->cs_num;
 871         /*T=200us,Power-up: VDD and CK stable */
 872         uint32 T = 200;
 873
 874         uint32 INIT0 = 0;
 875          INIT0 = ((dram_type == DRAM_LPDDR1) ? us_to_x1024(T) : 0x00);
 876          UMCTL_REG_SET(UMCTL_INIT0, INIT0);
 877          mr_rw(dram_type, mr_ranks, MR_WRITE, MR_ADDR_NOP, 0x00);
 878
 879         /*Issue precharege all command. */
 880          mr_rw(dram_type, mr_ranks, MR_WRITE, MR_CMD_PRECHARGE, 0x00);
 881
 882         /*Issue refresh command 8 times. */
 883         for (i = 0; i < 8; i++) {
 884                 mr_rw(dram_type, mr_ranks, MR_WRITE, MR_CMD_REFRESH, 0x00);
 885         }
 886         /*Load mode register(MR). */
 887             mr_rw(dram_type, mr_ranks, MR_WRITE, MR_CMD_PRECHARGE, 0x00);
 888
 889         /*Load extEnded mode register(EMR). */
 890         mr_rw(dram_type, mr_ranks, MR_WRITE, MR_CMD_PRECHARGE, 0x00);
 891
 892         /*Issue active command. */
 893         mr_rw(dram_type, mr_ranks, MR_WRITE, MR_CMD_PRECHARGE, 0x00);
 894         mr_rw(dram_type, mr_ranks, MR_WRITE, MR_ADDR_NOP, 0x00);
 895
 896         /*Now,begin normal operation */
 897 #endif
 898 }
 899
 900 /*
 901  *Refer to uMCTL2 databook Chapter2.15.4 "LPDDR2/LPDDR3 initialization sequence"
 902  *Also you can use PUBL build-in-test init sequence.
 903 */
 904 void umctl_ldppr2or3_init(DRAM_DESC * dram, void *init_timing) {
 905 #if 0
 906 //changde
 907         /*A reset command is issued to MRW63 register. */
 908         mr_rw(dram_type, mr_ranks, MR_WRITE, 0x3F, 0x00);
 909         mr_rw(dram_type, mr_ranks, MR_WRITE, MR_ADDR_NOP, 0x00);
 910         /*A ZQ initialization calibration command is issued to MRW10 register. */
 911         mr_rw(dram_type, mr_ranks, MR_WRITE, 0x0A, 0xFF);
 912         mr_rw(dram_type, mr_ranks, MR_WRITE, MR_ADDR_NOP, 0x00);
 913         /*Setting MR2 register to INIT3.emr followed by a NOP */
 914
 915         /*Setting MR1 register to INIT3.emr followed by a NOP */
 916
 917         /*Setting MR3 register to INIT3.emr followed by a NOP */
 918
 919         /*Schedule multiple all bank refresh */
 920
 921         /*Now,begin normal operation */
 922 #endif
 923 }
 924 /*
 925  *SDram power-on timing and common timing using PHY publ.
 926  *Configure PUBL_DCR,PUBL_PTR0/1/2 and PUBL_CFG_DTPR0/1/2
 927  *Attention:timing parameters in clock cycles.
 928 */ void phy_sdram_timing(DRAM_DESC * dram) {
 929         uint32 dcr = 0;
 930         uint32 dtpr0 = 0, dtpr1 = 0, dtpr2 = 0;
 931         uint8 dram_type = dram->dram_type;
 932         uint8 banks = dram->bank_num;
 933         uint8 BL = dram->bl;
 934         uint8 CL = dram->rl;
 935         uint8 RL = dram->rl;
 936         uint8 WL = dram->wl;
 937
 938         /*Get the timing we used. */
 939         LPDDR_ACTIMING *lpddr1_timing = (LPDDR_ACTIMING *) (dram->ac_timing);
 940         LPDDR2_ACTIMING *lpddr2_timing = (LPDDR2_ACTIMING *) (dram->ac_timing);
 941         DDR2_ACTIMING *ddr2_timing = (DDR2_ACTIMING *) (dram->ac_timing);
 942         DDR3_ACTIMING *ddr3_timing = (DDR3_ACTIMING *) (dram->ac_timing);
 943
 944         uint8 tWR = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tWR) : 0x00) |
 945             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tWR) : 0x00) |
 946             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tWR) : 0x00);
 947         uint8 tCKESR =
 948             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tCKESR) : 0x00);
 949         uint8 tCKSRX =
 950             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tCKSRX) : 0x00);
 951         uint8 tMOD = (dram_type == DRAM_DDR3) ? (ddr3_timing->tMOD) : 0x00;     /*DDR3 only */
 952         uint8 tMRD = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tMRD) : 0x00) | ((dram_type == DRAM_DDR2) ? (ddr2_timing->tMRD) : 0x00) |    /*DDR3/2 only */
 953             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tMRD) : 0x00);
 954         uint8 tRTP =
 955             ((dram_type ==
 956               DRAM_LPDDR2) ? (lpddr2_timing->tRTP) : 0x00) | ((dram_type ==
 957                                                                DRAM_DDR3)
 958                                                               ?
 959                                                               (ddr3_timing->tRTP)
 960                                                               : 0x00);
 961         uint8 tWTR =
 962             ((dram_type ==
 963               DRAM_LPDDR1) ? (lpddr1_timing->tWTR) : 0x00) | ((dram_type ==
 964                                                                DRAM_LPDDR2)
 965                                                               ?
 966                                                               (lpddr2_timing->tWTR)
 967                                                               : 0x00) |
 968             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tWTR) : 0x00);
 969         uint8 tRP =
 970             ((dram_type ==
 971               DRAM_LPDDR1) ? (lpddr1_timing->tRP) : 0x00) | ((dram_type ==
 972                                                               DRAM_LPDDR2)
 973                                                              ?
 974                                                              (lpddr2_timing->tRP)
 975                                                              : 0x00) |
 976             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRP) : 0x00);
 977         uint8 tRCD =
 978             ((dram_type ==
 979               DRAM_LPDDR1) ? (lpddr1_timing->tRCD) : 0x00) | ((dram_type ==
 980                                                                DRAM_LPDDR2)
 981                                                               ?
 982                                                               (lpddr2_timing->tRCD)
 983                                                               : 0x00) |
 984             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRCD) : 0x00);
 985         uint8 tRAS =
 986             ((dram_type ==
 987               DRAM_LPDDR1) ? (lpddr1_timing->tRAS) : 0x00) | ((dram_type ==
 988                                                                DRAM_LPDDR2)
 989                                                               ?
 990                                                               (lpddr2_timing->tRAS)
 991                                                               : 0x00) |
 992             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRAS) : 0x00);
 993         uint8 tRRD =
 994             ((dram_type ==
 995               DRAM_LPDDR1) ? (lpddr1_timing->tRRD) : 0x00) | ((dram_type ==
 996                                                                DRAM_LPDDR2)
 997                                                               ?
 998                                                               (lpddr2_timing->tRRD)
 999                                                               : 0x00) |
1000             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRRD) : 0x00);
1001         uint8 tRC =
1002             ((dram_type ==
1003               DRAM_LPDDR1) ? (lpddr1_timing->tRC) : 0x00) | ((dram_type ==
1004                                                               DRAM_LPDDR2)
1005                                                              ?
1006                                                              (lpddr2_timing->tRC)
1007                                                              : 0x00) |
1008             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRC) : 0x00);
1009         uint8 tCCD =
1010             ((dram_type ==
1011               DRAM_LPDDR2) ? (lpddr2_timing->tCCD) : 0x00) | ((dram_type ==
1012                                                                DRAM_DDR3)
1013                                                               ?
1014                                                               (ddr3_timing->tCCD)
1015                                                               : 0x00);
1016         uint8 tFAW =
1017             ((dram_type ==
1018               DRAM_LPDDR2) ? (lpddr2_timing->tFAW) : 0x00) | ((dram_type ==
1019                                                                DRAM_DDR3)
1020                                                               ?
1021                                                               (ddr3_timing->tFAW)
1022                                                               : 0x00);
1023         uint8 tRFC =
1024             ((dram_type ==
1025               DRAM_LPDDR1) ? (lpddr1_timing->tRFC) : 0x00) | ((dram_type ==
1026                                                                DRAM_LPDDR2)
1027                                                               ?
1028                                                               (lpddr2_timing->tRFC)
1029                                                               : 0x00) |
1030             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tRFC) : 0x00);
1031         uint8 tDQSCK = (dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tDQSCK) : 0x00;     /*LPDDR2 only */
1032         uint8 tXS = ((dram_type == DRAM_DDR2) ? (ddr2_timing->tXS) : 200) |     /*for DDR2/DDR3,default200 */
1033             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tXS) : 200);
1034         uint8 tXP = ((dram_type == DRAM_LPDDR1) ? (lpddr1_timing->tXP) : 0x00) |
1035             ((dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tXP) : 0x00) |
1036             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tXP) : 0x00);
1037         uint8 tCKE =
1038             ((dram_type ==
1039               DRAM_LPDDR1) ? (lpddr1_timing->tCKE) : 0x00) | ((dram_type ==
1040                                                                DRAM_LPDDR2)
1041                                                               ?
1042                                                               (lpddr2_timing->tCKE)
1043                                                               : 0x00) |
1044             ((dram_type == DRAM_DDR3) ? (ddr3_timing->tCKE) : 0x00);
1045         /*tDLLK:Dll locking time.Valid value are 2 to 1023 */
1046         uint8 tDLLK = (dram_type == DRAM_DDR3) ? (ddr3_timing->tDLLK) : 0x00;
1047         uint8 tDQSCKmax =
1048             (dram_type == DRAM_LPDDR2) ? (lpddr2_timing->tDQSCKmax) : 0x00;
1049         /*tAOND:ODT turnon/turnoff delays,DDR2 only */
1050         uint8 tAOND = ((dram_type == DRAM_DDR2) ? (ddr2_timing->tAOND) : 0x00);
1051         /*tRTODT:Read to ODT delay,DDR3 only
1052          *0--ODT maybe turned on immediately after read post-amble
1053          *1--ODT maybe not turned on until one clock after read post-amble
1054          */
1055         uint8 tRTODT = 0x00;
1056         /*Get the timing we used. */
1057
1058         {                       /*dram configuration register (DCR) */
1059                 /*[2:0]:SDram ddr mode. */
1060                 reg_bits_set(PUBL_DCR, 0, 3,
1061                              ((dram_type ==
1062                                DRAM_LPDDR1) ? 0x00 : 0x00) | ((dram_type ==
1063                                                                DRAM_DDR) ? 0x01
1064                                                               : 0x00) |
1065                              ((dram_type ==
1066                                DRAM_DDR2) ? 0x02 : 0x00) | ((dram_type ==
1067                                                              DRAM_DDR3) ? 0x03 :
1068                                                             0x00) | ((dram_type
1069                                                                       ==
1070                                                                       DRAM_LPDDR2)
1071                                                                      ? 0x04 :
1072                                                                      0x00));
1073                 /*DDR 8-bank,indicates if set that sdram used has 8 banks.
1074                  *tRPA=tRP+1 and tFAW are used for 8banks DRAMs,other tRPA=tRP and no tFAW
1075                  *is used.Note that a setting of 1for DRAMs that have fewer than 8banks still
1076                  *results in correct functionality but less tigther daram parameters.
1077                  */
1078                 reg_bits_set(PUBL_DCR, 3, 1, (banks == 8) ? 0x01 : 0x00);
1079                 /*Select the ddr type for the specified lpddr mode
1080                    reg_bits_set(PUBL_CFG_DCR, 8, 2, ((dram_type==DRAM_LPDDR2_S4)?0x00:0x00)|
1081                    ((dram_type==DRAM_LPDDR2_S2)?0x01:0x00)); */
1082         }
1083
1084         //PTR0, to set tDLLSRST, tDLLLOCK, tITMSRST
1085         {
1086                 //DLL Soft Reset Time: Number of controller clock cycles that the DLL soft reset pin
1087                 //must remain asserted when the soft reset is triggered through the PHY Initialization
1088                 //Register (PIR). This must correspond to a value that is equal to or more than 50ns
1089                 //or 8 controller clock cycles, whichever is bigger.
1090                 //Default value is corresponds to 50ns at 533Mhz
1091                 uint32 tDLLSRST = ns_to_xclock(50);     //ns-->clocks
1092                 //DLL Lock Time: Number of clock cycles for the DLL to stabilize and lock, i.e. number
1093                 //of clock cycles from when the DLL reset pin is de-asserted to when the DLL has
1094                 //locked and is ready for use. Refer to the PHY databook for the DLL lock time.
1095                 //Default value corresponds to 5.12us at 533MHz.
1096                 uint32 tDLLLOCK = ns_to_xclock(5120);   //ns-->clocks
1097                 //ITM Soft Reset Time: Number of controller clock cycles that the ITM soft reset pin
1098                 //must remain asserted when the soft reset is applied to the ITMs. This must
1099                 //correspond to a value that is equal to or more than 8 controller clock cycles.
1100                 //Default value corresponds to 8 controller clock cycles
1101                 uint32 tITMSRST = 8;    //clocks
1102
1103                 REG32(PUBL_PTR0) =
1104                     (tITMSRST << 18) | (tDLLLOCK << 6) | (tDLLSRST);
1105         }
1106
1107         //PTR1, to set tINT0,tINT1
1108         {
1109                 uint32 tINT0 = ((dram_type == DRAM_DDR3) ? us_to_xclock(500) : 0x00) |  /*Unit:us->clk */
1110                     ((dram_type == DRAM_DDR2) ? us_to_xclock(200) : 0x00) |
1111                     ((dram_type == DRAM_LPDDR1) ? us_to_xclock(200) : 0x00) |
1112                     ((dram_type == DRAM_LPDDR2) ? us_to_xclock(200) : 0x00);
1113                 uint32 tINT1 = ((dram_type == DRAM_DDR3) ? 0x05 : 0x00) |       /*Unit:clk */
1114                     ((dram_type == DRAM_DDR2) ? ns_to_xclock(400) : 0x00) | ((dram_type == DRAM_DDR) ? 0x01 : 0x00) |   /*400ns or 1tCK */
1115                     ((dram_type == DRAM_LPDDR2) ? ns_to_xclock(100) : 0x00);
1116
1117                 REG32(PUBL_PTR1) = (tINT1 << 19) | tINT0;
1118         }
1119
1120         //PTR2, to set tINT2,tINT3
1121         {
1122                 /*tINT2,default 200us, time for reset command to end of auto initialization */
1123                 uint32 tINT2 = ((dram_type == DRAM_DDR3) ? ns_to_xclock(200000) : 0x00) |       /*Unit:ns->clk */
1124                     ((dram_type == DRAM_LPDDR2) ? ns_to_xclock(11000) : 0x00);
1125                 //tINT3,default 1us, time for ZQ initialization command to first command */
1126                 uint32 tINT3 =
1127                     (dram_type == DRAM_LPDDR2) ? ns_to_xclock(1000) : 0x00;
1128
1129                 REG32(PUBL_PTR2) = (tINT3 << 17) | tINT2;
1130         }
1131
1132         /*Dram timing parameters in clock cycles can be set in register DTPR0-2.
1133          *Refer to the SDRAM datasheet for detailed description about these timing in more frequence.
1134          */
1135         dtpr0 = ((tMRD & 0x03) << 0) |
1136             ((tRTP & 0x07) << 2) |
1137             ((tWTR & 0x07) << 5) |
1138             ((tRP & 0x0F) << 8) |
1139             ((tRCD & 0x0F) << 12) |
1140             ((tRAS & 0x1F) << 16) |
1141             ((tRRD & 0x0F) << 21) |
1142             ((tRC & 0x3F) << 25) | ((tCCD & 0x01) << 31);
1143
1144         dtpr1 = ((tAOND & 0x03) << 0) |
1145             /*((tRTW&0x01)<<2) | use default */
1146             ((tFAW & 0x3F) << 3) |
1147             ((tMOD & 0x03) << 9) |
1148             ((tRTODT & 0x0F) << 11) |
1149             ((tRFC & 0xFF) << 16) | ((tDQSCK & 0x07) << 24)
1150             /*((tDQSCKmax&0x07)<<27)use default */ ;
1151
1152         dtpr2 = ((tXS & 0x3FF) << 0) |
1153             ((tXP & 0x1F) << 10) |
1154             ((tCKE & 0x0F) << 15) | ((tDLLK & 0x3FF) << 19);
1155
1156         REG32(PUBL_DTPR0) = dtpr0;
1157         REG32(PUBL_DTPR1) = dtpr1;
1158         REG32(PUBL_DTPR2) = dtpr2;
1159 }
1160
1161 uint32 ddr_rw_chk_single(uint32 offset, uint32 data) {
1162         uint32 rd;
1163         *(volatile uint32 *)(SDRAM_BASE + offset) = data;
1164         rd = *(volatile uint32 *)(SDRAM_BASE + offset);
1165         if (rd == data)
1166                 return 1;
1167         else
1168                 return 0;
1169 }
1170
1171 uint32 ddr_rw_chk(uint32 offset) {
1172         uint32 i, data;
1173         for (i = 0; i < 6; i++) {
1174                 if (i == 0) {
1175                         data = 0x00000000;
1176                 } else if (i == 1) {
1177                         data = 0xffffffff;
1178                 } else if (i == 2) {
1179                         data = 0x12345678;
1180                 } else if (i == 3) {
1181                         data = 0x87654321;
1182                 } else if (i == 4) {
1183                         data = 0x5a5a5a5a;
1184                 } else if (i == 5) {
1185                         data = 0xa5a5a5a5;
1186                 }
1187                 if (ddr_rw_chk_single(offset, data) == 0)
1188                         return 0;
1189                 if (ddr_rw_chk_single(offset + 0x4, data) == 0)
1190                         return 0;
1191                 if (ddr_rw_chk_single(offset + 0x8, data) == 0)
1192                         return 0;
1193                 if (ddr_rw_chk_single(offset + 0xc, data) == 0)
1194                         return 0;
1195         }
1196         return 1;
1197 }
1198
1199 uint32 dqs_manual_training(uint32 offset) {
1200         uint32 i = 0;
1201         uint32 B0, B1, B2, B3;
1202         for (B0 = 0; B0 < 16; B0++) {
1203                 UMCTL_REG_SET(PUBL_DX0DQSTR, B0);
1204
1205                 for (B1 = 0; B1 < 16; B1++) {
1206                         UMCTL_REG_SET(PUBL_DX1DQSTR, B1);
1207
1208                         for (B2 = 0; B2 < 16; B2++) {
1209                                 UMCTL_REG_SET(PUBL_DX2DQSTR, B2);
1210                                 for (B3 = 0; B3 < 16; B3++) {
1211                                         UMCTL_REG_SET(PUBL_DX3DQSTR, B3);
1212
1213                                         if (ddr_rw_chk(offset)) {
1214                                                 UMCTL_REG_SET((SDRAM_BASE +
1215                                                                0x1000 + i),
1216                                                               (0xBA55 << 16) |
1217                                                               (B3 << 12) | (B2
1218                                                                             <<
1219                                                                             8) |
1220                                                               (B1 << 4) | B0);
1221
1222                                                 UMCTL_REG_SET(PUBL_DX0DQSTR,
1223                                                               (B0 << 4) | B0);
1224                                                 UMCTL_REG_SET(PUBL_DX1DQSTR,
1225                                                               (B1 << 4) | B1);
1226                                                 UMCTL_REG_SET(PUBL_DX2DQSTR,
1227                                                               (B2 << 4) | B2);
1228                                                 UMCTL_REG_SET(PUBL_DX3DQSTR,
1229                                                               (B3 << 4) | B3);
1230                                                 return 1;
1231                                         } else {
1232                                                 UMCTL_REG_SET((SDRAM_BASE +
1233                                                                0x1000 + i),
1234                                                               (0xFA11 << 16) |
1235                                                               (B3 << 12) | (B2
1236                                                                             <<
1237                                                                             8) |
1238                                                               (B1 << 4) | B0);
1239                                         }
1240                                         i = i + 4;
1241                                 }
1242                         }
1243                 }
1244         }
1245         //if not found, set as default value
1246         UMCTL_REG_SET(PUBL_DX0DQSTR, 0xAA);
1247         UMCTL_REG_SET(PUBL_DX1DQSTR, 0xAA);
1248         UMCTL_REG_SET(PUBL_DX2DQSTR, 0xAA);
1249         UMCTL_REG_SET(PUBL_DX3DQSTR, 0xAA);
1250         return 0;
1251 }
1252
1253 /*
1254  *Init sdram with publ build-in test.
1255  *Do training routine defined in PUBL_CFG_PIR.
1256 */
1257 void phy_start_init(DRAM_DESC * dram) {
1258         uint8 dram_type = dram->dram_type;
1259         /*PGCR:PHY general configuration register.
1260          *[:0]-ITMDMD;0=ITMS uses DQS and DQS#,1=ITMS uses DQS only.
1261          *[:1]-DQSCFG;0=DQS gating is shut off using the rising edge of DQS_b(active windowing mode)
1262          *           1=DQS gating blankets the whole burst(passive windowing mode).
1263          *           Note:passive windowing must be used for LPDDR2
1264          *[:2]-DFTCMP;0=disable data strobe drift compensation,1=Enable
1265          *[4:3]-DFTLMT;DQS drift limit:0=NoLimit,1=90'C drift,2=180'C drift,3=270'C or more drift
1266          *[8:5]-DTOSEL;DigitalTestOutputSelect:
1267          *[11:9]-CKEN;Control whether the CK going to the SDRAM is enable(toggling) or disable.
1268          *[13:12]-CKDV;CK disable value.
1269          *[14]-CKINV
1270          *[15]-IOLB
1271          *[17:16]-IODDRM
1272          *[21:18]-RANKEN;Enable the ranks that are enabled for data-training. bit_n control trank_n.
1273          *[23:22]-ZCKSEL
1274          *[24]-PDDISDX
1275          *[28:25]-RFSHDT;Refresh during training.
1276          *[29]-LBDQSS
1277          *[30]-LBGQSS
1278          *[31]-LBMODE
1279          */
1280         reg_bits_set(PUBL_PGCR, 0, 1, (dram_type == DRAM_LPDDR1) ? 0x01 : 0x00);
1281         reg_bits_set(PUBL_PGCR, 1, 2, 0x01);    //attention lpddr1 set 0x01
1282         reg_bits_set(PUBL_PGCR, 18, 4, 0x03);
1283
1284         /*DSGCR:ddr system general configuration register.
1285          *[0]-PUREN;phy update request enable.
1286          *[1]-BDISEN;Byte disable enable.If set PHY should respond to DFI byte disable request.
1287          *[2]-ZUEN;Impedance update enable.If set PHY should perform impedance calibraion
1288          *         whenever there is a controller initiated DFI update request.
1289          *[3]-LPIOPD;Low power I/O power down.
1290          *[4]-LPDLLPD;
1291          *[07:5]-DQSGX,dqs gate extension.
1292          *[10:8]-DQSGE,dqs gate early.
1293          *[19:16]-CKEPDD,cke power down driver.
1294          *[23:20]-ODTPDD,ODT power down driver.
1295          */
1296         //xiaohui   yanbin_debug changde default:0xFA00001F
1297         /*if((dram_type==DRAM_LPDDR2) || (dram_type==DRAM_DDR3))
1298            reg_bits_set(PUBL_DSGCR,  0,12, 0x25F);
1299          */
1300         /*polling whether PHY initialization done */
1301         /*PGSR:phy general status register.
1302          *[0]-IDONE,initialization done.This bit is set after all the selected initializatin
1303          *    routines in PIR register has completed.
1304          *[1]-DLDONE,dll lock done.
1305          *[2]-ZCDONE,impedance calibrarion done.
1306          *[3]-DIDONE,DRAM initialization done
1307          *[4]-DTDONE,data training done.
1308          *[5]-DTERR,data training error.
1309          *[6]-DTIERR,data training intermittent error.
1310          *[7]-DFTERR,DQS drift Error.
1311          *[30:8]-reserved
1312          *[31]-TQ,temperature output(LPDDR only)
1313          */
1314         while (UMCTL_REG_GET(PUBL_PGSR) & 0x03 != 0x03) ;
1315
1316 //kevin.yanbin
1317         {
1318                 uint32 value_temp = 0, i = 0;
1319                 //triggering publ PIR initialization
1320                 UMCTL_REG_SET(PUBL_PIR, 0x00040001);
1321                 for (i = 0; i <= 100; i++) ;
1322
1323                 //waite for initialize done
1324                 do {
1325                         value_temp = UMCTL_REG_GET(PUBL_PGSR);
1326                 }
1327                 while ((value_temp & 0x1) != 0x1);
1328         }
1329
1330         /*PIR:phy initialization register.
1331          *[0]-trigger init routine
1332          *[1]-Dll soft reset
1333          *[2]-Dll lock
1334          *[3]-Impendence calibration
1335          *[4]-Interface timing module soft reset
1336          *[5]*DRAM reset (DDR3 only)
1337          *[6]-DRAM initialization
1338          *[7]-QSTRN,read DQS training
1339          *[8]-EYETRN,Read data eye training,(Not supported in PUBL)
1340          */
1341         reg_bits_set(PUBL_PIR, 0, 32, 0x41);    /*trigger and do dram init */
1342
1343         while (!(UMCTL_REG_GET(PUBL_PGSR) & BIT_0)) ;   /*wait dram init done */
1344
1345 #if 1
1346         dqs_manual_training(0x00);
1347 #else
1348         /*use build-in DQS training,FPGA not support */
1349         reg_bits_set(PUBL_PIR, 0, 32, 0x81);    /*trigger and do read DQS training */
1350         DELAY_CLK(100);
1351         while (!(UMCTL_REG_GET(PUBL_PGSR) & BIT_4)) ;   /*wait data training done */
1352 #endif
1353         /*!!PHY initialization complete!! */
1354 }
1355
1356 /*
1357  *configure DATx8 register and its timing.
1358  *xiaohui.beijing
1359 */
1360 void phy_datx8_config(DRAM_DESC * dram) {
1361         uint8 dram_type = dram->dram_type;
1362         /*datx8 common configuration register (DXCCR) */
1363         /*[1]: */
1364         reg_bits_set(PUBL_DXCCR, 1, 1,
1365                      ((dram_type == DRAM_LPDDR2) ? 0x00 : 0x01));
1366         /*[7:4]: */
1367         reg_bits_set(PUBL_DXCCR, 4, 4,
1368                      ((dram_type == DRAM_LPDDR2) ? 0x04 : 0x00) | ((dram_type ==
1369                                                                     DRAM_LPDDR1)
1370                                                                    ? 0x04 :
1371                                                                    0x00));
1372         /*[11:8]: */
1373         reg_bits_set(PUBL_DXCCR, 8, 4,
1374                      ((dram_type == DRAM_LPDDR2) ? 0x0C : 0x00) | ((dram_type ==
1375                                                                     DRAM_LPDDR1)
1376                                                                    ? 0x0C :
1377                                                                    0x00));
1378         /*[14]: */
1379         reg_bits_set(PUBL_DXCCR, 14, 1,
1380                      ((dram_type == DRAM_LPDDR2) ? 0x00 : 0x01));
1381
1382         /*DXxGCR[10:9]:disable DQ/DQS dynamic RTT controll */
1383         reg_bits_set(PUBL_DX0GCR, 9, 2, 0x00);
1384         reg_bits_set(PUBL_DX1GCR, 9, 2, 0x00);
1385         reg_bits_set(PUBL_DX2GCR, 9, 2, 0x00);
1386         reg_bits_set(PUBL_DX3GCR, 9, 2, 0x00);
1387
1388         reg_bits_set(PUBL_DX0DQTR, 0, 5, 0xf);
1389         reg_bits_set(PUBL_DX1DQTR, 0, 5, 0xf);
1390         reg_bits_set(PUBL_DX2DQTR, 0, 5, 0xf);
1391         reg_bits_set(PUBL_DX3DQTR, 0, 5, 0xf);
1392 }
1393
1394 /*
1395  *Use umctl controller to initialize Mode register in sdram.
1396  *Refer to PUBL databook Chapter 3.3.13(MR0)~3.3.16(MR3) for detail.
1397 */
1398 void publ_mdr_init(DRAM_DESC * dram) {
1399         uint8 dram_type = dram->dram_type;
1400         uint8 BL = dram->bl;
1401         uint8 CL = dram->rl;
1402         uint8 RL = dram->rl;
1403         uint8 WL = dram->wl;
1404         uint8 AL = dram->al;
1405
1406         /*Get the timing we used. */
1407         LPDDR_ACTIMING *lpddr1_timing = (LPDDR_ACTIMING *) (dram->ac_timing);
1408         LPDDR2_ACTIMING *lpddr2_timing = (LPDDR2_ACTIMING *) (dram->ac_timing);
1409         DDR2_ACTIMING *ddr2_timing = (DDR2_ACTIMING *) (dram->ac_timing);
1410         DDR3_ACTIMING *ddr3_timing = (DDR3_ACTIMING *) (dram->ac_timing);
1411
1412         if (dram_type == DRAM_DDR3) {
1413                 uint8 tWR = ddr3_timing->tWR;
1414                 uint8 CWL = (WL - AL) ? (WL - AL) : 0x00;
1415                 /*Mode register 0(MR0) */
1416                 reg_bits_set(PUBL_MR0, 0, 2, ((BL == 8) ? 0x00 : 0x00) |        /*Fixed on 8 */
1417                              ((BL == 4) ? 0x01 : 0x00) |        /*4or8 on the fly */
1418                              ((BL == 4) ? 0x02 : 0x00));        /*Fixed on 4 */
1419                 /*BurstType:0-sequential;1-interleave */
1420                 reg_bits_set(PUBL_MR0, 3, 1,
1421                              ((BURST_TYPE ==
1422                                DRAM_BT_SEQ) ? 0x00 : 0x00) | ((BURST_TYPE ==
1423                                                                DRAM_BT_INTER) ?
1424                                                               0x01 : 0x00));
1425                 reg_bits_set(PUBL_MR0, 4, 3, ((CL == 5) ? 0x01 : 0x00) |        /*CAS Latency */
1426                              ((CL == 6) ? 0x02 : 0x00) |
1427                              ((CL == 7) ? 0x03 : 0x00) |
1428                              ((CL == 8) ? 0x04 : 0x00) |
1429                              ((CL == 9) ? 0x05 : 0x00) |
1430                              ((CL == 10) ? 0x06 : 0x00) |
1431                              ((CL == 11) ? 0x07 : 0x00));
1432                 reg_bits_set(PUBL_MR0, 7, 1, 0x00);     /*OperationMode:0-opMode;1-TestMode */
1433                 reg_bits_set(PUBL_MR0, 8, 1, 0x00);     /*DLLReset:1-ResetDll,this bit is self-clearing */
1434                 reg_bits_set(PUBL_MR0, 9, 3, ((tWR <= 5) ? 0x01 : 0x00) |       /*WriteRecovery */
1435                              ((tWR == 6) ? 0x02 : 0x00) |
1436                              ((tWR == 7) ? 0x03 : 0x00) |
1437                              ((tWR == 8) ? 0x04 : 0x00) |
1438                              ((tWR == 10) ? 0x05 : 0x00) |
1439                              ((tWR == 12) ? 0x06 : 0x00));
1440                 /*PowerdownControl:0-SlowExit(DllOff);1-FastExit(DllOn) */
1441                 reg_bits_set(PUBL_MR0, 12, 1, 0x00);
1442
1443                 /*Mode register 1(MR1) */
1444                 reg_bits_set(PUBL_MR1, 0, 1, 0x00);     /*DllEnable(0),DllDis(1) */
1445                 /*Output Driver Impedance Control
1446                    [A5,A1]:00-RZQ/6;01-RZQ/7;10/11-RZQ/TBD;Note: RZQ=240ohm */
1447                 reg_bits_set(PUBL_MR1, 1, 1, 0);
1448                 reg_bits_set(PUBL_MR1, 5, 1, 0);
1449                 /*[A4:A3]:Additive Latency. */
1450                 reg_bits_set(PUBL_MR1, 3, 2, ((AL == 0) ? 0x00 : 0x00) |
1451                              ((AL == CL - 1) ? 0x01 : 0x00) |
1452                              ((AL == CL - 2) ? 0x02 : 0x00)
1453                     );
1454                 /*[A7]:1-Write leveling enable;0-Disabled */
1455                 reg_bits_set(PUBL_MR1, 7, 1, 1);
1456
1457                 /*mr2 store the value to write to MR2 register */
1458                 /*Partial Array Self-Refresh (Optional),[A2:A0]
1459                  */
1460                 /*CAS write Latency (CWL),WL=CWL+AL
1461                    [A5:A3]:5~12 tCK
1462                  */
1463                 reg_bits_set(PUBL_MR1, 3, 3, ((CWL == 5) ? 0x00 : 0x00) |
1464                              ((CWL == 6) ? 0x01 : 0x00) |
1465                              ((CWL == 7) ? 0x02 : 0x00) |
1466                              ((CWL == 8) ? 0x03 : 0x00) |
1467                              ((CWL == 9) ? 0x04 : 0x00) |
1468                              ((CWL == 10) ? 0x05 : 0x00) |
1469                              ((CWL == 11) ? 0x06 : 0x00) |
1470                              ((CWL == 12) ? 0x07 : 0x00)
1471                     );
1472                 /*Rtt_WR
1473                    00-Dynamic ODT off; 01-RZQ/4;
1474                    10-RZQ/2;           11-Reserved
1475                  */
1476                 reg_bits_set(PUBL_MR1, 9, 2, 0x02);
1477         } else if (dram_type == DRAM_DDR) {
1478                 /*to be done */
1479         } else if (dram_type == DRAM_LPDDR1) {
1480                 /*Mode register 0(MR0) */
1481                 reg_bits_set(PUBL_MR0, 0, 3, ((BL == 2) ? 0x01 : 0x00) |
1482                              ((BL == 4) ? 0x02 : 0x00) |
1483                              ((BL == 8) ? 0x03 : 0x00) |
1484                              ((BL == 16) ? 0x04 : 0x00));
1485                 /*BurstType:0-sequential;1-interleave */
1486                 reg_bits_set(PUBL_MR0, 3, 1,
1487                              ((BURST_TYPE ==
1488                                DRAM_BT_SEQ) ? 0x00 : 0x00) | ((BURST_TYPE ==
1489                                                                DRAM_BT_INTER) ?
1490                                                               0x01 : 0x00));
1491                 reg_bits_set(PUBL_MR0, 4, 3, ((CL == 2) ? 0x02 : 0x00) |        /*CAS Latency */
1492                              ((CL == 3) ? 0x03 : 0x00) |
1493                              ((CL == 4) ? 0x04 : 0x00));
1494                 reg_bits_set(PUBL_MR0, 7, 1, 0x00);     /*OperationMode:0-opMode;1-TestMode */
1495                 reg_bits_set(PUBL_MR0, 8, 8, 0x00);     /*[15:8] Reserved. */
1496
1497                 /*Mode register 2(map to LPDDR EMR) */
1498                 reg_bits_set(PUBL_MR2, 0, 3, 0x00);     /*PASR:0:AllBanks;1:HalfArray;2:QuarterArray,etc */
1499                 reg_bits_set(PUBL_MR2, 3, 2, 0x00);     /*TCSR:0:70'C;1:45'C;2:15'C;3:85'C; */
1500                 reg_bits_set(PUBL_MR2, 5, 3,
1501                              ((IO_DS == DS_FULL) ? 0x00 : 0x00) | ((IO_DS ==
1502                                                                     DS_HALF) ?
1503                                                                    0x01 : 0x00)
1504                              | ((IO_DS == DS_QUARTER) ? 0x02 : 0x00) |
1505                              ((IO_DS == DS_OCTANT) ? 0x03 : 0x00) | ((IO_DS ==
1506                                                                       DS_THREE_QUATERS)
1507                                                                      ? 0x04 :
1508                                                                      0x00)
1509                     );          /*DS:0:FullDriverStrength;1:HalfDS;2:QuaterDS;3:OctantDS;4:Three-Quater */
1510                 reg_bits_set(PUBL_MR2, 8, 8, 0x00);     /*[15:8] Reserved. */
1511         } else if (dram_type == DRAM_DDR2) {
1512                 /*to be done */
1513         } else if (dram_type == DRAM_LPDDR2) {
1514                 uint8 tWR = lpddr2_timing->tWR;
1515                 /*Mode register 1(MR1) */
1516                 reg_bits_set(PUBL_MR0, 0, 32, 0x00);
1517                 /*Mode register 1(MR1) */
1518                 reg_bits_set(PUBL_MR1, 0, 3, ((BL == 4) ? 0x02 : 0x00) |
1519                              ((BL == 8) ? 0x03 : 0x00) |
1520                              ((BL == 16) ? 0x04 : 0x00));
1521                 /*BurstType:0-sequential;1-interleave */
1522                 reg_bits_set(PUBL_MR1, 3, 1,
1523                              ((BURST_TYPE ==
1524                                DRAM_BT_SEQ) ? 0x00 : 0x00) | ((BURST_TYPE ==
1525                                                                DRAM_BT_INTER) ?
1526                                                               0x01 : 0x00));
1527                 reg_bits_set(PUBL_MR1, 4, 1, 0x00);     /*WrapControl:0-wrap;1-Nowrap */
1528                 reg_bits_set(PUBL_MR1, 5, 3, ((tWR == 3) ? 0x01 : 0x00) |       /*WriteRecovery,Default(0x01) */
1529                              ((tWR == 4) ? 0x02 : 0x00) |
1530                              ((tWR == 5) ? 0x03 : 0x00) |
1531                              ((tWR == 6) ? 0x04 : 0x00) |
1532                              ((tWR == 7) ? 0x05 : 0x00) |
1533                              ((tWR == 8) ? 0x06 : 0x00));
1534
1535                 /*Mode register 2(MR2) */
1536                 reg_bits_set(PUBL_MR2, 0, 4, (((RL == 3)
1537                                                && (WL ==
1538                                                    1)) ? 0x01 : 0x00) | (((RL ==
1539                                                                            4)
1540                                                                           && (WL
1541                                                                               ==
1542                                                                               2))
1543                                                                          ? 0x02
1544                                                                          : 0x00)
1545                              | (((RL == 5)
1546                                  && (WL == 2)) ? 0x03 : 0x00) | (((RL == 6)
1547                                                                   && (WL ==
1548                                                                       3)) ? 0x04
1549                                                                  : 0x00) |
1550                              (((RL == 7)
1551                                && (WL == 4)) ? 0x05 : 0x00) | (((RL == 8)
1552                                                                 && (WL ==
1553                                                                     4)) ? 0x06 :
1554                                                                0x00));
1555                 reg_bits_set(PUBL_MR2, 4, 4, 0x00);     /*Reserved. */
1556
1557                 /*Mode register 3(MR3) */
1558                 /*DS,driver strength configuration.Default,40ohm */
1559                 reg_bits_set(PUBL_MR3, 0, 4,
1560                              ((IO_DS == DS_34R3) ? 0x01 : 0x00) | ((IO_DS ==
1561                                                                     DS_40R) ?
1562                                                                    0x02 : 0x00)
1563                              | ((IO_DS == DS_48R) ? 0x03 : 0x00) |
1564                              ((IO_DS == DS_60R) ? 0x04 : 0x00) | ((IO_DS ==
1565                                                                    DS_68R6) ?
1566                                                                   0x05 : 0x00) |
1567                              ((IO_DS == DS_80R) ? 0x06 : 0x00) | ((IO_DS ==
1568                                                                    DS_120R) ?
1569                                                                   0x07 : 0x00));
1570                 reg_bits_set(PUBL_MR2, 4, 4, 0x00);     /*[7:4],Reserved. */
1571         } else if (dram_type == DRAM_LPDDR3) {
1572                 /*to be done */
1573         }
1574 }
1575
1576 void sdram_clk_sel(DRAM_DESC * dram, uint32 clock) {
1577         /*changde to be done */
1578         //SDRAM_CORE_CLK = clock;
1579 }
1580
1581 /**---------------------------------------------------------------------------*
1582  **                            PUBLIC Functions
1583  **---------------------------------------------------------------------------*/
1584 /*
1585  *Init the sdram using uMCTL and PUBL.
1586  *Refer to uMCTL2 user guide Chapter3.1.5 Table3-2
1587  *"DWC_ddr_umctl2 and memory initialization with PUBL"
1588 */
1589
1590 void sdram_init(void) {
1591         DRAM_DESC *dram = SDRAM_GetCfg();
1592          DDR_init(dram);
1593 } void DDR_init(DRAM_DESC * dram) {
1594 /*NOTE:
1595  *Ensure that initializing all APB registers in reset mode,except for Dynamic Registers.
1596  */
1597         sdram_clk_sel(dram, SDRAM_CORE_CLK);
1598         umctl_soft_reset(TRUE);
1599         UMCTL_REG_SET(UMCTL_DFIMISC, 0x0);
1600         //umctl_wait_status(OPERATION_MODE_INIT);
1601         umctl_core_init(dram);
1602         /*Power-up timing initialization and ModeRegister. */
1603         umctl_poweron_init(dram);
1604     /**Set sdram timing parameters,MCTL_DRAMTMG0~MCTL_DRAMTMG8.*/
1605         umctl_sdram_timing(dram);
1606         umctl_soft_reset(FALSE);
1607
1608         //DFI initialization
1609         //Address mapping
1610         //PERFxx setting
1611         //Each port configuration
1612         umctl_other_init(dram);
1613         umctl_wait_status(OPERATION_MODE_NORMAL);
1614
1615         /*configure PUBL_CFG_PTR0/1/2 and PUBL_CFG_DTPR0/1/2 */
1616         phy_sdram_timing(dram);
1617         /*configure mdr in phy */
1618         publ_mdr_init(dram);
1619         phy_datx8_config(dram);
1620         phy_start_init(dram);
1621
1622         /*configure power control */
1623         UMCTL_REG_SET(UMCTL_PWRCTL, 0x08);
1624 }
1625