arch/arm/cpu/armv7/sc8830/shark_boot_cp.c

   1 #include <normal_mode.h>
   2 static u32 state;
   3
   4 /*void boot_cp0(void)
   5 {
   6         u32 cp0data[3] = {0xe59f0000, 0xe12fff10, WMODEM_ADR};
   7         memcpy(CP0_CODE_COPY_ADR, cp0data, sizeof(cp0data));       // copy cp0 source code
   8         *((volatile u32*)CP_SOFT_RST_ADR) |=  BIT_0;       // reset cp0
   9         *((volatile u32*)PD_CP0_SYS_CFG_ADR) &= ~BIT_25;           //clear cp0 force shutdown
  10
  11         while(1)
  12         {
  13                 state = *((volatile u32*)PWR_STATUS1_DBG_ADR);
  14                 if (!(state & (0xf<<28)))
  15                         break;
  16         }
  17         *((volatile u32*)PD_CP0_SYS_CFG_ADR) &= ~BIT_31;           // clear cp0 force deep sleep
  18 }*/
  19
  20 /*both CP0 and CP1 are not booted here for shark 9620,
  21 currently delete CP0 part to avoid compile error ,in 9620
  22 , currently WMODEM_ADR is not defined*/
  23
  24
  25 void boot_cp1(void)
  26 {
  27         u32 cp1data[3] = {0xe59f0000, 0xe12fff10, TDMODEM_ADR};
  28         memcpy(CP1_CODE_COPY_ADR, cp1data, sizeof(cp1data));      /* copy cp1 source code */
  29         *((volatile u32*)CP_SOFT_RST_ADR) |=  BIT_1;       /* reset cp1 */
  30         *((volatile u32*)PD_CP1_SYS_CFG_ADR) &= ~BIT_25;       /* clear cp1 force shutdown */
  31
  32         while(1)
  33         {
  34                 state = *((volatile u32*)PWR_STATUS2_DBG_ADR);
  35                 if (!(state & (0xf<<16)))
  36                         break;
  37         }
  38
  39         *((volatile u32*)PD_CP1_SYS_CFG_ADR) &= ~BIT_28;       /* clear cp1 force deep sleep */
  40 }
  41
  42 void boot_cp2(void)
  43 {
  44         u32 cp2data[3] = {0xe59f0000, 0xe12fff10, WCNMODEM_ADR};
  45         memcpy(CP2_CODE_COPY_ADR, cp2data, sizeof(cp2data));       /* copy cp2 source code */
  46         *((volatile u32*)CP_SOFT_RST_ADR) |=  BIT_2;       /* reset cp2 */
  47         *((volatile u32*)PD_CP2_ARM9_CFG_ADR) &= ~BIT_25;          /* clear cp2 force shutdown */
  48
  49         while(1)
  50         {
  51                 state = *((volatile u32*)PWR_STATUS3_DBG_ADR);
  52                 if (!(state & (0xf<<16)))
  53                 break;
  54         }
  55
  56         *((volatile u32*)PD_CP2_SYS_CFG_ADR) &= ~(BIT_28 | BIT_25);        /*system force shutdown deep_sleep*/
  57         *((volatile u32*)CP_SOFT_RST_ADR) &= ~(BIT_0 | BIT_1 | BIT_2);     /* clear reset cp0 cp1 cp2 */
  58 }