arch/arm/cpu/armv7/sc8830/chip_x30g/low_power.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5 #include <asm/arch/low_power.h>
   6
   7 //#define LDO_SLP_DEBUG
   8 #ifdef LDO_SLP_DEBUG
   9 typedef struct slp_test {
  10         unsigned int                                            reg;
  11         unsigned int                                            val;
  12 }test_t;
  13 test_t b[60] = {0x0};
  14
  15 void test_store (test_t *buf)
  16 {
  17         unsigned int i = 0, j = 0;
  18         buf[i].reg = ANA_REG_GLB_LDO_PD_CTRL;
  19         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_PD_CTRL);
  20
  21         buf[i].reg = ANA_REG_GLB_LDO_SLP_CTRL0;
  22         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_SLP_CTRL0);
  23
  24         buf[i].reg = ANA_REG_GLB_LDO_SLP_CTRL1;
  25         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_SLP_CTRL1);
  26
  27         buf[i].reg = ANA_REG_GLB_LDO_SLP_CTRL2;
  28         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_SLP_CTRL2);
  29
  30         buf[i].reg = ANA_REG_GLB_LDO_SLP_CTRL3;
  31         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_SLP_CTRL3);
  32
  33         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN0;
  34         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN0);
  35
  36         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN1;
  37         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN1);
  38
  39         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN2;
  40         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN2);
  41
  42         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN3;
  43         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN3);
  44
  45         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN4;
  46         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN4);
  47
  48         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN5;
  49         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN5);
  50
  51         buf[i].reg = ANA_REG_GLB_LDO1828_XTL_CTL;
  52         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO1828_XTL_CTL);
  53
  54         buf[i].reg = ANA_REG_GLB_SLP_WAIT_DCDCARM;
  55         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_SLP_WAIT_DCDCARM);
  56
  57         buf[i].reg = REG_PMU_APB_XTL0_REL_CFG;
  58         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL0_REL_CFG);
  59
  60         buf[i].reg = REG_PMU_APB_XTL1_REL_CFG;
  61         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL1_REL_CFG);
  62
  63         buf[i].reg = REG_PMU_APB_XTL2_REL_CFG;
  64         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL2_REL_CFG);
  65
  66         buf[i].reg = REG_PMU_APB_XTLBUF0_REL_CFG;
  67         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF0_REL_CFG);
  68
  69         buf[i].reg = REG_PMU_APB_XTLBUF1_REL_CFG;
  70         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF1_REL_CFG);
  71
  72         buf[i].reg = REG_PMU_APB_MPLL_REL_CFG;
  73         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_MPLL_REL_CFG);
  74
  75         buf[i].reg = REG_PMU_APB_DPLL_REL_CFG;
  76         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_DPLL_REL_CFG);
  77
  78         buf[i].reg = REG_PMU_APB_TDPLL_REL_CFG;
  79         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
  80
  81         buf[i].reg = REG_PMU_APB_WPLL_REL_CFG;
  82         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
  83
  84         buf[i].reg = REG_PMU_APB_CPLL_REL_CFG;
  85         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_CPLL_REL_CFG);
  86
  87         buf[i].reg = REG_PMU_APB_WIFIPLL1_REL_CFG;
  88         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WIFIPLL1_REL_CFG);
  89
  90         buf[i].reg = REG_PMU_APB_WIFIPLL2_REL_CFG;
  91         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WIFIPLL2_REL_CFG);
  92
  93 //      buf[i].reg = REG_PMU_APB_CGM_AP_EN;
  94 //      buf[i++].val = CHIP_REG_GET(REG_PMU_APB_CGM_AP_EN);
  95
  96         buf[i].reg = REG_PMU_APB_PD_CA7_TOP_CFG;
  97         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_TOP_CFG);
  98
  99         buf[i].reg = REG_PMU_APB_PD_CA7_C0_CFG;
 100         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C0_CFG);
 101
 102         buf[i].reg = REG_PMU_APB_PD_CA7_C1_CFG;
 103         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C1_CFG);
 104
 105         buf[i].reg = REG_PMU_APB_PD_CA7_C2_CFG;
 106         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C2_CFG);
 107
 108         buf[i].reg = REG_PMU_APB_PD_CA7_C3_CFG;
 109         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C3_CFG);
 110
 111         buf[i].reg = REG_PMU_APB_PD_AP_SYS_CFG;
 112         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_AP_SYS_CFG);
 113
 114         buf[i].reg = REG_PMU_APB_PD_MM_TOP_CFG;
 115         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_MM_TOP_CFG);
 116
 117         buf[i].reg = REG_PMU_APB_PD_GPU_TOP_CFG;
 118         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_GPU_TOP_CFG);
 119
 120         buf[i].reg = REG_PMU_APB_PD_PUB_SYS_CFG;
 121         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_PUB_SYS_CFG);
 122
 123         buf[i].reg = REG_PMU_APB_XTL_WAIT_CNT;
 124         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL_WAIT_CNT);
 125
 126         buf[i].reg = REG_PMU_APB_XTLBUF_WAIT_CNT;
 127         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF_WAIT_CNT);
 128
 129         buf[i].reg = REG_PMU_APB_PLL_WAIT_CNT1;
 130         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PLL_WAIT_CNT1);
 131
 132         buf[i].reg = REG_PMU_APB_PLL_WAIT_CNT2;
 133         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PLL_WAIT_CNT2);
 134
 135
 136         buf[i].reg = i;
 137         buf[i].val = 0x55AA55AA;
 138
 139         for(j = 0; j < i; j++) {
 140                 printf("addr:0x%.8x, val:0x%.8x\n",buf[j].reg,buf[j].val);
 141         }
 142 }
 143 #endif
 144
 145 static struct ldo_lowpower_cfg *gp_ldo_cfg = NULL;
 146 static struct pll_cfg *gp_pll_cfg = NULL;
 147 static struct shutdown_cfg *gp_shutdown_cfg = NULL;
 148
 149 void customize_low_power_init_prepare(struct ldo_lowpower_cfg *ldo,
 150                                                                 struct pll_cfg *pll,
 151                                                                 struct shutdown_cfg *shutdown)
 152 {
 153         gp_ldo_cfg = ldo;
 154         gp_pll_cfg = pll;
 155         gp_shutdown_cfg = shutdown;
 156 }
 157
 158 static void switch_protect(unsigned int rf_id)
 159 {
 160    unsigned int pll_reg;
 161 /* before switch reference crystal, it must be sure that no module is using TDPLL */
 162     pll_reg = CHIP_REG_GET(REG_AP_CLK_AP_AHB_CFG);
 163     pll_reg &= ~AP_AHB_CLK_SEL_MASK;
 164     CHIP_REG_SET(REG_AP_CLK_AP_AHB_CFG,pll_reg);
 165
 166     pll_reg = CHIP_REG_GET(REG_AON_CLK_PUB_AHB_CFG);
 167     pll_reg &= ~PUB_AHB_CLK_SEL_MASK;
 168     CHIP_REG_SET(REG_AON_CLK_PUB_AHB_CFG,pll_reg);
 169
 170     pll_reg = CHIP_REG_GET(REG_AP_CLK_AP_APB_CFG);
 171     pll_reg &= ~AP_APB_CLK_SEL_MASK;
 172     CHIP_REG_SET(REG_AP_CLK_AP_APB_CFG,pll_reg);
 173
 174     pll_reg = CHIP_REG_GET(REG_AON_CLK_AON_APB_CFG);
 175     pll_reg &= ~PUB_APB_CLK_SEL_MASK;
 176     CHIP_REG_SET(REG_AON_CLK_AON_APB_CFG,pll_reg);
 177
 178     pll_reg = CHIP_REG_GET(REG_AON_APB_PLL_SOFT_CNT_DONE);
 179     pll_reg &= ~(BIT_TDPLL_SOFT_CNT_DONE);
 180     CHIP_REG_SET(REG_AON_APB_PLL_SOFT_CNT_DONE,pll_reg);
 181     udelay(1);
 182
 183 /* switch TDPLL reference crystal */
 184     if (rf_id == 0)
 185     {
 186         pll_reg = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 187         pll_reg &= ~(0x1 << 4);
 188         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,pll_reg);
 189
 190         pll_reg = CHIP_REG_GET(REG_PMU_APB_XTL0_REL_CFG);
 191         pll_reg |= BIT_XTL1_AP_SEL;
 192         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,pll_reg);
 193
 194         pll_reg = CHIP_REG_GET(REG_PMU_APB_XTLBUF0_REL_CFG);
 195         pll_reg |= BIT_XTLBUF1_AP_SEL;
 196         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,pll_reg);
 197     }
 198     else if(rf_id == 1)
 199     {
 200
 201         pll_reg = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 202         pll_reg |= (0x1 << 4);
 203         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,pll_reg);
 204
 205         pll_reg = CHIP_REG_GET(REG_PMU_APB_XTL1_REL_CFG);
 206         pll_reg |= BIT_XTL1_AP_SEL;
 207         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,pll_reg);
 208
 209         pll_reg = CHIP_REG_GET(REG_PMU_APB_XTLBUF1_REL_CFG);
 210         pll_reg |= BIT_XTLBUF1_AP_SEL;
 211         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,pll_reg);
 212
 213
 214     }
 215
 216     pll_reg = CHIP_REG_GET(REG_AON_APB_PLL_SOFT_CNT_DONE);
 217     pll_reg |= (BIT_TDPLL_SOFT_CNT_DONE);
 218     CHIP_REG_SET(REG_AON_APB_PLL_SOFT_CNT_DONE,pll_reg);
 219
 220     udelay(120);
 221
 222 /* after switch, up ahb clock to 128M, APB to 64M */
 223     pll_reg = CHIP_REG_GET(REG_AP_CLK_AP_AHB_CFG);
 224     pll_reg |= 0x3;
 225     CHIP_REG_SET(REG_AP_CLK_AP_AHB_CFG,pll_reg);
 226
 227     pll_reg = CHIP_REG_GET(REG_AON_CLK_PUB_AHB_CFG);
 228     pll_reg |= 0x3;
 229     CHIP_REG_SET(REG_AON_CLK_PUB_AHB_CFG,pll_reg);
 230
 231     pll_reg = CHIP_REG_GET(REG_AP_CLK_AP_APB_CFG);
 232     pll_reg |= 0x1;
 233     CHIP_REG_SET(REG_AP_CLK_AP_APB_CFG,pll_reg);
 234
 235     pll_reg = CHIP_REG_GET(REG_AON_CLK_AON_APB_CFG);
 236     pll_reg |= 0x3;
 237     CHIP_REG_SET(REG_AON_CLK_AON_APB_CFG,pll_reg);
 238     printf("switch_protect end\n");
 239 }
 240
 241 static void lowpower_earlyinit(void)
 242 {
 243 //      ANA_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG, BIT_CP0_FORCE_DEEP_SLEEP);
 244 //      ANA_REG_SET(REG_PMU_APB_PD_CP1_SYS_CFG, BIT_CP1_FORCE_DEEP_SLEEP);
 245 //      ANA_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG, BIT_CP2_FORCE_DEEP_SLEEP);
 246
 247         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0, BIT_SLP_IO_EN);
 248         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1, BIT_SLP_LDO_PD_EN);
 249         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN);
 250
 251         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,0x0908);
 252 //      ANA_REG_SET(REG_PMU_APB_CGM_AP_EN,0x1fff81 );
 253
 254 //      ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, 0xffff);
 255 //      ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, 0xffff);
 256
 257 //      switch_protect(1);
 258 //      ANA_REG_SET(REG_PMU_APB_WPLL_REL_CFG,BIT_WPLL_REF_SEL);
 259 //      ANA_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,BIT_TDPLL_REF_SEL);
 260         /*plls wait, xtl0/1 wait, xtlbuf0/1 wait time*/
 261 }
 262
 263 static unsigned long ffs(unsigned int x)
 264 {
 265         unsigned long i = 0;
 266         if(x == 0)
 267                 i = 32;
 268         else {
 269                 while((x & (1<<i)) == 0) {
 270                         i ++;
 271                 }
 272                 i++;
 273         }
 274         return i;
 275 }
 276
 277 static unsigned long __ffs(unsigned int x)
 278 {
 279         return ffs(x) -1;
 280 }
 281
 282 /* pll */
 283 static void pll_xtl_with_sys_config(struct pll_cfg *cfg, struct pll_reg_bit *pll_reg)
 284 {
 285         /*enable all xtl for simply config.  xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
 286         unsigned int i = 0, j;
 287         unsigned int sel_mode = 0, sel_tmp = 0;
 288
 289         if ((!cfg) || (cfg[0].pll_id == RESERVED_NUM) || (pll_reg == NULL)) {
 290                 return;
 291         }
 292
 293         /*collecting the current system mode, like TD only ..etc.*/
 294         while (cfg[i].pll_id != RESERVED_NUM) {
 295                 j = 0;
 296                 while (pll_reg[j].pll_id != RESERVED_NUM) {
 297                         if (cfg[i].pll_id == pll_reg[j].pll_id) {
 298                                 break;
 299                         }
 300                         ++j;
 301                 }
 302
 303                 sel_mode = 0;
 304                 /* set select by ap,cp0,cp1,cp2 */
 305                 if (pll_reg[j].pll_sys_reg != -1) {
 306                         if(cfg[i].sys != DEFAULT) {
 307                                 if (cfg[i].sys & AP_SYS) {
 308                                         sel_mode |= BIT(0);
 309                                 }
 310                                 if (cfg[i].sys & CP0_SYS) {
 311                                         sel_mode |= BIT(1);
 312                                 }
 313                                 if (cfg[i].sys & CP1_SYS) {
 314                                         sel_mode |= BIT(2);
 315                                 }
 316                                 if (cfg[i].sys & CP2_SYS) {
 317                                         sel_mode |= BIT(3);
 318                                 }
 319
 320                                 sel_tmp = CHIP_REG_GET(pll_reg[j].pll_sys_reg);
 321                                 sel_tmp &= ~pll_reg[j].pll_sys_reg_bitmsk;
 322                                 sel_tmp |= (sel_mode << __ffs(pll_reg[j].pll_sys_reg_bitmsk)
 323                                                         & pll_reg[j].pll_sys_reg_bitmsk);
 324
 325                                 CHIP_REG_SET(pll_reg[j].pll_sys_reg, sel_tmp);
 326                         }
 327                 }
 328
 329                 if (pll_reg[j].pll_wait_reg != -1) {
 330                         if (cfg[i].wait != DEFAULT) {
 331                                 sel_mode = cfg[i].wait << __ffs(pll_reg[j].pll_wait_reg_bitmsk);
 332                                 sel_mode &= pll_reg[j].pll_wait_reg_bitmsk;
 333
 334                                 sel_tmp = CHIP_REG_GET(pll_reg[j].pll_wait_reg);
 335                                 sel_tmp &= ~pll_reg[j].pll_wait_reg_bitmsk;
 336                                 sel_tmp |= sel_mode;
 337
 338                                 CHIP_REG_SET(pll_reg[j].pll_wait_reg, sel_tmp);
 339                         }
 340                 }
 341
 342                 ++i;
 343         }
 344 }
 345
 346 static void pd_shutdown_config(struct shutdown_cfg *cfg,
 347                                                 struct pd_reg_bit *pd_reg)
 348 {
 349         /*enable all xtl for simply config.  xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
 350         unsigned int i = 0, j;
 351         unsigned int reg_value = 0;
 352
 353         if ((!cfg) || (cfg[0].pd_shutdown_id == RESERVED_NUM) || (pd_reg == NULL)) {
 354                 return;
 355         }
 356
 357         /*collecting the current system mode, like TD only ..etc.*/
 358         while (cfg[i].pd_shutdown_id != RESERVED_NUM) {
 359                 j = 0;
 360                 while (pd_reg[j].pd_shutdown_id != RESERVED_NUM) {
 361                         if (cfg[i].pd_shutdown_id == pd_reg[j].pd_shutdown_id) {
 362                                 break;
 363                         }
 364                         ++j;
 365                 }
 366
 367                 if (pd_reg[j].pd_shutdown_id == RESERVED_NUM) {
 368                         continue;
 369                 }
 370
 371                 if (pd_reg[j].pd_reg != -1) {
 372                         if(cfg[i].iso_on_delay != DEFAULT) {
 373                                 reg_value = cfg[i].iso_on_delay << __ffs(pd_reg[j].iso_on_delay_bitmsk);
 374                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].iso_on_delay_bitmsk);
 375                                 CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
 376                         }
 377
 378                         if(cfg[i].pwr_on_seq_delay != DEFAULT) {//pwr_on_seq_delay
 379                                 reg_value = cfg[i].pwr_on_seq_delay
 380                                                         << __ffs(pd_reg[j].pwr_on_seq_delay_bitmsk);
 381                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_seq_delay_bitmsk);
 382                                 CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
 383                         }
 384
 385                         if(cfg[i].pwr_on_delay != DEFAULT) {//pwr_on_delay
 386                                 reg_value = cfg[i].pwr_on_delay << __ffs(pd_reg[j].pwr_on_delay_bitmsk);
 387                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_delay_bitmsk);
 388                                 CHIP_REG_OR(pd_reg[j].pd_reg,reg_value);
 389                         }
 390
 391                         if(cfg[i].auto_shutdown != DEFAULT) {
 392                                 if(cfg[i].auto_shutdown == ENABLE) {//auto_shutdown
 393                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].auto_shutdown_bitmsk);
 394                                 }
 395                                 else if(cfg[i].auto_shutdown == DISABLE) {
 396                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].auto_shutdown_bitmsk);
 397                                 }
 398                         }
 399
 400                         if(cfg[i].force_shutdown != DEFAULT) {
 401                                 if(cfg[i].force_shutdown == ENABLE) {//force_shutdown
 402                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].force_shutdown_bitmsk);
 403                                 }
 404                                 else if(cfg[i].force_shutdown == DISABLE) {
 405                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].force_shutdown_bitmsk);
 406                                 }
 407                         }
 408
 409                         if(cfg[i].debug_shutdown != DEFAULT) {
 410                                 if(cfg[i].debug_shutdown == ENABLE) {//debug_shutdown
 411                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].debug_shutdown_bitmsk);
 412                                 }
 413                                 else if(cfg[i].debug_shutdown == DISABLE) {
 414                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~(pd_reg[j].debug_shutdown_bitmsk));
 415                                 }
 416                         }
 417                 }
 418                 ++i;
 419         }
 420 }
 421
 422 static void ddie_pll_lowpower_init(void)
 423 {
 424         /*default all:xtl0/1/2 to ap, default all:xtlbuf0/1 to ap +*/
 425         pll_xtl_with_sys_config(gp_pll_cfg, pll_reg_tb);
 426         pd_shutdown_config(gp_shutdown_cfg, shutdown_tb);
 427 }
 428
 429 /* ldo */
 430
 431 static  void ldo_set_sts(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 432 {
 433         if (reg->ldo_pd_reg != -1) {
 434                 if (cfg->ldo_pd == ON) {
 435                         ANA_REG_OR(reg->ldo_pd_reg, reg->ldo_pd_reg_bitmsk);
 436                 } else if (cfg->ldo_pd == OFF) {
 437                         ANA_REG_BIC(reg->ldo_pd_reg, reg->ldo_pd_reg_bitmsk);
 438                 }
 439         }
 440 }
 441
 442 static  void ldo_set_sts_sleep(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 443 {
 444         if (cfg->status_in_sleep == SLP_PD_MODE) {
 445                 if (reg->slp_pd_reg != -1) {
 446                         ANA_REG_OR(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 447                 }
 448                 if (reg->slp_lp_reg != -1) {
 449                         ANA_REG_BIC(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 450                 }
 451         } else if (cfg->status_in_sleep == SLP_LP_MODE) {
 452                 if (reg->slp_pd_reg != -1) {
 453                         ANA_REG_BIC(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 454                 }
 455                 if (reg->slp_lp_reg != -1) {
 456                         ANA_REG_OR(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 457                 }
 458         } else if (cfg->status_in_sleep == SLP_NO_MODE) {
 459                 if (reg->slp_pd_reg != -1) {
 460                         ANA_REG_BIC(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 461                 }
 462                 if (reg->slp_lp_reg != -1) {
 463                         ANA_REG_BIC(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 464                 }
 465         } else {
 466 //              printf("error for this callback ldo_set_sts_sleep\n");
 467         }
 468 }
 469
 470 /* ldo_id, cfg_to_xtl, cfg_to_ext_xtl,power_sts_in_sleep; */
 471 static void ldo_set_xtl(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 472 {
 473         unsigned int v = 0, tmp = 0;
 474         unsigned int shft = 0;
 475
 476         if (reg->xtl_reg != -1) {
 477                 shft = __ffs(reg->xtl_reg_bitmsk);
 478
 479                 if (cfg->select_by_xtl & BY_XTL0)
 480                         v |= BIT(0);
 481                 if (cfg->select_by_xtl & BY_XTL1)
 482                         v |= BIT(1);
 483                 if (cfg->select_by_xtl & BY_XTL2)
 484                         v |= BIT(2);
 485                 v = v << shft;
 486                 v &= reg->xtl_reg_bitmsk;
 487
 488                 tmp = ANA_REG_GET(reg->xtl_reg);
 489                 tmp &= ~reg->xtl_reg_bitmsk;
 490                 tmp |= v;
 491
 492                 ANA_REG_SET(reg->xtl_reg, tmp);
 493         }
 494 }
 495
 496 static  void ldo_set_exxtl(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 497 {
 498         unsigned int v = 0, tmp = 0;
 499         unsigned int shft = 0;
 500
 501         if (reg->ext_xtl_reg != -1) {
 502                 shft = __ffs(reg->ext_xtl_reg_bitmsk);
 503
 504                 if (cfg->select_by_ext_xtl & BY_EXT_XTL0)
 505                         v |= BIT(0);
 506                 if (cfg->select_by_ext_xtl & BY_EXT_XTL1)
 507                         v |= BIT(1);
 508                 if (cfg->select_by_ext_xtl & BY_EXT_XTL2)
 509                         v |= BIT(2);
 510
 511                 v = v << shft;
 512                 v &= reg->ext_xtl_reg_bitmsk;
 513
 514                 tmp = ANA_REG_GET(reg->ext_xtl_reg);
 515                 tmp &= ~reg->ext_xtl_reg_bitmsk;
 516                 tmp |= v;
 517
 518                 ANA_REG_SET(reg->ext_xtl_reg, tmp);
 519         }
 520 }
 521
 522 static void adie_ldo_lowpower_init()
 523 {
 524         struct ldo_lowpower_cfg *ldo_cfg = gp_ldo_cfg;
 525         struct ldo_reg_bit *ldo_reg = ldo_reg_tb;
 526         unsigned int i = 0, j = 0;
 527
 528         if ((!ldo_cfg) || (ldo_reg == NULL))
 529                 return;
 530
 531         while (ldo_cfg[i].ldo_id != RESERVED_NUM) {
 532                 j = 0;
 533                 while (ldo_reg[j].ldo_id != RESERVED_NUM) {
 534                         if (ldo_cfg[i].ldo_id == ldo_reg[j].ldo_id) {
 535                                 break;
 536                         }
 537                         ++j;
 538                 }
 539
 540                 if (ldo_reg[j].ldo_id == RESERVED_NUM) {
 541                         continue;
 542                 }
 543
 544                 if (ldo_cfg[i].ldo_pd != DEFAULT) {
 545                         ldo_set_sts(&ldo_cfg[i], &ldo_reg[j]);
 546                 }
 547                 if (ldo_cfg[i].status_in_sleep != DEFAULT) {
 548                         ldo_set_sts_sleep(&ldo_cfg[i], &ldo_reg[j]);
 549                 }
 550                 if (ldo_cfg[i].select_by_xtl!= DEFAULT) {
 551                         ldo_set_xtl(&ldo_cfg[i], &ldo_reg[j]);
 552                 }
 553                 if (ldo_cfg[i].select_by_ext_xtl != DEFAULT) {
 554                         ldo_set_exxtl(&ldo_cfg[i], &ldo_reg[j]);
 555                 }
 556                 ++i;
 557         }
 558 }
 559
 560 void low_power_init(void)
 561 {
 562         /*
 563         Every ldo LP/PD depend on AP, we can make ap select xtl_buf_en0, xtl_buf_en1,
 564         xtl_buf_en2 and cp0 select xtl_buf_en0, cp1 select xtl-buf_en1, cp2 select xtl_buf_en2, so
 565         ldo_x can flexiblly config to xtl0/cp0, xtl1/cp1, xtl2/cp2. But now, we can make this process
 566         to simple. make xtl_buf_en0 == xtl_buf_en1 == xtl_buf_en2
 567         if cp(X) is exist, slecet all xtl_Buf_en0/1/2.
 568         */
 569         lowpower_earlyinit();
 570         ddie_pll_lowpower_init();
 571         adie_ldo_lowpower_init();
 572
 573         /* used test register */
 574 #ifdef LDO_SLP_DEBUG
 575         test_store(&b);
 576 #endif
 577 }