arch/arm/cpu/armv7/sc8830/chip_x30g/ap_cp_sync.s

   1         AREA    Init, CODE, READONLY
   2         ENTRY
   3         CODE32
   4
   5 DMC_RET
   6         CMP     r0,#0x0
   7         ADREQ   r3,AP_STACK
   8         CMP     r0,#0x1
   9         ADREQ   r3,CP0_STACK
  10         CMP     r0,#0x2
  11         ADREQ   r3,CP2_STACK
  12
  13         STMFD   r3!,{r4-r9,lr}
  14
  15         ADR     r5,REG_CTRL_INFO_STRUCT
  16         MOV     r4,#0x28
  17         MUL     r4,r0,r4
  18         ADD     r4,r4,r5
  19         MOV     r5,#0x14
  20         MUL     r6,r1,r5
  21         ADD     r4,r4,r6
  22         MUL     r6,r2,r5
  23         ADD     r4,r4,r6
  24
  25         CMP     r1,#0x1
  26         ;*(volatile unsigned int*)0x402b012c |= (0x1 << 24);
  27         LDREQ   r8,[r4,#0x04]
  28         LDREQ   r9,[r8,#0x12c]
  29         ORREQ   r9,r9,#0x01000000
  30         STREQ   r9,[r8,#0x12c]
  31         BEQ     finish
  32
  33         ;r2=is_exit_nopd == 1
  34         CMP     r2,#0x1
  35         BNE     no_delay
  36         ;get delay time
  37         ADR     r5,DELAY_TIME
  38         MOV     r6,r0,lsl #0x2
  39         ADD     r5,r5,r6
  40         LDR     r6,[r5]
  41 wait_loop
  42         SUB     r6,r6,#0x1
  43         CMP     r6,#0x0
  44         BNE     wait_loop
  45
  46 no_delay
  47         LDR     r8,[r4,#0x04]
  48 check_pub_fsm_0
  49         LDR     r9,[r8,#0xc8]
  50         AND     r9,r9,#0x00F0
  51         CMP     r9,#0x0
  52         BNE     check_pub_fsm_0
  53 check_phy_fsm_0
  54         LDR     r9,[r8,#0xc8]
  55         AND     r9,r9,#0xF000
  56         CMP     r9,#0x0
  57         BNE     check_phy_fsm_0
  58
  59         LDR     r5,[r4]
  60 get_hw_spinlock
  61         LDR     r6,[r5]
  62         CMP     r6,#0x0
  63         BNE     get_hw_spinlock
  64
  65         ;set information for who taken hw spinlock
  66         ADR     r8,DEBUG_INFO
  67         MOV     r9,#0x1
  68         MOV     r9,r9,lsl r0
  69         STR     r9,[r8,#0x0]
  70         STR     r1,[r8,#0x4]
  71         STR     r2,[r8,#0x8]
  72         MOV     r7,#0x0
  73         STR     r7,[r8,#0xc]
  74
  75         ;check ddr phy is power down
  76         LDR     r8,[r4,#0x10]
  77         LDR     r9,[r8]
  78         TST     r9,#0x1
  79         BNE     rel_hw_spinlock
  80         ORR     r9,r9,#0x1
  81         STR     r9,[r8]
  82
  83         ADR     r8,DEBUG_INFO
  84         ORR     r7,r7,#0x1
  85         STR     r7,[r8,#0xc]
  86
  87         LDR     r8,[r4,#0x8]
  88         ADR     r5,DMC_PHY_RET_CHECK
  89         LDR     r5,[r5]
  90 check_retention
  91         LDR     r9,[r8]
  92         CMP     r5,r9
  93         BNE     check_retention
  94
  95         ADR     r8,DEBUG_INFO
  96         ORR     r7,r7,#0x2
  97         STR     r7,[r8,#0xc]
  98
  99         LDR     r8,[r4,#0x0c]   ;r8=dfimisc address
 100         MOV     r9,#0x00
 101         STR     r9,[r8]
 102
 103         ADR     r8,DEBUG_INFO
 104         ORR     r7,r7,#0x4
 105         STR     r7,[r8,#0xc]
 106
 107         LDR     r8,[r4,#0x08]   ;r8=phy base address
 108         MOV     r9,#0x21
 109         STR     r9,[r8,#0x04]
 110
 111 check_point_0
 112         LDR     r9,[r8,#0x18]
 113         TST     r9,#0x1
 114         BEQ     check_point_0
 115
 116 check_point_1
 117         LDR     r9,[r8,#0x18]
 118         TST     r9,#0x1
 119         BEQ     check_point_1
 120
 121         ADR     r8,DEBUG_INFO
 122         ORR     r7,r7,#0x8
 123         STR     r7,[r8,#0xc]
 124
 125         LDR     r8,[r4,#0x0C]   ;r8=dfimisc address
 126         MOV     r9,#0x1
 127         STR     r9,[r8]
 128
 129         ADR     r8,DEBUG_INFO
 130         ORR     r7,r7,#0x10
 131         STR     r7,[r8,#0xc]
 132
 133 rel_hw_spinlock
 134         ;clear who taken hw spinlock
 135         ADR     r8,DEBUG_INFO
 136         MOV     r9,#0x0
 137         STR     r9,[r8]
 138
 139         LDR     r8,[r4]
 140         ADR     r9,SPINLOCK_31_MAGIC
 141         LDR     r9,[r9]
 142         STR     r9,[r8]
 143
 144         ;*(volatile unsigned int*)0x402b012c &= ~(0x1 << 24)
 145         LDR     r8,[r4,#0x04]
 146         LDR     r9,[r8,#0x12c]
 147         BIC     r9,r9,#0x01000000
 148         STR     r9,[r8,#0x12c]
 149
 150 finish
 151         LDMFD   r3!,{r4-r9,pc}
 152
 153 DMC_PHY_RET_CHECK
 154         DCD     0x00131154
 155 SPINLOCK_31_MAGIC
 156         DCD     0x55aa10c5
 157 REG_CTRL_INFO_STRUCT
 158         DCD     0x4006087c      ;ap aon spinlock phys address
 159         DCD     0x402b0000      ;ap aon phy auto en phys address
 160         DCD     0x30010000      ;ap ddr phy base phys address
 161         DCD     0x300001b0      ;ap umctl dfimisc phys address
 162         DCD     0x30040000      ;ap pub busmon reg phys address
 163
 164         DCD     0xF51F687c      ;ap aon spinlock virt address
 165         DCD     0xF5230000      ;ap aon phy auto ret en virt address
 166         DCD     0xF5170000      ;ap ddr phy base virt address
 167         DCD     0xF51601b0      ;ap umctl dfimisc virt address
 168         DCD     0xF519E000      ;ap pub busmon reg virt address
 169
 170         DCD     0x0206087c      ;cp0 aon spinlock phys address
 171         DCD     0x022b0000      ;cp0 aon phy auto en phys address
 172         DCD     0x01010000      ;cp0 ddr phy base phys address
 173         DCD     0x010001b0      ;cp0 umctl dfimisc phys address
 174         DCD     0x01040000      ;cp0 pub busmon reg phys address
 175
 176         DCD     0x0206087c      ;cp0 aon spinlock virt address
 177         DCD     0x022b0000      ;cp0 aon phy auto en virt address
 178         DCD     0x01010000      ;cp0 ddr phy base virt address
 179         DCD     0x010001b0      ;cp0 umctl dfimisc virt address
 180         DCD     0x01040000      ;cp0 pub busmon reg virt address
 181
 182         DCD     0x0206087c      ;cp2 aon spinlock phys address
 183         DCD     0x022b0000      ;cp2 aon phy auto en phys address
 184         DCD     0x01010000      ;cp2 ddr phy base phys address
 185         DCD     0x010001b0      ;cp2 umctl dfimisc phys address
 186         DCD     0x01040000      ;cp2 pub busmon reg phys address
 187
 188         DCD     0x0206087c      ;cp2 aon spinlock virt address
 189         DCD     0x022b0000      ;cp2 aon phy auto en virt address
 190         DCD     0x01010000      ;cp2 ddr phy base virt address
 191         DCD     0x010001b0      ;cp2 umctl dfimisc virt address
 192         DCD     0x01040000      ;cp2 pub busmon reg virt address
 193
 194         DCD     0x00000000      ;r4
 195         DCD     0x00000000      ;r5
 196         DCD     0x00000000      ;r6
 197         DCD     0x00000000      ;r7
 198         DCD     0x00000000      ;r8
 199         DCD     0x00000000      ;r9
 200         DCD     0x00000000      ;lr
 201 AP_STACK
 202         DCD     0x00000000      ;r4
 203         DCD     0x00000000      ;r5
 204         DCD     0x00000000      ;r6
 205         DCD     0x00000000      ;r7
 206         DCD     0x00000000      ;r8
 207         DCD     0x00000000      ;r9
 208         DCD     0x00000000      ;lr
 209 CP0_STACK
 210         DCD     0x00000000      ;r4
 211         DCD     0x00000000      ;r5
 212         DCD     0x00000000      ;r6
 213         DCD     0x00000000      ;r7
 214         DCD     0x00000000      ;r8
 215         DCD     0x00000000      ;r9
 216         DCD     0x00000000      ;lr
 217 CP2_STACK
 218 DEBUG_INFO
 219         DCD     0x5a5aa5a5
 220         DCD     0x5a5aa5a5
 221         DCD     0x5a5aa5a5
 222         DCD     0x5a5aa5a5
 223         DCD     0x5a5aa5a5
 224 DELAY_TIME
 225         DCD     0x00001000
 226         DCD     0x00000600
 227         DCD     0x00000500
 228         DCD     0x5a5aa5a5
 229         END