arch/arm/cpu/armv7/sc8825/efuse_drv.h

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  ************************************************
  14  * Automatically generated C config: don't edit *
  15  ************************************************
  16  */
  17
  18 #ifndef __EFUSE_H__
  19 #define __EFUSE_H__
  20
  21 #define CTL_EFUSE_BASE                                          0x49000000
  22 #define SCI_D(_addr_)                                                   ( *(volatile u32 *)(_addr_) )
  23
  24 /* registers definitions for controller CTL_EFUSE */
  25 #define REG_EFUSE_DATA_RD                                       ( CTL_EFUSE_BASE + 0x0000 )
  26 #define REG_EFUSE_DATA_WR                                       ( CTL_EFUSE_BASE + 0x0004 )
  27 #define REG_EFUSE_BLOCK_INDEX                           ( CTL_EFUSE_BASE + 0x0008 )
  28 #define REG_EFUSE_MODE_CTRL                                     ( CTL_EFUSE_BASE + 0x000C )
  29 #define REG_EFUSE_PGM_PARA                                      ( CTL_EFUSE_BASE + 0x0010 )
  30 #define REG_EFUSE_STATUS                                        ( CTL_EFUSE_BASE + 0x0014 )
  31 #define REG_EFUSE_BLK_FLAGS                                     ( CTL_EFUSE_BASE + 0x0018 )
  32 #define REG_EFUSE_BLK_CLR                                       ( CTL_EFUSE_BASE + 0x001C )
  33 #define REG_EFUSE_MAGIC_NUMBER                          ( CTL_EFUSE_BASE + 0x0020 )
  34
  35 /* bits definitions for register REG_EFUSE_BLOCK_INDEX */
  36 #define BITS_READ_INDEX(_x_)                                    ( (_x_) << 0 & ( BIT_0 | BIT_1 | BIT_2 ) )
  37 #define BITS_PGM_INDEX(_x_)                                     ( (_x_) << 16 & ( BIT_16 | BIT_17 | BIT_18 ) )
  38
  39 #define SHIFT_READ_INDEX                                                ( 0 )
  40 #define MASK_READ_INDEX                                         ( BIT_0 | BIT_1 | BIT_2 )
  41
  42 #define SHIFT_PGM_INDEX                                         ( 16 )
  43 #define MASK_PGM_INDEX                                          ( BIT_16 | BIT_17 | BIT_18 )
  44
  45 /* bits definitions for register REG_EFUSE_MODE_CTRL */
  46 #define BIT_PG_START                                                    ( BIT_0 )
  47 #define BIT_RD_START                                                    ( BIT_1 )
  48 #define BIT_STANDBY_START                                       ( BIT_2 )
  49
  50 /* bits definitions for register REG_EFUSE_PGM_PARA */
  51 #define BITS_TPGM_TIME_CNT(_x_)                         ( (_x_) & 0x1FF )
  52 #define BIT_CLK_EFS_EN                                          ( BIT_28 )
  53 #define BIT_EFUSE_VDD_ON                                                ( BIT_29 )
  54 #define BIT_PCLK_DIV_EN                                         ( BIT_30 )
  55 #define BIT_PGM_EN                                                      ( BIT_31 )
  56
  57 /* bits definitions for register REG_EFUSE_STATUS */
  58 #define BIT_PGM_BUSY                                                    ( BIT_0 )
  59 #define BIT_READ_BUSY                                           ( BIT_1 )
  60 #define BIT_STANDBY_BUSY                                                ( BIT_2 )
  61
  62 /* bits definitions for register REG_EFUSE_BLK_FLAGS */
  63 #define BIT_BLK0_PROT_FLAG                                      ( BIT_0 )
  64 #define BIT_BLK1_PROT_FLAG                                      ( BIT_1 )
  65 #define BIT_BLK2_PROT_FLAG                                      ( BIT_2 )
  66 #define BIT_BLK3_PROT_FLAG                                      ( BIT_3 )
  67 #define BIT_BLK4_PROT_FLAG                                      ( BIT_4 )
  68 #define BIT_BLK5_PROT_FLAG                                      ( BIT_5 )
  69 #define BIT_BLK6_PROT_FLAG                                      ( BIT_6 )
  70 #define BIT_BLK7_PROT_FLAG                                      ( BIT_7 )
  71
  72 /* bits definitions for register REG_EFUSE_BLK_CLR */
  73 #define BIT_BLK0_PROT_FLAG_CLR                          ( BIT_0 )
  74 #define BIT_BLK1_PROT_FLAG_CLR                          ( BIT_1 )
  75 #define BIT_BLK2_PROT_FLAG_CLR                          ( BIT_2 )
  76 #define BIT_BLK3_PROT_FLAG_CLR                          ( BIT_3 )
  77 #define BIT_BLK4_PROT_FLAG_CLR                          ( BIT_4 )
  78 #define BIT_BLK5_PROT_FLAG_CLR                          ( BIT_5 )
  79 #define BIT_BLK6_PROT_FLAG_CLR                          ( BIT_6 )
  80 #define BIT_BLK7_PROT_FLAG_CLR                          ( BIT_7 )
  81
  82 /* bits definitions for register REG_EFUSE_MAGIC_NUMBER */
  83 #define BITS_MAGIC_NUMBER(_x_)                          ( (_x_) & 0xFFFF )
  84
  85 /* vars definitions for controller CTL_EFUSE */
  86 #define PROT_LOCK                                                       ( BIT_31 )
  87
  88 #endif //__EFUSE_H__