2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <asm/arch/regs_global.h>
16 #include "efuse_drv.h"
19 static inline void delay(unsigned long loops)
21 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
22 "bne 1b":"=r" (loops):"0"(loops));
26 //static void __iomem *ctl_efuse_base = 0;
27 void sci_efuse_poweron(void)
29 SCI_D(GR_GEN0) |= GEN0_EFUSE_EN;
30 SCI_D(REG_EFUSE_PGM_PARA) |= BIT_EFUSE_VDD_ON;
31 SCI_D(REG_EFUSE_PGM_PARA) |= BIT_CLK_EFS_EN;
34 void sci_efuse_poweroff(void)
36 SCI_D(REG_EFUSE_PGM_PARA) &= ~BIT_CLK_EFS_EN;
37 SCI_D(REG_EFUSE_PGM_PARA) &= ~BIT_EFUSE_VDD_ON;
38 SCI_D(GR_GEN0) &= ~GEN0_EFUSE_EN;
41 int sci_efuse_read(unsigned blk)
45 if (blk > (MASK_READ_INDEX >> SHIFT_READ_INDEX))
50 SCI_D(REG_EFUSE_BLOCK_INDEX) = BITS_READ_INDEX(blk);
51 SCI_D(REG_EFUSE_MODE_CTRL) |= BIT_RD_START;
55 busy = SCI_D(REG_EFUSE_STATUS) & BIT_READ_BUSY;
58 return SCI_D(REG_EFUSE_DATA_RD);
61 int sci_efuse_is_locked(unsigned blk)
66 int sci_efuse_lock(unsigned blk)
72 int sci_efuse_program(unsigned blk, int data)
76 if (blk > (MASK_PGM_INDEX >> SHIFT_PGM_INDEX))
81 SCI_D(REG_EFUSE_BLOCK_INDEX) = BITS_PGM_INDEX(blk);
82 SCI_D(REG_EFUSE_DATA_WR) = data;
83 SCI_D(REG_EFUSE_MODE_CTRL) |= BIT_PG_START;
87 busy = SCI_D(REG_EFUSE_STATUS) & BIT_PGM_BUSY;
94 int sci_efuse_raw_write(unsigned blk, int data, u32 magic)
98 SCI_D(REG_EFUSE_PGM_PARA) |= BIT_PGM_EN;
99 SCI_D(REG_EFUSE_MAGIC_NUMBER) = BITS_MAGIC_NUMBER(magic);
100 ADI_Analogdie_reg_write(0x420006D4, 0xC686);
101 ADI_Analogdie_reg_write(0x420006D8, 0x01);
105 retVal = sci_efuse_program(blk, data);
106 SCI_D(REG_EFUSE_PGM_PARA) &= ~BIT_PGM_EN;
111 int sci_efuse_program(unsigned blk, int data)
116 int sci_efuse_raw_write(unsigned blk, int data, u32 magic)
122 static int overclocking_flag = 0;
123 static int overclocking_data = 0;;
125 int sci_efuse_overclocking_get()
129 if (overclocking_flag == 0)
132 data = sci_efuse_read(1);
133 sci_efuse_poweroff();
135 if ((data & BIT_29) != 0) {
136 overclocking_data = 1;
139 overclocking_flag = 1;
142 return overclocking_data;
147 #define CAL_DATA_BLK 7
148 #define BASE_ADC_P0 785 //3.6V
149 #define BASE_ADC_P1 917 //4.2V
152 #define ADC_DATA_OFFSET 128
153 int sci_efuse_calibration_get(unsigned int * p_cal_data)
156 unsigned int cal_temp;
157 unsigned short adc_temp;
160 data = sci_efuse_read(CAL_DATA_BLK);
161 sci_efuse_poweroff();
165 // data = (173 |(171 << 8));
166 printf("sci_efuse_calibration data:%d\n",data);
167 if((!data)||(p_cal_data == NULL))
172 adc_temp = ((data>>8) & 0x00FF) + BASE_ADC_P0 - ADC_DATA_OFFSET;
173 p_cal_data[1] = (VOL_P0)|(adc_temp << 16);
176 adc_temp = (data & 0x00FF) + BASE_ADC_P1 - ADC_DATA_OFFSET;
177 p_cal_data[0] = (VOL_P1)|(adc_temp << 16);