5 #ifdef PLATFORM_SC8800G
6 #define REMAP 0x20900218
7 #define SVC_STACK_TEMP 0x40008000
8 #define GEN2_ADDR 0x8b00002c
9 #define ON_CHIP_RAM_EN 0xF
12 #ifdef PLATFORM_SC8800G
13 #define BIGEND_PROT_REG 0x20900290
14 #define AHB_CTRL5_REG 0x20900230
24 #ifdef CHIP_ENDIAN_BIG
31 BIC r0,r0,#1 /*disable MMU*/
33 BIC r0,r0,r1 /*disable cache*/
39 /*Set Endian Regs of SC8800G*/
40 #if defined(CHIP_ENDIAN_BIG) && defined(PLATFORM_SC8800G)
41 LDR R0, =BIGEND_PROT_REG
46 LDR R2, =AHB_CTRL5_REG
55 /*set stack limit to 0*/
58 #if defined(PLATFORM_SC8800H) || defined(PLATFORM_SC8800G)
60 /*Enable on chip ram for ARM*/
62 LDR R1, =ON_CHIP_RAM_EN
69 LDR sp, =SVC_STACK_TEMP
75 The sp here must be in the reserved region
81 /*end of function cpu_spec*/