1 /******************************************************************************
2 ** File Name: chip_phy_v3.c *
3 ** Author: Richard Yang *
5 ** Copyright: 2002 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: This file defines the basic information on chip. *
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION *
13 ** 08/14/2002 Richard.Yang Create. *
14 ** 09/16/2003 Xueliang.Wang Modify CR4013 *
15 ** 08/23/2004 JImmy.Jia Modify for SC6600D *
16 ******************************************************************************/
18 /**---------------------------------------------------------------------------*
20 **---------------------------------------------------------------------------*/
22 #include "adi_hal_internal.h"
23 #include "wdg_drvapi.h"
24 #include "mocor_boot_mode.h"
26 /**---------------------------------------------------------------------------*
28 **---------------------------------------------------------------------------*/
34 /**---------------------------------------------------------------------------*
36 **---------------------------------------------------------------------------*/
37 #define HW_RST_MASK 0x1F
39 #define HWRST_ADDR (DMA_REG_BASE + 0x400 + 31 * 0x20 + 8) //src addr reg in chn 31
41 #define ENABLE_DMA_MODULE \
43 if(!(CHIP_REG_GET(AHB_CTL0) & BIT_6)) \
45 CHIP_REG_OR(AHB_CTL0, BIT_6); \
49 /**---------------------------------------------------------------------------*
51 **---------------------------------------------------------------------------*/
53 /**---------------------------------------------------------------------------*
55 **---------------------------------------------------------------------------*/
57 /**---------------------------------------------------------------------------*
58 ** Function Definitions *
59 **---------------------------------------------------------------------------*/
60 /*****************************************************************************/
61 // Description : This function is used to reset MCU.
62 // Global resource dependence :
63 // Author : Xueliang.Wang
65 /*****************************************************************************/
66 void CHIP_ResetMCU (void) //reset interrupt disable??
68 // This loop is very important to let the reset process work well on V3 board
71 ANA_REG_OR (ANA_AGEN, (AGEN_WDG_EN | AGEN_RTC_WDG_EN));
76 volatile uint32 tick1 = SCI_GetTickCount();
77 volatile uint32 tick2 = SCI_GetTickCount();
78 while ( (tick2 - tick1) < 500)
80 tick2 = SCI_GetTickCount();
85 /*****************************************************************************/
86 // Description: Returns the HW_RST register address.
88 // Note : Because there is no register which can restore information
89 // when watchdog resets the system, so we choose IRAM.
90 /*****************************************************************************/
91 LOCAL uint32 CHIP_PHY_GetHwRstAddr (void)
93 // Returns a DWORD of IRAM shared with DCAM
101 /*****************************************************************************/
102 // Description: Returns the reset mode register address.
105 /*****************************************************************************/
106 LOCAL uint32 CHIP_PHY_GetRstModeAddr (void)
108 return GR_ARM_BOOT_ADDR;
111 /*****************************************************************************/
112 // Description: Gets the register in analog die to judge the reset mode.
114 // Note: !It is called before __main now, so it can not call the adi
115 // interface because it contains SCI_DisableIRQ inside, below
116 // writes the adi read interface individually. Because the la-
117 // ckless of SCI_DisableIRQ, so this function must be called
118 // before system interrupt is turnned on!
119 /*****************************************************************************/
120 LOCAL uint32 CHIP_PHY_GetANAReg (void)
125 * (volatile uint32 *) ADI_ARM_RD_CMD = ANA_HWRST_STATUS;
127 // Wait read operation complete, RD_data[31] will be cleared after the read
128 // operation complete
131 adi_rd_data = * (volatile uint32 *) ADI_RD_DATA;
133 while (adi_rd_data & BIT_31);
135 return ((adi_rd_data & 0x0000FFFF));
138 /*****************************************************************************/
139 // Description: This fuction returns the HW_RST value written before reset.
142 /*****************************************************************************/
143 LOCAL uint32 CHIP_PHY_GetHWFlag (void)
145 // Switch IRAM from DCAM to ARM
146 REG32 (AHB_CTL1) |= BIT_0;
148 return CHIP_REG_GET (CHIP_PHY_GetHwRstAddr ());
151 /*****************************************************************************/
152 // Description: PHY layer realization of BOOT_SetRstMode.
154 // Note: The valid bit filed is from bit15 to bit0
155 /*****************************************************************************/
156 PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
158 CHIP_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
159 CHIP_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
162 /*****************************************************************************/
163 // Description: This fuction returns the reset mode value.
166 /*****************************************************************************/
167 PUBLIC uint32 CHIP_PHY_GetRstMode (void)
169 return (CHIP_REG_GET (CHIP_PHY_GetRstModeAddr ()) & 0xFFFF);
172 /*****************************************************************************/
173 // Description: PHY layer realization of BOOT_ResetHWFlag. It resets the HW
174 // reset register after system initialization.
176 // Note: The valid bit filed of analog register is from bit11 to bit0.
177 // | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
178 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
180 // The valid bit filed of HW_RST is from bit11 to bit0.
181 /*****************************************************************************/
182 PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
185 // Reset the analog die register
186 ANA_REG_AND (ANA_HWRST_STATUS, (~0xF));
187 ANA_REG_OR (ANA_HWRST_STATUS, (val & 0xF));
190 CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
191 CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
195 ANA_REG_AND (ANA_HWRST_STATUS, (~0xF));
196 ANA_REG_OR (ANA_HWRST_STATUS, (val & 0xF));
200 CHIP_REG_AND(CHIP_PHY_GetHwRstAddr(), (~HW_RST_MASK));
201 CHIP_REG_OR(CHIP_PHY_GetHwRstAddr(), (val & HW_RST_MASK));
205 /*****************************************************************************/
206 // Description: PHY layer realization of BOOT_SetWDGHWFlag. It Writes flag
207 // to the register which would not be reset by watchdog reset.
209 // Note: The valid bit filed is from bit15 to bit0
210 /*****************************************************************************/
211 PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
213 if(TYPE_RESET == type)
216 // Switch IRAM from DCAM to ARM
217 REG32 (AHB_CTL1) |= BIT_0;
219 CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
220 CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
224 CHIP_REG_AND(CHIP_PHY_GetHwRstAddr(), (~HW_RST_MASK));
225 CHIP_REG_OR(CHIP_PHY_GetHwRstAddr(), (val & HW_RST_MASK));
233 /*****************************************************************************/
234 // Description: PHY layer realization of __BOOT_IRAM_EN.
236 // Note: Do nothing. There are 32KB internal ram dedicated for ARM.
237 /*****************************************************************************/
238 PUBLIC void CHIP_PHY_BootIramEn ()
242 /*****************************************************************************/
243 // Description : This function returns whether the watchdog reset is caused
244 // by software reset or system halted.
246 // Note : The valid bit filed is from bit15 to bit0
247 /*****************************************************************************/
248 PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag)
250 // Copy the value of HW_RST register to the register specific to reset mode
251 CHIP_REG_SET (CHIP_PHY_GetRstModeAddr (),
252 (CHIP_PHY_GetHWFlag () & 0xFFFF));
254 if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF))
264 /*****************************************************************************/
265 // Description : This function returns whether the reset is caused by power
268 // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
269 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
270 /*****************************************************************************/
271 PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp()
273 if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0)
283 /*****************************************************************************/
284 // Description : This function returns whether the reset is caused by watch-
287 // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
288 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
289 /*****************************************************************************/
290 PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog()
292 if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0)
302 /**---------------------------------------------------------------------------*
304 **---------------------------------------------------------------------------*/