uprobe/arch/arm/swap-asm/trampoline_thumb.S

   1                 .thumb
   2
   3                 .global gen_insn_execbuf_thumb
   4 gen_insn_execbuf_thumb:
   5                 nop
   6                 nop
   7                 nop                     // original instruction
   8                 nop                     // original instruction
   9                 nop
  10                 nop
  11                 nop
  12                 sub     sp, sp, #8
  13                 str     r0, [sp, #0]
  14                 ldr     r0, [pc, #12]
  15                 str     r0, [sp, #4]
  16                 nop
  17                 pop     {r0, pc}        // ssbreak
  18                 nop                     // retbreak
  19                 nop
  20                 nop
  21                 nop                     // stored PC-4(next insn addr) hi
  22                 nop                     // stored PC-4(next insn addr) lo
  23
  24                 nop
  25
  26                 .global pc_dep_insn_execbuf_thumb
  27                 .align 4
  28 pc_dep_insn_execbuf_thumb:
  29                 push    {r6, r7}
  30                 ldr     r6, i1
  31                 mov     r7, sp
  32                 mov     sp, r6
  33                 nop                     // PC -> SP
  34                 nop                     // PC -> SP
  35                 mov     sp, r7
  36                 pop     {r6, r7}
  37                 push    {r0, r1}
  38                 ldr     r0, i2
  39                 nop
  40                 str     r0, [sp, #4]
  41                 pop     {r0, pc}        // ssbreak
  42                 nop                     // retbreak
  43 i1:             nop                     // stored PC hi
  44                 nop                     // stored PC lo
  45 i2:             nop                     // stored PC-4(next insn addr) hi
  46                 nop                     // stored PC-4(next insn addr) lo
  47
  48                 .global b_r_insn_execbuf_thumb
  49                 .align 4
  50 b_r_insn_execbuf_thumb:
  51                 nop
  52                 nop
  53                 nop
  54                 nop
  55                 nop                     // bx,blx (Rm)
  56                 nop                     //
  57                 push {r0,r1}
  58                 ldr r0, np
  59                 nop
  60                 str r0, [sp, #4]
  61                 pop {r0,pc}
  62                 nop
  63                 nop                     // ssbreak
  64                 nop                     // retbreak
  65                 nop
  66                 nop
  67 np:             nop                     // stored PC-4(next insn addr) hi
  68                 nop                     // stored PC-4(next insn addr) lo
  69
  70                 .global b_off_insn_execbuf_thumb
  71                 .align 4
  72 b_off_insn_execbuf_thumb:
  73                 push {r0,r1}
  74                 ldr r0, bd
  75                 str r0, [sp, #4]
  76                 pop {r0, pc}
  77                 nop
  78                 nop
  79                 push {r0,r1}
  80                 ldr r0, np2
  81                 nop
  82                 str r0, [sp, #4]
  83                 pop {r0,pc}
  84                 nop
  85                 nop                     // ssbreak
  86                 nop                     // retbreak
  87 bd:             nop                     // branch displacement hi
  88                 nop                     // branch displacement lo
  89 np2:            nop                     // stored PC-4(next insn addr) hi
  90                 nop                     // stored PC-4(next insn addr) lo
  91
  92                 .global blx_off_insn_execbuf_thumb
  93                 .align 4
  94 blx_off_insn_execbuf_thumb:
  95                 push {r0}
  96                 ldr r0, bd3
  97                 mov lr, r0
  98                 pop {r0}
  99                 blx lr
 100                 nop
 101                 push {r0,r1}
 102                 ldr r0, np3
 103                 nop
 104                 str r0, [sp, #4]
 105                 pop {r0,pc}
 106                 nop
 107                 nop                     // ssbreak
 108                 nop                     // retbreak
 109 bd3:            nop                     // branch displacement hi
 110                 nop                     // branch displacement lo
 111 np3:            nop                     // stored PC-4(next insn addr) hi
 112                 nop                     // stored PC-4(next insn addr) lo
 113
 114                 .global b_cond_insn_execbuf_thumb
 115                 .align 4
 116 b_cond_insn_execbuf_thumb:
 117                 beq condway
 118                 push {r0,r1}
 119                 ldr r0, np4
 120                 nop
 121                 str r0, [sp, #4]
 122                 pop {r0,pc}
 123 condway:        push {r0,r1}
 124                 ldr r0, bd4
 125                 str r0, [sp, #4]
 126                 pop {r0,pc}
 127                 nop
 128                 nop
 129                 nop                     // ssbreak
 130                 nop                     // retbreak
 131 bd4:            nop                     // branch displacement hi
 132                 nop                     // branch displacement lo
 133 np4:            nop                     // stored PC-4(next insn addr) hi
 134                 nop                     // stored PC-4(next insn addr) lo
 135
 136                 .global cbz_insn_execbuf_thumb
 137                 .align 4
 138 cbz_insn_execbuf_thumb:
 139                 nop                     // cbz
 140                 push {r0,r1}
 141                 ldr r0, np5
 142                 nop
 143                 str r0, [sp, #4]
 144                 pop {r0,pc}
 145                 push {r0,r1}
 146                 ldr r0, bd5
 147                 str r0, [sp, #4]
 148                 pop {r0,pc}
 149                 nop
 150                 nop
 151                 nop                     // ssbreak
 152                 nop                     // retbreak
 153 bd5:            nop                     // branch displacement hi
 154                 nop                     // branch displacement lo
 155 np5:            nop                     // stored PC-4(next insn addr) hi
 156                 nop                     // stored PC-4(next insn addr) lo