drivers/video/samsung/s5p-dsim.c

   1 /* linux/drivers/video/samsung/s5p-dsim.c
   2  *
   3  * Samsung MIPI-DSIM driver.
   4  *
   5  * InKi Dae, <inki.dae@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Modified by Samsung Electronics (UK) on May 2010
  12  *
  13 */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/clk.h>
  19 #include <linux/mutex.h>
  20 #include <linux/wait.h>
  21 #include <linux/fs.h>
  22 #include <linux/mm.h>
  23 #include <linux/fb.h>
  24 #include <linux/ctype.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/memory.h>
  29 #include <linux/delay.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/kthread.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/gpio.h>
  35 #include <plat/clock.h>
  36 #include <plat/regs-dsim.h>
  37 #include <plat/gpio-cfg.h>
  38 #include <mach/map.h>
  39 #include <mach/dsim.h>
  40 #include <mach/mipi_ddi.h>
  41 #include <mach/irqs.h>
  42
  43 #include "s5p-dsim.h"
  44 #include "s5p_dsim_lowlevel.h"
  45 #include "s3cfb.h"
  46
  47 #ifdef CONFIG_HAS_WAKELOCK
  48 #include <linux/wakelock.h>
  49 #include <linux/earlysuspend.h>
  50 #include <linux/suspend.h>
  51 #endif
  52
  53 struct mipi_lcd_info {
  54         struct list_head        list;
  55         struct mipi_lcd_driver  *mipi_drv;
  56 };
  57
  58 static DEFINE_MUTEX(dsim_rd_wr_mutex);
  59 static DECLARE_COMPLETION(dsim_rd_comp);
  60 static DECLARE_COMPLETION(dsim_wr_comp);
  61
  62 #define MIPI_RESP_ERR                           0x02
  63 #define MIPI_RESP_EOTP                  0x08
  64 #define MIPI_RESP_GENERIC_RD_1          0x11
  65 #define MIPI_RESP_GENERIC_RD_2          0x12
  66 #define MIPI_RESP_GENERIC_RD_LONG               0x1A
  67 #define MIPI_RESP_DCS_RD_LONG           0x1C
  68 #define MIPI_RESP_DCS_RD_1                      0x21
  69 #define MIPI_RESP_DCS_RD_2                      0x22
  70
  71 #define MIPI_CMD_GENERIC_WR_0           0x03
  72 #define MIPI_CMD_GENERIC_WR_1           0x13
  73 #define MIPI_CMD_GENERIC_WR_2           0x23
  74 #define MIPI_CMD_GENERIC_WR_LONG                0x29
  75
  76 #define MIPI_CMD_DSI_WR_0                       0x05
  77 #define MIPI_CMD_DSI_WR_1                       0x15
  78 #define MIPI_CMD_DSI_WR_LONG                    0x39
  79
  80 #define MIPI_CMD_GENERIC_RD_0           0x04
  81 #define MIPI_CMD_GENERIC_RD_1           0x14
  82 #define MIPI_CMD_GENERIC_RD_2           0x24
  83
  84 #define MIPI_CMD_DSI_RD_0                       0x06
  85
  86 #define MIPI_CMD_DSI_SET_PKT_SZ         0x37
  87
  88 #define DSIM_TIMEOUT                            msecs_to_jiffies(250)
  89 #define DSIM_RX_FIFO_READ_DONE          0x30800002
  90 #define DSIM_MAX_RX_FIFO                        20
  91
  92 #define S5P_DSIM_INT_SFR_FIFO_EMPTY             29
  93 #define S5P_DSIM_INT_BTA                        25
  94 #define S5P_DSIM_INT_MSK_FRAME_DONE             24
  95 #define S5P_DSIM_INT_RX_TIMEOUT         21
  96 #define S5P_DSIM_INT_BTA_TIMEOUT                20
  97 #define S5P_DSIM_INT_RX_DONE                    18
  98 #define S5P_DSIM_INT_RX_TE                      17
  99 #define S5P_DSIM_INT_RX_ACK                     16
 100 #define S5P_DSIM_INT_RX_ECC_ERR         15
 101 #define S5P_DSIM_IMT_RX_CRC_ERR         14
 102
 103 static LIST_HEAD(lcd_info_list);
 104 static DEFINE_MUTEX(mipi_lock);
 105 static struct dsim_global *g_dsim;
 106
 107 static struct s5p_platform_dsim *to_dsim_plat(struct device *dev)
 108 {
 109         struct platform_device *pdev = to_platform_device(dev);
 110
 111         return (struct s5p_platform_dsim *)pdev->dev.platform_data;
 112 }
 113
 114 static void s5p_dsim_frame_done_interrupt_enable(struct dsim_global *dsim, u8 enable)
 115 {
 116         u32 intmsk;
 117         u8 state = !enable;
 118
 119         if (!dsim->mipi_ddi_pd->resume_complete)
 120                 return;
 121
 122         intmsk = readl(dsim->reg_base + S5P_DSIM_INTMSK);
 123
 124         if (state == 0) /* enable Frame Done interrupts */
 125                 intmsk &= ~(0x01 << S5P_DSIM_INT_MSK_FRAME_DONE);
 126         else    /* disable Frame Done interrupts */
 127                 intmsk |= (0x01 << S5P_DSIM_INT_MSK_FRAME_DONE);
 128
 129         writel(intmsk, dsim->reg_base + S5P_DSIM_INTMSK);
 130 }
 131
 132 void set_dsim_lcd_enabled(u8 enable)
 133 {
 134         struct dsim_global *dsim = g_dsim;
 135
 136         dsim->dsim_lcd_info->lcd_enabled = enable;
 137         if (dsim->dsim_info->hs_toggle)
 138                 s5p_dsim_frame_done_interrupt_enable(dsim, enable);
 139 }
 140
 141 void set_dsim_hs_clk_toggle_count(u8 count)
 142 {
 143         struct dsim_global *dsim = g_dsim;
 144
 145         dsim->dsim_toggle_per_frame_count = count;
 146         if (dsim->dsim_lcd_info->lcd_enabled) {
 147                 if (dsim->dsim_info->hs_toggle) {
 148                         s5p_dsim_frame_done_interrupt_enable(dsim, 1);
 149                         schedule_delayed_work(&dsim->check_hs_toggle_work, msecs_to_jiffies(60000));
 150                 } else
 151                         s5p_dsim_frame_done_interrupt_enable(dsim, count ? 1 : 0);
 152         }
 153 }
 154
 155 static void dsim_work_q_handler(struct work_struct *work)
 156 {
 157         struct dsim_global *dsim =
 158                 container_of(work, struct dsim_global, dsim_work.work);
 159
 160         s5p_dsim_frame_done_interrupt_enable(dsim, 1);
 161 }
 162
 163 static void dsim_check_hs_toggle_work_q_handler(struct work_struct *work)
 164 {
 165         struct dsim_global *dsim =
 166                 container_of(work, struct dsim_global, check_hs_toggle_work.work);
 167
 168         if (dsim->dsim_info->hs_toggle) {
 169                 dev_info(dsim->dev, "check_hs_toggle\n");
 170                 schedule_delayed_work(&dsim->check_hs_toggle_work, msecs_to_jiffies(60000));
 171         }
 172 }
 173
 174 unsigned char s5p_dsim_wr_data(void *ptr,
 175         unsigned int data_id, unsigned int data0, unsigned int data1)
 176 {
 177         struct dsim_global *dsim = ptr;
 178         unsigned int dsim_base = dsim->reg_base;
 179
 180         if (dsim->state == DSIM_STATE_ULPS) {
 181                 dev_err(dsim->dev, "DSIM state: ULPS\n");
 182                 return DSIM_FALSE;
 183         }
 184
 185         if (dsim->mipi_ddi_pd->resume_complete == 0) {
 186                 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
 187                 return DSIM_FALSE;
 188         }
 189
 190         mutex_lock(&dsim_rd_wr_mutex);
 191
 192         switch (data_id) {
 193         /* short packet types of packet types for command. */
 194         case GEN_SHORT_WR_NO_PARA:
 195         case GEN_SHORT_WR_1_PARA:
 196         case GEN_SHORT_WR_2_PARA:
 197         case DCS_WR_NO_PARA:
 198         case DCS_WR_1_PARA:
 199         case SET_MAX_RTN_PKT_SIZE:
 200                 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
 201                         (unsigned char) data0, (unsigned char) data1);
 202                 mutex_unlock(&dsim_rd_wr_mutex);
 203                 return DSIM_TRUE; /* response should be implemented */
 204         /* general command */
 205         case CMD_OFF:
 206         case CMD_ON:
 207         case SHUT_DOWN:
 208         case TURN_ON:
 209                 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
 210                         (unsigned char) data0, (unsigned char) data1);
 211                 mutex_unlock(&dsim_rd_wr_mutex);
 212                 return DSIM_TRUE; /* response should be implemented. */
 213         /* packet types for video data */
 214         case VSYNC_START:
 215         case VSYNC_END:
 216         case HSYNC_START:
 217         case HSYNC_END:
 218         case EOT_PKT:
 219                 mutex_unlock(&dsim_rd_wr_mutex);
 220                 return DSIM_TRUE;
 221
 222         /* short and response packet types for command */
 223         case GEN_RD_1_PARA:
 224         case GEN_RD_2_PARA:
 225         case GEN_RD_NO_PARA:
 226         case DCS_RD_NO_PARA:
 227                 s5p_dsim_clear_interrupt(dsim_base, 0xffffffff);
 228                 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
 229                         (unsigned char) data0, (unsigned char) data1);
 230                 mutex_unlock(&dsim_rd_wr_mutex);
 231                 return DSIM_FALSE; /* response should be implemented. */
 232
 233         /* long packet type and null packet */
 234         case NULL_PKT:
 235         case BLANKING_PKT:
 236                 mutex_unlock(&dsim_rd_wr_mutex);
 237                 return DSIM_TRUE;
 238         case GEN_LONG_WR:
 239         case DCS_LONG_WR:
 240         {
 241                 u32 uCnt = 0;
 242                 u32* pWordPtr = (u32 *)data0;
 243                 INIT_COMPLETION(dsim_wr_comp);
 244
 245                 do {
 246                         s5p_dsim_wr_tx_data(dsim_base, pWordPtr[uCnt]);
 247                 } while (((data1-1) / 4) > uCnt++);
 248
 249                 /* put data into header fifo */
 250                 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
 251                         (unsigned char) (((unsigned short) data1) & 0xff),
 252                         (unsigned char) ((((unsigned short) data1) & 0xff00) >> 8));
 253
 254                 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp, DSIM_TIMEOUT)) {
 255                         dev_err(dsim->dev, "[DSIM:ERROR] %s Timeout\n", __func__);
 256                         mutex_unlock(&dsim_rd_wr_mutex);
 257                         return DSIM_FALSE;
 258                 }
 259                 mutex_unlock(&dsim_rd_wr_mutex);
 260                 return DSIM_TRUE;
 261         }
 262         /* packet typo for video data */
 263         case RGB565_PACKED:
 264         case RGB666_PACKED:
 265         case RGB666_LOOSLY:
 266         case RGB888_PACKED:
 267                 mutex_unlock(&dsim_rd_wr_mutex);
 268                 return DSIM_TRUE; /* response should be implemented. */
 269         default:
 270                 dev_warn(dsim->dev, "data id %x is not supported current DSI spec\n", data_id);
 271                 mutex_unlock(&dsim_rd_wr_mutex);
 272                 return DSIM_FALSE;
 273         }
 274 }
 275
 276 int s5p_dsim_rd_data(void *ptr, u8 addr, u16 count, u8 *buf)
 277 {
 278         u32 i, temp;
 279         u8 response = 0;
 280         u16 rxsize;
 281         u32 txhd;
 282         u32 rxhd;
 283         int j;
 284         struct dsim_global *dsim = ptr;
 285         unsigned int reg_base = dsim->reg_base;
 286
 287         if (dsim->mipi_ddi_pd->resume_complete == 0) {
 288                 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
 289                 return DSIM_FALSE;
 290         }
 291
 292         mutex_lock(&dsim_rd_wr_mutex);
 293         INIT_COMPLETION(dsim_rd_comp);
 294
 295         switch (count) {
 296         case 1:
 297                 response = MIPI_RESP_GENERIC_RD_1;
 298                 break;
 299         case 2:
 300                 response = MIPI_RESP_GENERIC_RD_2;
 301                 break;
 302         default:
 303                 response = MIPI_RESP_GENERIC_RD_LONG;
 304                 break;
 305         }
 306
 307         /* set return packet size */
 308         txhd = MIPI_CMD_DSI_SET_PKT_SZ | count << 8;
 309
 310         writel(txhd, reg_base + S5P_DSIM_PKTHDR);
 311
 312         /* set address to read */
 313         txhd = MIPI_CMD_GENERIC_RD_1 | addr << 8;
 314
 315         writel(txhd, reg_base + S5P_DSIM_PKTHDR);
 316
 317         if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp, DSIM_TIMEOUT)) {
 318                 dev_err(dsim->dev, "ERROR:%s timout\n", __func__);
 319                 mutex_unlock(&dsim_rd_wr_mutex);
 320                 return 0;
 321         }
 322
 323         rxhd = readl(reg_base + S5P_DSIM_RXFIFO);
 324         dev_info(dsim->dev, "rxhd : %x\n", rxhd);
 325         if ((u8)(rxhd & 0xff) != response) {
 326                 dev_err(dsim->dev, "[DSIM:ERROR]:%s wrong response rxhd : %x, response:%x\n"
 327                     , __func__, rxhd, response);
 328                 goto clear_rx_fifo;
 329         }
 330         /* for short packet */
 331         if (count <= 2) {
 332                 for (i = 0; i < count; i++)
 333                         buf[i] = (rxhd >> (8+(i*8))) & 0xff;
 334                 rxsize = count;
 335         } else {
 336                 /* for long packet */
 337                 rxsize = (u16)((rxhd & 0x00ffff00) >> 8);
 338                 dev_info(dsim->dev, "rcv size : %d\n", rxsize);
 339                 if (rxsize != count) {
 340                         dev_err(dsim->dev, "[DSIM:ERROR]:%s received data size mismatch received : %d, requested : %d\n",
 341                                 __func__, rxsize, count);
 342                         goto clear_rx_fifo;
 343                 }
 344
 345                 for (i = 0; i < rxsize>>2; i++) {
 346                         temp = readl(reg_base + S5P_DSIM_RXFIFO);
 347                         dev_info(dsim->dev, "pkt : %08x\n", temp);
 348                         for (j = 0; j < 4; j++) {
 349                                 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
 350                                 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
 351                         }
 352                 }
 353                 if (rxsize % 4) {
 354                         temp = readl(reg_base + S5P_DSIM_RXFIFO);
 355                         dev_info(dsim->dev, "pkt-l : %08x\n", temp);
 356                         for (j = 0; j < rxsize%4; j++) {
 357                                 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
 358                                 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
 359                         }
 360                 }
 361         }
 362
 363         temp = readl(reg_base + S5P_DSIM_RXFIFO);
 364
 365         if (temp != DSIM_RX_FIFO_READ_DONE) {
 366                 dev_warn(dsim->dev, "[DSIM:WARN]:%s Can't found RX FIFO READ DONE FLAG : %x\n", __func__, temp);
 367                 goto clear_rx_fifo;
 368         }
 369
 370         mutex_unlock(&dsim_rd_wr_mutex);
 371         return rxsize;
 372
 373 clear_rx_fifo:
 374         i = 0;
 375         while (1) {
 376                 temp = readl(reg_base+S5P_DSIM_RXFIFO);
 377                 if ((temp == DSIM_RX_FIFO_READ_DONE) || (i > DSIM_MAX_RX_FIFO))
 378                         break;
 379                 dev_info(dsim->dev, "[DSIM:INFO] : %s clear rx fifo : %08x\n", __func__, temp);
 380                 i++;
 381         }
 382         dev_info(dsim->dev, "[DSIM:INFO] : %s done count : %d, temp : %08x\n", __func__, i, temp);
 383
 384         mutex_unlock(&dsim_rd_wr_mutex);
 385         return 0;
 386
 387 }
 388
 389 int s5p_dsim_dcs_rd_data(void *ptr, u8 addr, u16 count, u8 *buf)
 390 {
 391         u32 i, temp;
 392         u8 response = 0;
 393         u16 rxsize;
 394         u32 txhd;
 395         u32 rxhd;
 396         int j;
 397         struct dsim_global *dsim = ptr;
 398         unsigned int reg_base = dsim->reg_base;
 399
 400         if (dsim->mipi_ddi_pd->resume_complete == 0) {
 401                 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
 402                 return DSIM_FALSE;
 403         }
 404
 405         mutex_lock(&dsim_rd_wr_mutex);
 406         INIT_COMPLETION(dsim_rd_comp);
 407
 408         switch (count) {
 409         case 1:
 410                 response = MIPI_RESP_DCS_RD_1;
 411                 break;
 412         case 2:
 413                 response = MIPI_RESP_DCS_RD_2;
 414                 break;
 415         default:
 416                 response = MIPI_RESP_DCS_RD_LONG;
 417                 break;
 418         }
 419
 420         /* set return packet size */
 421         txhd = MIPI_CMD_DSI_SET_PKT_SZ | count << 8;
 422
 423         writel(txhd, reg_base + S5P_DSIM_PKTHDR);
 424
 425         /* set address to read */
 426         txhd = MIPI_CMD_DSI_RD_0 | addr << 8;
 427
 428         writel(txhd, reg_base + S5P_DSIM_PKTHDR);
 429
 430         if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp, DSIM_TIMEOUT)) {
 431                 dev_err(dsim->dev, "ERROR:%s timout\n", __func__);
 432                 mutex_unlock(&dsim_rd_wr_mutex);
 433                 return 0;
 434         }
 435
 436         rxhd = readl(reg_base + S5P_DSIM_RXFIFO);
 437         dev_info(dsim->dev, "rxhd : %x\n", rxhd);
 438         if ((u8)(rxhd & 0xff) != response) {
 439                 dev_err(dsim->dev, "[DSIM:ERROR]:%s wrong response rxhd : %x, response:%x\n"
 440                     , __func__, rxhd, response);
 441                 goto error_read;
 442         }
 443         /* for short packet */
 444         if (count <= 2) {
 445                 for (i = 0; i < count; i++)
 446                         buf[i] = (rxhd >> (8+(i*8))) & 0xff;
 447                 rxsize = count;
 448         } else {
 449                 /* for long packet */
 450                 rxsize = (u16)((rxhd & 0x00ffff00) >> 8);
 451                 dev_info(dsim->dev, "rcv size : %d\n", rxsize);
 452                 if (rxsize != count) {
 453                         dev_err(dsim->dev, "[DSIM:ERROR]:%s received data size mismatch received : %d, requested : %d\n",
 454                                 __func__, rxsize, count);
 455                         goto error_read;
 456                 }
 457
 458                 for (i = 0; i < rxsize>>2; i++) {
 459                         temp = readl(reg_base + S5P_DSIM_RXFIFO);
 460                         dev_info(dsim->dev, "pkt : %08x\n", temp);
 461                         for (j = 0; j < 4; j++) {
 462                                 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
 463                                 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
 464                         }
 465                 }
 466                 if (rxsize % 4) {
 467                         temp = readl(reg_base + S5P_DSIM_RXFIFO);
 468                         dev_info(dsim->dev, "pkt-l : %08x\n", temp);
 469                         for (j = 0; j < rxsize%4; j++) {
 470                                 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
 471                                 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
 472                         }
 473                 }
 474         }
 475
 476         mutex_unlock(&dsim_rd_wr_mutex);
 477         return rxsize;
 478
 479 error_read:
 480         mutex_unlock(&dsim_rd_wr_mutex);
 481         return 0;
 482
 483 }
 484
 485 static irqreturn_t s5p_dsim_isr(int irq, void *dev_id)
 486 {
 487         int i;
 488         unsigned int intsrc = 0;
 489         unsigned int intmsk = 0;
 490         struct dsim_global *dsim = NULL;
 491
 492         dsim = (struct dsim_global *)dev_id;
 493         if (!dsim) {
 494                 printk(KERN_ERR "%s:error:wrong parameter\n", __func__);
 495                 return IRQ_HANDLED;
 496         }
 497
 498         intsrc = readl(dsim->reg_base + S5P_DSIM_INTSRC);
 499         intmsk = readl(dsim->reg_base + S5P_DSIM_INTMSK);
 500
 501         intmsk = ~(intmsk) & intsrc;
 502
 503         for (i = 0; i < 32; i++) {
 504                 if (intmsk & (0x01<<i)) {
 505                         switch (i) {
 506                         case S5P_DSIM_INT_BTA:
 507                                 /* printk("S5P_DSIM_INT_BTA\n"); */
 508                                 break;
 509                         case S5P_DSIM_INT_RX_TIMEOUT:
 510                                 /* printk("S5P_DSIM_INT_RX_TIMEOUT\n"); */
 511                                 break;
 512                         case S5P_DSIM_INT_BTA_TIMEOUT:
 513                                 /* printk("S5P_DSIM_INT_BTA_TIMEOUT\n"); */
 514                                 break;
 515                         case S5P_DSIM_INT_RX_DONE:
 516                                 complete_all(&dsim_rd_comp);
 517                                 /* printk("S5P_DSIM_INT_RX_DONE\n"); */
 518                                 break;
 519                         case S5P_DSIM_INT_RX_TE:
 520                                 /* printk("S5P_DSIM_INT_RX_TE\n"); */
 521                                 break;
 522                         case S5P_DSIM_INT_RX_ACK:
 523                                 /* printk("S5P_DSIM_INT_RX_ACK\n"); */
 524                                 break;
 525                         case S5P_DSIM_INT_RX_ECC_ERR:
 526                                 /* printk("S5P_DSIM_INT_RX_ECC_ERR\n"); */
 527                                 break;
 528                         case S5P_DSIM_IMT_RX_CRC_ERR:
 529                                 /* printk("S5P_DSIM_IMT_RX_CRC_ERR\n"); */
 530                                 break;
 531                         case S5P_DSIM_INT_SFR_FIFO_EMPTY:
 532                                 /* printk("S5P_DSIM_INT_SFR_FIFO_EMPTY\n"); */
 533                                 complete_all(&dsim_wr_comp);
 534                                 break;
 535                         case S5P_DSIM_INT_MSK_FRAME_DONE:
 536                                 /* printk("S5P_DSIM_INT_MSK_FRAME_DONE\n"); */
 537                                 if (dsim->dsim_lcd_info->lcd_enabled && dsim->mipi_ddi_pd->resume_complete) {
 538                                         if (completion_done(&dsim_wr_comp) && completion_done(&dsim_rd_comp)) {
 539                                                 if (s3cfb_vsync_status_check()) {
 540                                                         s5p_dsim_toggle_hs_clock(dsim->reg_base);
 541                                                         if (!dsim->dsim_toggle_per_frame_count) {
 542                                                                 s5p_dsim_frame_done_interrupt_enable(dsim, 0);
 543                                                                 if (likely(dsim->dsim_info->hs_toggle))
 544                                                                         schedule_delayed_work(&dsim->dsim_work, dsim->dsim_info->hs_toggle);
 545                                                         }
 546                                                         if (dsim->dsim_toggle_per_frame_count)
 547                                                                 dsim->dsim_toggle_per_frame_count--;
 548                                                 }
 549                                         }
 550                                 }
 551                                 break;
 552                         }
 553                 }
 554         }
 555         /* clear irq */
 556         writel(intsrc, dsim->reg_base + S5P_DSIM_INTSRC);
 557         return IRQ_HANDLED;
 558 }
 559
 560 static void s5p_dsim_init_header_fifo(struct dsim_global *dsim)
 561 {
 562         unsigned int cnt;
 563
 564         for (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++)
 565                 dsim->header_fifo_index[cnt] = -1;
 566         return;
 567 }
 568
 569 static unsigned char s5p_dsim_pll_on(unsigned int dsim_base, unsigned char enable)
 570 {
 571         if (enable) {
 572                 int sw_timeout = 1000;
 573                 s5p_dsim_clear_interrupt(dsim_base, DSIM_PLL_STABLE);
 574                 s5p_dsim_enable_pll(dsim_base, 1);
 575                 while (1) {
 576                         sw_timeout--;
 577                         if (s5p_dsim_is_pll_stable(dsim_base))
 578                                 return DSIM_TRUE;
 579                         if (sw_timeout == 0)
 580                                 return DSIM_FALSE;
 581                 }
 582         } else
 583                 s5p_dsim_enable_pll(dsim_base, 0);
 584
 585         return DSIM_TRUE;
 586 }
 587
 588 static unsigned long s5p_dsim_change_pll(struct dsim_global *dsim, unsigned char pre_divider,
 589         unsigned short main_divider, unsigned char scaler)
 590 {
 591         unsigned long dfin_pll, dfvco, dpll_out;
 592         unsigned char freq_band;
 593         unsigned char temp0 = 0, temp1 = 0;
 594         unsigned int dsim_base = dsim->reg_base;
 595
 596         dfin_pll = (MIPI_FIN / pre_divider);
 597
 598         if (dfin_pll < 6 * 1000 * 1000 || dfin_pll > 12 * 1000 * 1000) {
 599                 dev_warn(dsim->dev, "warning!!\n");
 600                 dev_warn(dsim->dev, "fin_pll range is 6MHz ~ 12MHz\n");
 601                 dev_warn(dsim->dev, "fin_pll of mipi dphy pll is %luMHz\n", (dfin_pll / 1000000));
 602
 603                 s5p_dsim_enable_afc(dsim_base, 0, 0);
 604         } else {
 605                 if (dfin_pll < 7 * 1000000)
 606                         s5p_dsim_enable_afc(dsim_base, 1, 0x1);
 607                 else if (dfin_pll < 8 * 1000000)
 608                         s5p_dsim_enable_afc(dsim_base, 1, 0x0);
 609                 else if (dfin_pll < 9 * 1000000)
 610                         s5p_dsim_enable_afc(dsim_base, 1, 0x3);
 611                 else if (dfin_pll < 10 * 1000000)
 612                         s5p_dsim_enable_afc(dsim_base, 1, 0x2);
 613                 else if (dfin_pll < 11 * 1000000)
 614                         s5p_dsim_enable_afc(dsim_base, 1, 0x5);
 615                 else
 616                         s5p_dsim_enable_afc(dsim_base, 1, 0x4);
 617         }
 618
 619         dfvco = dfin_pll * main_divider;
 620         dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
 621                 dfvco, dfin_pll, main_divider);
 622         if (dfvco < 500000000 || dfvco > 1000000000) {
 623                 dev_warn(dsim->dev, "Caution!!\n");
 624                 dev_warn(dsim->dev, "fvco range is 500MHz ~ 1000MHz\n");
 625                 dev_warn(dsim->dev, "fvco of mipi dphy pll is %luMHz\n", (dfvco / 1000000));
 626         }
 627
 628         dpll_out = dfvco / (1 << scaler);
 629         dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
 630                 dpll_out, dfvco, scaler);
 631         if (dpll_out < 100 * 1000000)
 632                 freq_band = 0x0;
 633         else if (dpll_out < 120 * 1000000)
 634                 freq_band = 0x1;
 635         else if (dpll_out < 170 * 1000000)
 636                 freq_band = 0x2;
 637         else if (dpll_out < 220 * 1000000)
 638                 freq_band = 0x3;
 639         else if (dpll_out < 270 * 1000000)
 640                 freq_band = 0x4;
 641         else if (dpll_out < 320 * 1000000)
 642                 freq_band = 0x5;
 643         else if (dpll_out < 390 * 1000000)
 644                 freq_band = 0x6;
 645         else if (dpll_out < 450 * 1000000)
 646                 freq_band = 0x7;
 647         else if (dpll_out < 510 * 1000000)
 648                 freq_band = 0x8;
 649         else if (dpll_out < 560 * 1000000)
 650                 freq_band = 0x9;
 651         else if (dpll_out < 640 * 1000000)
 652                 freq_band = 0xa;
 653         else if (dpll_out < 690 * 1000000)
 654                 freq_band = 0xb;
 655         else if (dpll_out < 770 * 1000000)
 656                 freq_band = 0xc;
 657         else if (dpll_out < 870 * 1000000)
 658                 freq_band = 0xd;
 659         else if (dpll_out < 950 * 1000000)
 660                 freq_band = 0xe;
 661         else
 662                 freq_band = 0xf;
 663
 664         dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
 665
 666         s5p_dsim_pll_freq(dsim_base, pre_divider, main_divider, scaler);
 667
 668         s5p_dsim_hs_zero_ctrl(dsim_base, temp0);
 669         s5p_dsim_prep_ctrl(dsim_base, temp1);
 670
 671         /* Freq Band */
 672         s5p_dsim_pll_freq_band(dsim_base, freq_band);
 673
 674         /* Stable time */
 675         s5p_dsim_pll_stable_time(dsim_base, dsim->dsim_info->pll_stable_time);
 676
 677         /* Enable PLL */
 678         dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n", (dpll_out / 1000000));
 679
 680         return dpll_out;
 681 }
 682
 683 static void s5p_dsim_set_clock(struct dsim_global *dsim,
 684         unsigned char byte_clk_sel, unsigned char enable)
 685 {
 686         unsigned int esc_div;
 687         unsigned long esc_clk_error_rate;
 688         unsigned int dsim_base = dsim->reg_base;
 689
 690         if (enable) {
 691                 dsim->e_clk_src = byte_clk_sel;
 692
 693                 /* Escape mode clock and byte clock source */
 694                 s5p_dsim_set_byte_clock_src(dsim_base, byte_clk_sel);
 695
 696                 /* DPHY, DSIM Link : D-PHY clock out */
 697                 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
 698                         dsim->hs_clk = s5p_dsim_change_pll(dsim, dsim->dsim_info->p,
 699                                 dsim->dsim_info->m, dsim->dsim_info->s);
 700                         dsim->byte_clk = dsim->hs_clk / 8;
 701                         s5p_dsim_enable_pll_bypass(dsim_base, 0);
 702                         s5p_dsim_pll_on(dsim_base, 1);
 703                         usleep_range(1000, 1000);
 704                 /* DPHY : D-PHY clock out, DSIM link : external clock out */
 705                 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
 706                         dev_warn(dsim->dev, "this project is not supported external clock source for MIPI DSIM\n");
 707                 else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
 708                         dev_warn(dsim->dev, "this project is not supported external clock source for MIPI DSIM\n");
 709
 710                 /* escape clock divider */
 711                 esc_div = dsim->byte_clk / (dsim->dsim_info->esc_clk);
 712                 dev_dbg(dsim->dev, "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
 713                         esc_div, dsim->byte_clk, dsim->dsim_info->esc_clk);
 714                 if ((dsim->byte_clk / esc_div) >= 20000000 ||
 715                         (dsim->byte_clk / esc_div) > dsim->dsim_info->esc_clk)
 716                         esc_div += 1;
 717
 718                 dsim->escape_clk = dsim->byte_clk / esc_div;
 719                 dev_dbg(dsim->dev, "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
 720                         dsim->escape_clk, dsim->byte_clk, esc_div);
 721
 722                 /*
 723                  * enable escclk on lane
 724                  */
 725                 s5p_dsim_enable_byte_clock(dsim_base, DSIM_TRUE);
 726
 727                 /* enable byte clk and escape clock */
 728                 s5p_dsim_set_esc_clk_prs(dsim_base, 1, esc_div);
 729                 /* escape clock on lane */
 730                 s5p_dsim_enable_esc_clk_on_lane(dsim_base, (DSIM_LANE_CLOCK | dsim->data_lane), 1);
 731
 732                 dev_dbg(dsim->dev, "byte clock is %luMHz\n", (dsim->byte_clk / 1000000));
 733                 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n", (dsim->dsim_info->esc_clk / 1000000));
 734                 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
 735                 dev_dbg(dsim->dev, "escape clock is %luMHz\n", ((dsim->byte_clk / esc_div) / 1000000));
 736
 737                 if ((dsim->byte_clk / esc_div) > dsim->escape_clk) {
 738                         esc_clk_error_rate = dsim->escape_clk / (dsim->byte_clk / esc_div);
 739                         dev_warn(dsim->dev, "error rate is %lu over\n", (esc_clk_error_rate / 100));
 740                 } else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) {
 741                         esc_clk_error_rate = (dsim->byte_clk / esc_div) / dsim->escape_clk;
 742                         dev_warn(dsim->dev, "error rate is %lu under\n", (esc_clk_error_rate / 100));
 743                 }
 744         } else {
 745                 s5p_dsim_enable_esc_clk_on_lane(dsim_base, (DSIM_LANE_CLOCK | dsim->data_lane), 0);
 746                 s5p_dsim_set_esc_clk_prs(dsim_base, 0, 0);
 747
 748                 s5p_dsim_enable_byte_clock(dsim_base, DSIM_FALSE);
 749
 750                 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
 751                         s5p_dsim_pll_on(dsim_base, 0);
 752         }
 753 }
 754
 755 static int s5p_dsim_late_resume_init_dsim(struct dsim_global *dsim)
 756 {
 757         unsigned int dsim_base = dsim->reg_base;
 758
 759         if (dsim->pd->init_d_phy)
 760                 dsim->pd->init_d_phy(dsim->reg_base);
 761
 762         dsim->state = DSIM_STATE_RESET;
 763
 764         switch (dsim->dsim_info->e_no_data_lane) {
 765         case DSIM_DATA_LANE_1:
 766                 dsim->data_lane = DSIM_LANE_DATA0;
 767                 break;
 768         case DSIM_DATA_LANE_2:
 769                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
 770                 break;
 771         case DSIM_DATA_LANE_3:
 772                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 773                         DSIM_LANE_DATA2;
 774                 break;
 775         case DSIM_DATA_LANE_4:
 776                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 777                         DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
 778                 break;
 779         default:
 780                 dev_info(dsim->dev, "data lane is invalid\n");
 781                 return -1;
 782         };
 783
 784         s5p_dsim_init_header_fifo(dsim);
 785         s5p_dsim_sw_reset(dsim_base);
 786         s5p_dsim_dp_dn_swap(dsim_base, dsim->dsim_info->e_lane_swap);
 787
 788         /* enable only frame done interrupt */
 789         /* s5p_dsim_clear_interrupt(dsim_base, AllDsimIntr); */
 790         /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 1); */
 791
 792         return 0;
 793 }
 794
 795 #if 0
 796 static int s5p_dsim_init_dsim(struct dsim_global *dsim)
 797 {
 798         unsigned int dsim_base = dsim->reg_base;
 799
 800         if (dsim->pd->init_d_phy)
 801                 dsim->pd->init_d_phy(dsim->reg_base);
 802
 803         dsim->state = DSIM_STATE_RESET;
 804
 805         switch (dsim->dsim_info->e_no_data_lane) {
 806         case DSIM_DATA_LANE_1:
 807                 dsim->data_lane = DSIM_LANE_DATA0;
 808                 break;
 809         case DSIM_DATA_LANE_2:
 810                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
 811                 break;
 812         case DSIM_DATA_LANE_3:
 813                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 814                         DSIM_LANE_DATA2;
 815                 break;
 816         case DSIM_DATA_LANE_4:
 817                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 818                         DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
 819                 break;
 820         default:
 821                 dev_info(dsim->dev, "data lane is invalid\n");
 822                 return -1;
 823         };
 824
 825         s5p_dsim_init_header_fifo(dsim);
 826         s5p_dsim_dp_dn_swap(dsim_base, dsim->dsim_info->e_lane_swap);
 827
 828         /* enable only frame done interrupt */
 829         /* s5p_dsim_clear_interrupt(dsim_base, AllDsimIntr); */
 830         /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 1); */
 831
 832         return 0;
 833 }
 834 #endif
 835
 836 static void s5p_dsim_set_display_mode(struct dsim_global *dsim,
 837         struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)
 838 {
 839         struct s3cfb_lcd *main_lcd_panel_info = NULL, *sub_lcd_panel_info = NULL;
 840         struct s3cfb_lcd_timing *main_timing = NULL;
 841         unsigned int dsim_base = dsim->reg_base;
 842
 843         if (main_lcd != NULL) {
 844                 if (main_lcd->lcd_panel_info != NULL) {
 845                         main_lcd_panel_info =
 846                                 (struct s3cfb_lcd *) main_lcd->lcd_panel_info;
 847
 848                         s5p_dsim_set_main_disp_resol(dsim_base,
 849                                 main_lcd_panel_info->height,
 850                                 main_lcd_panel_info->width);
 851                 } else
 852                         dev_warn(dsim->dev, "lcd panel info of main lcd is NULL\n");
 853         } else {
 854                 dev_err(dsim->dev, "main lcd is NULL\n");
 855                 return;
 856         }
 857
 858         /* in case of VIDEO MODE (RGB INTERFACE) */
 859         if (dsim->dsim_lcd_info->e_interface == (u32)DSIM_VIDEO) {
 860
 861                 main_timing = &main_lcd_panel_info->timing;
 862                 if (main_timing == NULL) {
 863                         dev_err(dsim->dev, "main_timing is NULL\n");
 864                         return;
 865                 }
 866
 867                 s5p_dsim_set_main_disp_vporch(dsim_base,
 868                                 main_timing->cmd_allow_len,
 869                                 main_timing->stable_vfp, (u16) main_timing->v_bp);
 870                 s5p_dsim_set_main_disp_hporch(dsim_base,
 871                                 main_timing->h_fp, (u16) main_timing->h_bp);
 872                 s5p_dsim_set_main_disp_sync_area(dsim_base,
 873                                 main_timing->v_sw, (u16) main_timing->h_sw);
 874
 875         /* in case of COMMAND MODE (CPU or I80 INTERFACE) */
 876         } else {
 877                 if (sub_lcd != NULL) {
 878                         if (sub_lcd->lcd_panel_info != NULL) {
 879                                 sub_lcd_panel_info =
 880                                         (struct s3cfb_lcd *)
 881                                                 sub_lcd->lcd_panel_info;
 882
 883                                 s5p_dsim_set_sub_disp_resol(dsim_base,
 884                                         sub_lcd_panel_info->height,
 885                                         sub_lcd_panel_info->width);
 886                         } else
 887                                 dev_warn(dsim->dev, "lcd panel info of sub lcd is NULL\n");
 888                 }
 889         }
 890
 891         s5p_dsim_display_config(dsim_base, dsim->dsim_lcd_info, NULL);
 892 }
 893
 894 static int s5p_dsim_init_link(struct dsim_global *dsim)
 895 {
 896         unsigned int time_out = 100;
 897         unsigned int dsim_base = dsim->reg_base;
 898
 899         switch (dsim->state) {
 900         case DSIM_STATE_RESET:
 901         case DSIM_STATE_INIT:
 902                 s5p_dsim_init_fifo_pointer(dsim_base, 0x0);
 903                 usleep_range(10000, 10000);
 904                 s5p_dsim_init_fifo_pointer(dsim_base, 0x1f);
 905
 906                 /* dsi configuration */
 907                 s5p_dsim_init_config(dsim_base, dsim->dsim_lcd_info, NULL, dsim->dsim_info);
 908                 s5p_dsim_enable_lane(dsim_base, DSIM_LANE_CLOCK, 1);
 909                 s5p_dsim_enable_lane(dsim_base, dsim->data_lane, 1);
 910
 911                 /* set clock configuration */
 912                 s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk, 1);
 913                 usleep_range(5000, 5000);
 914                 /* check clock and data lane state is stop state */
 915                 while (!(s5p_dsim_is_lane_state(dsim_base, DSIM_LANE_CLOCK) == DSIM_LANE_STATE_STOP) &&
 916                         !(s5p_dsim_is_lane_state(dsim_base, dsim->data_lane) == DSIM_LANE_STATE_STOP)) {
 917                         time_out--;
 918                         if (time_out == 0) {
 919                                 dev_info(dsim->dev, "DSI Master state is not stop state!!!\n");
 920                                 dev_info(dsim->dev, "Please check initialization process\n");
 921
 922                                 return DSIM_FALSE;
 923                         }
 924                 }
 925
 926                 if (time_out != 0) {
 927                         /* dev_info(dsim->dev, "initialization of DSI Master is successful\n"); */
 928                         /* dev_info(dsim->dev, "DSI Master state is stop state\n"); */
 929                 }
 930
 931                 dsim->state = DSIM_STATE_STOP;
 932
 933                 /* BTA sequence counters */
 934                 s5p_dsim_set_stop_state_counter(dsim_base, dsim->dsim_info->stop_holding_cnt);
 935                 s5p_dsim_set_bta_timeout(dsim_base, dsim->dsim_info->bta_timeout);
 936                 s5p_dsim_set_lpdr_timeout(dsim_base, dsim->dsim_info->rx_timeout);
 937
 938                 /* default LPDT by both cpu and lcd controller */
 939                 s5p_dsim_set_data_mode(dsim_base, DSIM_TRANSFER_BOTH, DSIM_STATE_STOP);
 940
 941                 return DSIM_TRUE;
 942         default:
 943                 dev_info(dsim->dev, "DSI Master is already init\n");
 944
 945                 return DSIM_FALSE;
 946         }
 947 }
 948
 949 static unsigned char s5p_dsim_set_hs_enable(struct dsim_global *dsim)
 950 {
 951         u8 ret = DSIM_FALSE;
 952         unsigned int dsim_base = dsim->reg_base;
 953
 954         if (dsim->state == DSIM_STATE_STOP) {
 955                 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
 956                         dsim->state = DSIM_STATE_HSCLKEN;
 957                         s5p_dsim_set_data_mode(dsim_base, DSIM_TRANSFER_BOTH, DSIM_STATE_HSCLKEN);
 958                         s5p_dsim_enable_hs_clock(dsim_base, 1);
 959
 960                         ret = DSIM_TRUE;
 961                 } else
 962                         dev_warn(dsim->dev, "clock source is external bypass\n");
 963         } else
 964                 dev_warn(dsim->dev, "DSIM is not stop state\n");
 965
 966         return ret;
 967 }
 968
 969 #if 0
 970 static unsigned char s5p_dsim_set_stopstate(struct dsim_global *dsim)
 971 {
 972         u8 ret =  DSIM_FALSE;
 973         unsigned int dsim_base = dsim->reg_base;
 974
 975         if (dsim->state == DSIM_STATE_HSCLKEN) {
 976                 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
 977                         dsim->state = DSIM_STATE_STOP;
 978                         s5p_dsim_enable_hs_clock(dsim_base, 0);
 979                         ret = DSIM_TRUE;
 980                 } else
 981                         dev_warn(dsim->dev, "clock source is external bypass\n");
 982         } else if (dsim->state == DSIM_STATE_ULPS) {
 983                 /* will be update for exiting ulps */
 984                 ret = DSIM_TRUE;
 985         } else if (dsim->state == DSIM_STATE_STOP) {
 986                 dev_warn(dsim->dev, "DSIM is already stop state\n");
 987                 ret = DSIM_TRUE;
 988         } else
 989                 dev_warn(dsim->dev, "DSIM is not stop state\n");
 990
 991         return ret;
 992 }
 993 #endif
 994
 995 static unsigned char s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,
 996         unsigned char data_path, unsigned char hs_enable)
 997 {
 998         u8 ret = DSIM_FALSE;
 999         unsigned int dsim_base = dsim->reg_base;
1000
1001         if (hs_enable) {
1002                 if (dsim->state == DSIM_STATE_HSCLKEN) {
1003                         s5p_dsim_set_data_mode(dsim_base, data_path, DSIM_STATE_HSCLKEN);
1004                         ret = DSIM_TRUE;
1005                 } else {
1006                         dev_err(dsim->dev, "HS Clock lane is not enabled\n");
1007                         ret = DSIM_FALSE;
1008                 }
1009         } else {
1010                 if (dsim->state == DSIM_STATE_INIT || dsim->state == DSIM_STATE_ULPS) {
1011                         dev_err(dsim->dev, "DSI Master is not STOP or HSDT state\n");
1012                         ret = DSIM_FALSE;
1013                 } else {
1014                         s5p_dsim_set_data_mode(dsim_base, data_path, DSIM_STATE_STOP);
1015                         ret = DSIM_TRUE;
1016                 }
1017         }
1018
1019         return ret;
1020 }
1021
1022 int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv)
1023 {
1024         struct mipi_lcd_info *lcd_info = NULL;
1025         struct dsim_global *dsim = g_dsim;
1026
1027         lcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL);
1028         if (lcd_info == NULL)
1029                 return -ENOMEM;
1030
1031         lcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver), GFP_KERNEL);
1032         if (lcd_info->mipi_drv == NULL) {
1033                 kfree(lcd_info);
1034                 return -ENOMEM;
1035         }
1036
1037         memcpy(lcd_info->mipi_drv, lcd_drv, sizeof(struct mipi_lcd_driver));
1038
1039         mutex_lock(&mipi_lock);
1040         list_add_tail(&lcd_info->list, &lcd_info_list);
1041         mutex_unlock(&mipi_lock);
1042
1043         dev_dbg(dsim->dev, "registered lcd panel driver(%s) to mipi-dsi driver\n", lcd_drv->name);
1044
1045         return 0;
1046 }
1047
1048 static struct mipi_lcd_driver *scan_mipi_driver(struct dsim_global *dsim, const char *name)
1049 {
1050         struct mipi_lcd_info *lcd_info;
1051         struct mipi_lcd_driver *mipi_drv = NULL;
1052
1053         mutex_lock(&mipi_lock);
1054
1055         dev_dbg(dsim->dev, "find lcd panel driver(%s)\n", name);
1056
1057         list_for_each_entry(lcd_info, &lcd_info_list, list) {
1058                 mipi_drv = lcd_info->mipi_drv;
1059
1060                 if ((strcmp(mipi_drv->name, name)) == 0) {
1061                         mutex_unlock(&mipi_lock);
1062                         dev_dbg(dsim->dev, "found!!!(%s)\n", mipi_drv->name);
1063                         return mipi_drv;
1064                 }
1065         }
1066
1067         dev_warn(dsim->dev, "failed to find lcd panel driver(%s)\n", name);
1068
1069         mutex_unlock(&mipi_lock);
1070
1071         return NULL;
1072 }
1073
1074 static void s5p_dsim_interrupt_mask_set(struct dsim_global *dsim)
1075 {
1076         u32 int_stat;
1077
1078         int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1079
1080         int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1081                 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1082                 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1083                 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1084                 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1085
1086         writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1087 }
1088
1089 static int s5p_dsim_fifo_clear(struct dsim_global *dsim)
1090 {
1091         int dsim_count = 0, ret;
1092
1093         writel(SwRstRelease, dsim->reg_base + S5P_DSIM_INTSRC);
1094
1095         writel(DSIM_FUNCRST, dsim->reg_base + S5P_DSIM_SWRST);
1096
1097         do {
1098                 if (++dsim_count > 90000) {
1099                         dev_err(dsim->dev, "dsim fifo clear fail re_try dsim resume\n");
1100                         ret = 0;
1101                         break;
1102                 }
1103
1104                 if (readl(dsim->reg_base + S5P_DSIM_INTSRC) & SwRstRelease) {
1105                         ret = 1;
1106                         break;
1107                 }
1108         } while (1);
1109
1110         return ret;
1111 }
1112
1113 #ifdef CONFIG_HAS_EARLYSUSPEND
1114 void s5p_dsim_early_suspend(void)
1115 {
1116         u32 int_stat = 0;
1117         pm_message_t state;
1118         struct dsim_global *dsim = g_dsim;
1119
1120         dev_info(dsim->dev, "+%s\n", __func__);
1121
1122         if (dsim->mipi_ddi_pd->resume_complete == 0)
1123                 return;
1124
1125         dsim->mipi_ddi_pd->resume_complete = 0;
1126         dsim->dsim_lcd_info->lcd_enabled = 0;
1127
1128         /* int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK); */
1129
1130         int_stat |= ((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1131                 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1132                 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1133                 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1134                 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY) | (0x01 << S5P_DSIM_INT_MSK_FRAME_DONE));
1135
1136         writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1137
1138         /* disable_irq(dsim->irq); */
1139         state.event = PM_EVENT_SUSPEND;
1140
1141         if (dsim->mipi_drv->suspend)
1142                 dsim->mipi_drv->suspend(dsim->dev, state);
1143
1144         if (dsim->mipi_ddi_pd->lcd_power_on)
1145                 dsim->mipi_ddi_pd->lcd_power_on(dsim->dev, 0);
1146
1147         s5p_dsim_enable_hs_clock(dsim->reg_base, 0);
1148         s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk, 0);
1149
1150 #if defined(CONFIG_CPU_EXYNOS4210)
1151         writel(0x1, dsim->reg_base + S5P_DSIM_SWRST);
1152 #endif
1153
1154         if (dsim->pd->exit_d_phy)
1155                 dsim->pd->exit_d_phy(dsim->reg_base);
1156
1157         clk_disable(dsim->clock);
1158
1159         if (dsim->pd->mipi_power)
1160                 dsim->pd->mipi_power(0);
1161
1162         dev_info(dsim->dev, "-%s\n", __func__);
1163
1164         return;
1165 }
1166
1167 void s5p_dsim_late_resume(void)
1168 {
1169         struct dsim_global *dsim = g_dsim;
1170
1171         dev_info(dsim->dev, "+%s\n", __func__);
1172
1173         /* MIPI SIGNAL ON */
1174         if (dsim->pd->mipi_power)
1175                 dsim->pd->mipi_power(1);
1176
1177         clk_enable(dsim->clock);
1178         usleep_range(10000, 10000);
1179
1180         if (dsim->mipi_ddi_pd->lcd_power_on)
1181                 dsim->mipi_ddi_pd->lcd_power_on(dsim->dev, 1);
1182         usleep_range(25000, 25000);
1183
1184         if (dsim->mipi_ddi_pd->lcd_reset)
1185                 dsim->mipi_ddi_pd->lcd_reset();
1186         usleep_range(5000, 5000);
1187
1188         s5p_dsim_late_resume_init_dsim(dsim);
1189         s5p_dsim_init_link(dsim);
1190         usleep_range(10000, 10000);
1191         s5p_dsim_set_hs_enable(dsim);
1192         s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYCPU, 1);
1193         s5p_dsim_set_display_mode(dsim, dsim->dsim_lcd_info, NULL);
1194         s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYLCDC, 1);
1195         /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 0); */
1196
1197 #if defined(CONFIG_CPU_EXYNOS4210)
1198         if (s5p_dsim_fifo_clear(dsim) == 0)
1199                 dev_err(dsim->dev, "dsim fifo clear fail!!!\n");
1200 #endif
1201
1202         s5p_dsim_interrupt_mask_set(dsim);
1203
1204         dsim->mipi_ddi_pd->resume_complete = 1;
1205
1206         dev_info(dsim->dev, "-%s\n", __func__);
1207
1208         return;
1209 }
1210
1211 #else
1212 #ifdef CONFIG_PM
1213 static int s5p_dsim_suspend(struct platform_device *pdev, pm_message_t state)
1214 {
1215         struct dsim_global *dsim = platform_get_drvdata(pdev);
1216
1217         dev_info(&pdev->dev, "%s\n", __func__);
1218
1219         dsim->mipi_ddi_pd->resume_complete = 0;
1220
1221         if (dsim->mipi_drv->suspend)
1222                 dsim->mipi_drv->suspend(&pdev->dev, state);
1223         else
1224                 dev_warn(&pdev->dev, "suspend func is null\n");
1225
1226         clk_disable(dsim->clock);
1227
1228         if (dsim->pd->mipi_power)
1229                 dsim->pd->mipi_power(0);
1230         else
1231                 dev_warn(&pdev->dev, "mipi_power func is null\n");
1232
1233         return 0;
1234 }
1235
1236 static int s5p_dsim_resume(struct platform_device *pdev)
1237 {
1238         u32 int_stat;
1239
1240         struct dsim_global *dsim = platform_get_drvdata(pdev);
1241
1242         dev_info(&pdev->dev, "%s\n", __func__);
1243
1244         if (dsim->pd->mipi_power)
1245                 dsim->pd->mipi_power(1);
1246         else
1247                 dev_warn(&pdev->dev, "mipi_power func is null\n");
1248
1249         usleep_range(10000, 10000);
1250
1251         clk_enable(dsim->clock);
1252
1253         if (dsim->mipi_drv->resume)
1254                 dsim->mipi_drv->resume(&pdev->dev);
1255         else
1256                 dev_warn(&pdev->dev, "resume func is null\n");
1257
1258         s5p_dsim_init_dsim(dsim);
1259         s5p_dsim_init_link(dsim);
1260
1261         s5p_dsim_set_hs_enable(dsim);
1262         s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYCPU, 1);
1263
1264         msleep(120);
1265
1266         /* initialize lcd panel */
1267         if (dsim->mipi_drv->init)
1268                 dsim->mipi_drv->init(&pdev->dev);
1269         else
1270                 dev_warn(&pdev->dev, "init func is null\n");
1271
1272         s5p_dsim_set_display_mode(dsim, dsim->dsim_lcd_info, NULL);
1273
1274         s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYLCDC, 1);
1275
1276         int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1277
1278         int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1279                 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1280                 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1281                 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1282                 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1283
1284         writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1285
1286         dsim->mipi_ddi_pd->resume_complete = 1;
1287
1288         return 0;
1289 }
1290 #else
1291 #define s5p_dsim_suspend NULL
1292 #define s5p_dsim_resume NULL
1293 #endif
1294 #endif
1295
1296 u32 read_dsim_register(u32 num)
1297 {
1298         struct dsim_global *dsim = g_dsim;
1299
1300         return readl(dsim->reg_base + (num*4));
1301 }
1302
1303 static ssize_t hs_toggle_show(struct device *dev,
1304         struct device_attribute *attr, char *buf)
1305 {
1306         char temp[3];
1307         struct dsim_global *dsim = container_of(dev, struct dsim_global, panel);
1308
1309         sprintf(temp, "%d\n", jiffies_to_msecs(dsim->dsim_info->hs_toggle));
1310         strcpy(buf, temp);
1311
1312         return strlen(buf);
1313 }
1314
1315 static int hs_toggle_store(struct device *dev,
1316         struct device_attribute *attr, const char *buf, size_t size)
1317 {
1318         int value;
1319         int rc;
1320         struct dsim_global *dsim = container_of(dev, struct dsim_global, panel);
1321
1322         rc = strict_strtoul(buf, (unsigned int)0, (unsigned long *)&value);
1323         if (rc < 0)
1324                 return rc;
1325         else {
1326                 dev_info(dev, "%s - %d, %d\n", __func__, jiffies_to_msecs(dsim->dsim_info->hs_toggle), value);
1327
1328                 if (value == 1)
1329                         dsim->dsim_info->hs_toggle = msecs_to_jiffies(3000);
1330                 else
1331                         dsim->dsim_info->hs_toggle = 0;
1332         }
1333         return size;
1334 }
1335
1336 static DEVICE_ATTR(hs_toggle, 0644, hs_toggle_show, hs_toggle_store);
1337
1338 static ssize_t dsim_dump_show(struct device *dev,
1339         struct device_attribute *attr, char *buf)
1340 {
1341         int reg_val, i;
1342         char temp[50];
1343         struct dsim_global *dsim = dev_get_drvdata(dev);
1344
1345         for (i = 0; i < 25; i++) {
1346                 reg_val = readl(dsim->reg_base + i*4);
1347                 sprintf(temp, "[DSIM]0x11C8_00%02X = 0x%08X\n", (i*4), reg_val);
1348                 strcat(buf, temp);
1349         }
1350
1351         return strlen(buf);
1352 }
1353 static DEVICE_ATTR(dsim_dump, 0444, dsim_dump_show, NULL);
1354
1355 static struct dsim_ops s5p_dsim_ops = {
1356         .cmd_write      = s5p_dsim_wr_data,
1357         .cmd_read       = s5p_dsim_rd_data,
1358         .cmd_dcs_read   = s5p_dsim_dcs_rd_data,
1359         .suspend        = s5p_dsim_early_suspend,
1360         .resume         = s5p_dsim_late_resume,
1361 };
1362
1363 static int s5p_dsim_probe(struct platform_device *pdev)
1364 {
1365         struct resource *res;
1366         int ret = -1;
1367         u32 int_stat;
1368         struct dsim_global *dsim;
1369
1370         dsim = kzalloc(sizeof(struct dsim_global), GFP_KERNEL);
1371         if (!dsim) {
1372                 pr_err("failed to allocate for dsim_global\n");
1373                 ret = -ENOMEM;
1374                 goto err_alloc;
1375         }
1376
1377         g_dsim = dsim;
1378
1379         dsim->pd = to_dsim_plat(&pdev->dev);
1380         if (!dsim->pd) {
1381                 dev_err(&pdev->dev, "platform data is NULL\n");
1382                 ret = -EINVAL;
1383                 goto err_plat;
1384         }
1385
1386         dsim->dev = &pdev->dev;
1387
1388         /* set dsim config data, dsim lcd config data and lcd panel data. */
1389         dsim->dsim_info = dsim->pd->dsim_info;
1390         dsim->dsim_lcd_info = dsim->pd->dsim_lcd_info;
1391         dsim->lcd_panel_info = (struct s3cfb_lcd *) dsim->dsim_lcd_info->lcd_panel_info;
1392         dsim->mipi_ddi_pd = (struct mipi_ddi_platform_data *) dsim->dsim_lcd_info->mipi_ddi_pd;
1393         dsim->mipi_ddi_pd->te_irq = dsim->pd->te_irq;
1394
1395         if (dsim->pd->mipi_power)
1396                 dsim->pd->mipi_power(1);
1397
1398         strcpy(dsim->pd->lcd_panel_name, dsim->lcd_panel_info->name);
1399
1400         /* clock */
1401         dsim->clock = clk_get(&pdev->dev, dsim->pd->clk_name);
1402         if (IS_ERR(dsim->clock)) {
1403                 dev_err(&pdev->dev, "failed to get dsim clock source\n");
1404                 ret = -EINVAL;
1405                 goto err_clk_get;
1406         }
1407
1408         clk_enable(dsim->clock);
1409
1410         /* io memory */
1411         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412         if (!res) {
1413                 dev_err(&pdev->dev, "failed to get io memory region\n");
1414                 ret = -EINVAL;
1415                 goto err_clk_disable;
1416         }
1417
1418         /* request mem region */
1419         res = request_mem_region(res->start,
1420                                  res->end - res->start + 1, pdev->name);
1421         if (!res) {
1422                 dev_err(&pdev->dev, "failed to request io memory region\n");
1423                 ret = -EINVAL;
1424                 goto err_clk_disable;
1425         }
1426
1427         /* ioremap for register block */
1428         dsim->reg_base = (unsigned int)ioremap(res->start,
1429                         res->end - res->start + 1);
1430         if (!dsim->reg_base) {
1431                 dev_err(&pdev->dev, "failed to remap io region\n");
1432                 ret = -EINVAL;
1433                 goto err_clk_disable;
1434         }
1435
1436         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1437         if (!res) {
1438                 dev_err(&pdev->dev, "failed to request dsim irq resource\n");
1439                 ret = -EINVAL;
1440                 goto err_clk_disable;
1441         }
1442         /* dsim->irq = res->start; */
1443
1444         /* clear interrupt */
1445         /* int_stat = readl(dsim->reg_base + S5P_DSIM_INTSRC); */
1446         int_stat = 0xffffffff;
1447         writel(int_stat, dsim->reg_base + S5P_DSIM_INTSRC);
1448
1449         /* enable interrupts */
1450         int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1451
1452         int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1453                 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1454                 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1455                 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1456                 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1457
1458         writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1459
1460         init_completion(&dsim_rd_comp);
1461         init_completion(&dsim_wr_comp);
1462         mutex_init(&dsim_rd_wr_mutex);
1463
1464         dsim->mipi_ddi_pd->resume_complete = 1;
1465         dsim->dsim_lcd_info->lcd_enabled = 1;
1466
1467         ret = request_irq(res->start, (void *)s5p_dsim_isr, IRQF_DISABLED, pdev->name, dsim);
1468         if (ret != 0) {
1469                 dev_err(&pdev->dev, "failed to request dsim irq\n");
1470                 ret = -EINVAL;
1471                 goto err_clk_disable;
1472         }
1473
1474         INIT_DELAYED_WORK(&dsim->dsim_work, dsim_work_q_handler);
1475         INIT_DELAYED_WORK(&dsim->check_hs_toggle_work, dsim_check_hs_toggle_work_q_handler);
1476
1477         dsim->ops = &s5p_dsim_ops;
1478
1479         platform_set_drvdata(pdev, dsim);
1480
1481         dsim->panel.parent = &pdev->dev;
1482         dev_set_name(&dsim->panel, dsim->pd->lcd_panel_name);
1483         ret = device_register(&dsim->panel);
1484         if (ret < 0) {
1485                 dev_err(&pdev->dev, "faild device register\n");
1486                 ret = -EINVAL;
1487                 goto mipi_drv_err;
1488         }
1489
1490         /* find lcd panel driver registered to mipi-dsi driver. */
1491         dsim->mipi_drv = scan_mipi_driver(dsim, dsim->pd->lcd_panel_name);
1492         if (dsim->mipi_drv == NULL) {
1493                 dev_err(&pdev->dev, "mipi_drv is NULL\n");
1494                 ret = -EINVAL;
1495                 goto mipi_drv_err;
1496         }
1497
1498         ret = dsim->mipi_drv->probe(&dsim->panel);
1499         if (ret < 0) {
1500                 dev_err(&pdev->dev, "faild probe\n");
1501                 ret = -EINVAL;
1502                 goto mipi_drv_err;
1503         }
1504
1505         dsim->state = DSIM_STATE_HSCLKEN;
1506
1507         ret = device_create_file(&(pdev->dev), &dev_attr_dsim_dump);
1508         if (ret < 0)
1509                 dev_err(&pdev->dev, "failed to add sysfs entries, %d\n", __LINE__);
1510
1511         if (!dsim->dsim_info->hs_toggle) {
1512                 ret = device_create_file(&dsim->panel, &dev_attr_hs_toggle);
1513                 if (ret < 0)
1514                         dev_err(&pdev->dev, "failed to add sysfs entries, %d\n", __LINE__);
1515         }
1516
1517         if (dsim->dsim_info->hs_toggle)
1518                 s5p_dsim_frame_done_interrupt_enable(dsim, 1);
1519
1520         dev_info(&pdev->dev, "mipi-dsi driver has been probed\n");
1521
1522 #if 0
1523 #ifdef CONFIG_HAS_WAKELOCK
1524 #ifdef CONFIG_HAS_EARLYSUSPEND
1525         dsim->early_suspend.suspend = s5p_dsim_early_suspend;
1526         dsim->early_suspend.resume = s5p_dsim_late_resume;
1527         dsim->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 1;
1528         register_early_suspend(&dsim->early_suspend);
1529 #endif
1530 #endif
1531 #endif
1532         return 0;
1533
1534 mipi_drv_err:
1535         free_irq(res->start, &dsim);
1536         dsim->pd->mipi_power(0);
1537
1538 err_clk_disable:
1539         clk_disable(dsim->clock);
1540
1541 err_clk_get:
1542 err_plat:
1543         kfree(dsim);
1544
1545 err_alloc:
1546         return ret;
1547 }
1548
1549 static int s5p_dsim_remove(struct platform_device *pdev)
1550 {
1551         return 0;
1552 }
1553
1554 static struct platform_driver s5p_dsim_driver = {
1555         .probe = s5p_dsim_probe,
1556         .remove = s5p_dsim_remove,
1557 #ifndef CONFIG_HAS_EARLYSUSPEND
1558         .suspend = s5p_dsim_suspend,
1559         .resume = s5p_dsim_resume,
1560 #endif
1561         .driver = {
1562                    .name = "s5p-dsim",
1563                    .owner = THIS_MODULE,
1564         },
1565 };
1566
1567 static int s5p_dsim_register(void)
1568 {
1569         return platform_driver_register(&s5p_dsim_driver);
1570 }
1571
1572 static void s5p_dsim_unregister(void)
1573 {
1574         platform_driver_unregister(&s5p_dsim_driver);
1575 }
1576
1577 module_init(s5p_dsim_register);
1578 module_exit(s5p_dsim_unregister);
1579
1580 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
1581 MODULE_DESCRIPTION("Samusung MIPI-DSIM driver");
1582 MODULE_LICENSE("GPL");