drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/prefetch.h>
  45 #include <scsi/fc/fc_fcoe.h>
  46
  47 #include "ixgbe.h"
  48 #include "ixgbe_common.h"
  49 #include "ixgbe_dcb_82599.h"
  50 #include "ixgbe_sriov.h"
  51
  52 char ixgbe_driver_name[] = "ixgbe";
  53 static const char ixgbe_driver_string[] =
  54                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  55 #define MAJ 3
  56 #define MIN 3
  57 #define BUILD 8
  58 #define KFIX 2
  59 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  60         __stringify(BUILD) "-k" __stringify(KFIX)
  61 const char ixgbe_driver_version[] = DRV_VERSION;
  62 static const char ixgbe_copyright[] =
  63                                 "Copyright (c) 1999-2011 Intel Corporation.";
  64
  65 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  66         [board_82598] = &ixgbe_82598_info,
  67         [board_82599] = &ixgbe_82599_info,
  68         [board_X540] = &ixgbe_X540_info,
  69 };
  70
  71 /* ixgbe_pci_tbl - PCI Device ID Table
  72  *
  73  * Wildcard entries (PCI_ANY_ID) should come last
  74  * Last entry must be all 0s
  75  *
  76  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  77  *   Class, Class Mask, private data (not used) }
  78  */
  79 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  99          board_82598 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 101          board_82598 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 103          board_82598 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 105          board_82599 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 121          board_82599 },
 122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 123          board_82599 },
 124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 125          board_82599 },
 126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 127          board_X540 },
 128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 129          board_82599 },
 130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 131          board_82599 },
 132
 133         /* required last entry */
 134         {0, }
 135 };
 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 137
 138 #ifdef CONFIG_IXGBE_DCA
 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 140                             void *p);
 141 static struct notifier_block dca_notifier = {
 142         .notifier_call = ixgbe_notify_dca,
 143         .next          = NULL,
 144         .priority      = 0
 145 };
 146 #endif
 147
 148 #ifdef CONFIG_PCI_IOV
 149 static unsigned int max_vfs;
 150 module_param(max_vfs, uint, 0);
 151 MODULE_PARM_DESC(max_vfs,
 152                  "Maximum number of virtual functions to allocate per physical function");
 153 #endif /* CONFIG_PCI_IOV */
 154
 155 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 156 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 157 MODULE_LICENSE("GPL");
 158 MODULE_VERSION(DRV_VERSION);
 159
 160 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 161
 162 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 163 {
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         u32 gcr;
 166         u32 gpie;
 167         u32 vmdctl;
 168
 169 #ifdef CONFIG_PCI_IOV
 170         /* disable iov and allow time for transactions to clear */
 171         pci_disable_sriov(adapter->pdev);
 172 #endif
 173
 174         /* turn off device IOV mode */
 175         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 176         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 177         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 178         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 179         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 180         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 181
 182         /* set default pool back to 0 */
 183         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 184         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 185         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 186
 187         /* take a breather then clean up driver data */
 188         msleep(100);
 189
 190         kfree(adapter->vfinfo);
 191         adapter->vfinfo = NULL;
 192
 193         adapter->num_vfs = 0;
 194         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 195 }
 196
 197 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 198 {
 199         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 200             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 201                 schedule_work(&adapter->service_task);
 202 }
 203
 204 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 205 {
 206         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 207
 208         /* flush memory to make sure state is correct before next watchog */
 209         smp_mb__before_clear_bit();
 210         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 211 }
 212
 213 struct ixgbe_reg_info {
 214         u32 ofs;
 215         char *name;
 216 };
 217
 218 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 219
 220         /* General Registers */
 221         {IXGBE_CTRL, "CTRL"},
 222         {IXGBE_STATUS, "STATUS"},
 223         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 224
 225         /* Interrupt Registers */
 226         {IXGBE_EICR, "EICR"},
 227
 228         /* RX Registers */
 229         {IXGBE_SRRCTL(0), "SRRCTL"},
 230         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 231         {IXGBE_RDLEN(0), "RDLEN"},
 232         {IXGBE_RDH(0), "RDH"},
 233         {IXGBE_RDT(0), "RDT"},
 234         {IXGBE_RXDCTL(0), "RXDCTL"},
 235         {IXGBE_RDBAL(0), "RDBAL"},
 236         {IXGBE_RDBAH(0), "RDBAH"},
 237
 238         /* TX Registers */
 239         {IXGBE_TDBAL(0), "TDBAL"},
 240         {IXGBE_TDBAH(0), "TDBAH"},
 241         {IXGBE_TDLEN(0), "TDLEN"},
 242         {IXGBE_TDH(0), "TDH"},
 243         {IXGBE_TDT(0), "TDT"},
 244         {IXGBE_TXDCTL(0), "TXDCTL"},
 245
 246         /* List Terminator */
 247         {}
 248 };
 249
 250
 251 /*
 252  * ixgbe_regdump - register printout routine
 253  */
 254 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 255 {
 256         int i = 0, j = 0;
 257         char rname[16];
 258         u32 regs[64];
 259
 260         switch (reginfo->ofs) {
 261         case IXGBE_SRRCTL(0):
 262                 for (i = 0; i < 64; i++)
 263                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 264                 break;
 265         case IXGBE_DCA_RXCTRL(0):
 266                 for (i = 0; i < 64; i++)
 267                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 268                 break;
 269         case IXGBE_RDLEN(0):
 270                 for (i = 0; i < 64; i++)
 271                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 272                 break;
 273         case IXGBE_RDH(0):
 274                 for (i = 0; i < 64; i++)
 275                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 276                 break;
 277         case IXGBE_RDT(0):
 278                 for (i = 0; i < 64; i++)
 279                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 280                 break;
 281         case IXGBE_RXDCTL(0):
 282                 for (i = 0; i < 64; i++)
 283                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 284                 break;
 285         case IXGBE_RDBAL(0):
 286                 for (i = 0; i < 64; i++)
 287                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 288                 break;
 289         case IXGBE_RDBAH(0):
 290                 for (i = 0; i < 64; i++)
 291                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 292                 break;
 293         case IXGBE_TDBAL(0):
 294                 for (i = 0; i < 64; i++)
 295                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 296                 break;
 297         case IXGBE_TDBAH(0):
 298                 for (i = 0; i < 64; i++)
 299                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 300                 break;
 301         case IXGBE_TDLEN(0):
 302                 for (i = 0; i < 64; i++)
 303                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 304                 break;
 305         case IXGBE_TDH(0):
 306                 for (i = 0; i < 64; i++)
 307                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 308                 break;
 309         case IXGBE_TDT(0):
 310                 for (i = 0; i < 64; i++)
 311                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 312                 break;
 313         case IXGBE_TXDCTL(0):
 314                 for (i = 0; i < 64; i++)
 315                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 316                 break;
 317         default:
 318                 pr_info("%-15s %08x\n", reginfo->name,
 319                         IXGBE_READ_REG(hw, reginfo->ofs));
 320                 return;
 321         }
 322
 323         for (i = 0; i < 8; i++) {
 324                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 325                 pr_err("%-15s", rname);
 326                 for (j = 0; j < 8; j++)
 327                         pr_cont(" %08x", regs[i*8+j]);
 328                 pr_cont("\n");
 329         }
 330
 331 }
 332
 333 /*
 334  * ixgbe_dump - Print registers, tx-rings and rx-rings
 335  */
 336 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 337 {
 338         struct net_device *netdev = adapter->netdev;
 339         struct ixgbe_hw *hw = &adapter->hw;
 340         struct ixgbe_reg_info *reginfo;
 341         int n = 0;
 342         struct ixgbe_ring *tx_ring;
 343         struct ixgbe_tx_buffer *tx_buffer_info;
 344         union ixgbe_adv_tx_desc *tx_desc;
 345         struct my_u0 { u64 a; u64 b; } *u0;
 346         struct ixgbe_ring *rx_ring;
 347         union ixgbe_adv_rx_desc *rx_desc;
 348         struct ixgbe_rx_buffer *rx_buffer_info;
 349         u32 staterr;
 350         int i = 0;
 351
 352         if (!netif_msg_hw(adapter))
 353                 return;
 354
 355         /* Print netdevice Info */
 356         if (netdev) {
 357                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 358                 pr_info("Device Name     state            "
 359                         "trans_start      last_rx\n");
 360                 pr_info("%-15s %016lX %016lX %016lX\n",
 361                         netdev->name,
 362                         netdev->state,
 363                         netdev->trans_start,
 364                         netdev->last_rx);
 365         }
 366
 367         /* Print Registers */
 368         dev_info(&adapter->pdev->dev, "Register Dump\n");
 369         pr_info(" Register Name   Value\n");
 370         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 371              reginfo->name; reginfo++) {
 372                 ixgbe_regdump(hw, reginfo);
 373         }
 374
 375         /* Print TX Ring Summary */
 376         if (!netdev || !netif_running(netdev))
 377                 goto exit;
 378
 379         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 380         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 381         for (n = 0; n < adapter->num_tx_queues; n++) {
 382                 tx_ring = adapter->tx_ring[n];
 383                 tx_buffer_info =
 384                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 385                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 386                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 387                            (u64)tx_buffer_info->dma,
 388                            tx_buffer_info->length,
 389                            tx_buffer_info->next_to_watch,
 390                            (u64)tx_buffer_info->time_stamp);
 391         }
 392
 393         /* Print TX Rings */
 394         if (!netif_msg_tx_done(adapter))
 395                 goto rx_ring_summary;
 396
 397         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 398
 399         /* Transmit Descriptor Formats
 400          *
 401          * Advanced Transmit Descriptor
 402          *   +--------------------------------------------------------------+
 403          * 0 |         Buffer Address [63:0]                                |
 404          *   +--------------------------------------------------------------+
 405          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 406          *   +--------------------------------------------------------------+
 407          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 408          */
 409
 410         for (n = 0; n < adapter->num_tx_queues; n++) {
 411                 tx_ring = adapter->tx_ring[n];
 412                 pr_info("------------------------------------\n");
 413                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 414                 pr_info("------------------------------------\n");
 415                 pr_info("T [desc]     [address 63:0  ] "
 416                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 417                         "leng  ntw timestamp        bi->skb\n");
 418
 419                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 420                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 421                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 422                         u0 = (struct my_u0 *)tx_desc;
 423                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 424                                 " %04X  %3X %016llX %p", i,
 425                                 le64_to_cpu(u0->a),
 426                                 le64_to_cpu(u0->b),
 427                                 (u64)tx_buffer_info->dma,
 428                                 tx_buffer_info->length,
 429                                 tx_buffer_info->next_to_watch,
 430                                 (u64)tx_buffer_info->time_stamp,
 431                                 tx_buffer_info->skb);
 432                         if (i == tx_ring->next_to_use &&
 433                                 i == tx_ring->next_to_clean)
 434                                 pr_cont(" NTC/U\n");
 435                         else if (i == tx_ring->next_to_use)
 436                                 pr_cont(" NTU\n");
 437                         else if (i == tx_ring->next_to_clean)
 438                                 pr_cont(" NTC\n");
 439                         else
 440                                 pr_cont("\n");
 441
 442                         if (netif_msg_pktdata(adapter) &&
 443                                 tx_buffer_info->dma != 0)
 444                                 print_hex_dump(KERN_INFO, "",
 445                                         DUMP_PREFIX_ADDRESS, 16, 1,
 446                                         phys_to_virt(tx_buffer_info->dma),
 447                                         tx_buffer_info->length, true);
 448                 }
 449         }
 450
 451         /* Print RX Rings Summary */
 452 rx_ring_summary:
 453         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 454         pr_info("Queue [NTU] [NTC]\n");
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 pr_info("%5d %5X %5X\n",
 458                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 459         }
 460
 461         /* Print RX Rings */
 462         if (!netif_msg_rx_status(adapter))
 463                 goto exit;
 464
 465         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 466
 467         /* Advanced Receive Descriptor (Read) Format
 468          *    63                                           1        0
 469          *    +-----------------------------------------------------+
 470          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 471          *    +----------------------------------------------+------+
 472          *  8 |       Header Buffer Address [63:1]           |  DD  |
 473          *    +-----------------------------------------------------+
 474          *
 475          *
 476          * Advanced Receive Descriptor (Write-Back) Format
 477          *
 478          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 479          *   +------------------------------------------------------+
 480          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 481          *   | Checksum   Ident  |   |           |    | Type | Type |
 482          *   +------------------------------------------------------+
 483          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 484          *   +------------------------------------------------------+
 485          *   63       48 47    32 31            20 19               0
 486          */
 487         for (n = 0; n < adapter->num_rx_queues; n++) {
 488                 rx_ring = adapter->rx_ring[n];
 489                 pr_info("------------------------------------\n");
 490                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 491                 pr_info("------------------------------------\n");
 492                 pr_info("R  [desc]      [ PktBuf     A0] "
 493                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 494                         "<-- Adv Rx Read format\n");
 495                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 496                         "[vl er S cks ln] ---------------- [bi->skb] "
 497                         "<-- Adv Rx Write-Back format\n");
 498
 499                 for (i = 0; i < rx_ring->count; i++) {
 500                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 501                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 502                         u0 = (struct my_u0 *)rx_desc;
 503                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 504                         if (staterr & IXGBE_RXD_STAT_DD) {
 505                                 /* Descriptor Done */
 506                                 pr_info("RWB[0x%03X]     %016llX "
 507                                         "%016llX ---------------- %p", i,
 508                                         le64_to_cpu(u0->a),
 509                                         le64_to_cpu(u0->b),
 510                                         rx_buffer_info->skb);
 511                         } else {
 512                                 pr_info("R  [0x%03X]     %016llX "
 513                                         "%016llX %016llX %p", i,
 514                                         le64_to_cpu(u0->a),
 515                                         le64_to_cpu(u0->b),
 516                                         (u64)rx_buffer_info->dma,
 517                                         rx_buffer_info->skb);
 518
 519                                 if (netif_msg_pktdata(adapter)) {
 520                                         print_hex_dump(KERN_INFO, "",
 521                                            DUMP_PREFIX_ADDRESS, 16, 1,
 522                                            phys_to_virt(rx_buffer_info->dma),
 523                                            rx_ring->rx_buf_len, true);
 524
 525                                         if (rx_ring->rx_buf_len
 526                                                 < IXGBE_RXBUFFER_2048)
 527                                                 print_hex_dump(KERN_INFO, "",
 528                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 529                                                   phys_to_virt(
 530                                                     rx_buffer_info->page_dma +
 531                                                     rx_buffer_info->page_offset
 532                                                   ),
 533                                                   PAGE_SIZE/2, true);
 534                                 }
 535                         }
 536
 537                         if (i == rx_ring->next_to_use)
 538                                 pr_cont(" NTU\n");
 539                         else if (i == rx_ring->next_to_clean)
 540                                 pr_cont(" NTC\n");
 541                         else
 542                                 pr_cont("\n");
 543
 544                 }
 545         }
 546
 547 exit:
 548         return;
 549 }
 550
 551 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 552 {
 553         u32 ctrl_ext;
 554
 555         /* Let firmware take over control of h/w */
 556         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 557         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 558                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 559 }
 560
 561 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 562 {
 563         u32 ctrl_ext;
 564
 565         /* Let firmware know the driver has taken over */
 566         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 567         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 568                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 569 }
 570
 571 /*
 572  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 573  * @adapter: pointer to adapter struct
 574  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 575  * @queue: queue to map the corresponding interrupt to
 576  * @msix_vector: the vector to map to the corresponding queue
 577  *
 578  */
 579 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 580                            u8 queue, u8 msix_vector)
 581 {
 582         u32 ivar, index;
 583         struct ixgbe_hw *hw = &adapter->hw;
 584         switch (hw->mac.type) {
 585         case ixgbe_mac_82598EB:
 586                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 587                 if (direction == -1)
 588                         direction = 0;
 589                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 590                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 591                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 592                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 593                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 594                 break;
 595         case ixgbe_mac_82599EB:
 596         case ixgbe_mac_X540:
 597                 if (direction == -1) {
 598                         /* other causes */
 599                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 600                         index = ((queue & 1) * 8);
 601                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 602                         ivar &= ~(0xFF << index);
 603                         ivar |= (msix_vector << index);
 604                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 605                         break;
 606                 } else {
 607                         /* tx or rx causes */
 608                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 609                         index = ((16 * (queue & 1)) + (8 * direction));
 610                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 611                         ivar &= ~(0xFF << index);
 612                         ivar |= (msix_vector << index);
 613                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 614                         break;
 615                 }
 616         default:
 617                 break;
 618         }
 619 }
 620
 621 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 622                                           u64 qmask)
 623 {
 624         u32 mask;
 625
 626         switch (adapter->hw.mac.type) {
 627         case ixgbe_mac_82598EB:
 628                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 629                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 630                 break;
 631         case ixgbe_mac_82599EB:
 632         case ixgbe_mac_X540:
 633                 mask = (qmask & 0xFFFFFFFF);
 634                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 635                 mask = (qmask >> 32);
 636                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 637                 break;
 638         default:
 639                 break;
 640         }
 641 }
 642
 643 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 644                                       struct ixgbe_tx_buffer *tx_buffer_info)
 645 {
 646         if (tx_buffer_info->dma) {
 647                 if (tx_buffer_info->mapped_as_page)
 648                         dma_unmap_page(tx_ring->dev,
 649                                        tx_buffer_info->dma,
 650                                        tx_buffer_info->length,
 651                                        DMA_TO_DEVICE);
 652                 else
 653                         dma_unmap_single(tx_ring->dev,
 654                                          tx_buffer_info->dma,
 655                                          tx_buffer_info->length,
 656                                          DMA_TO_DEVICE);
 657                 tx_buffer_info->dma = 0;
 658         }
 659         if (tx_buffer_info->skb) {
 660                 dev_kfree_skb_any(tx_buffer_info->skb);
 661                 tx_buffer_info->skb = NULL;
 662         }
 663         tx_buffer_info->time_stamp = 0;
 664         /* tx_buffer_info must be completely set up in the transmit path */
 665 }
 666
 667 /**
 668  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 669  * @adapter: driver private struct
 670  * @index: reg idx of queue to query (0-127)
 671  *
 672  * Helper function to determine the traffic index for a particular
 673  * register index.
 674  *
 675  * Returns : a tc index for use in range 0-7, or 0-3
 676  */
 677 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 678 {
 679         int tc = -1;
 680         int dcb_i = netdev_get_num_tc(adapter->netdev);
 681
 682         /* if DCB is not enabled the queues have no TC */
 683         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 684                 return tc;
 685
 686         /* check valid range */
 687         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 688                 return tc;
 689
 690         switch (adapter->hw.mac.type) {
 691         case ixgbe_mac_82598EB:
 692                 tc = reg_idx >> 2;
 693                 break;
 694         default:
 695                 if (dcb_i != 4 && dcb_i != 8)
 696                         break;
 697
 698                 /* if VMDq is enabled the lowest order bits determine TC */
 699                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 700                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 701                         tc = reg_idx & (dcb_i - 1);
 702                         break;
 703                 }
 704
 705                 /*
 706                  * Convert the reg_idx into the correct TC. This bitmask
 707                  * targets the last full 32 ring traffic class and assigns
 708                  * it a value of 1. From there the rest of the rings are
 709                  * based on shifting the mask further up to include the
 710                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 711                  * will only ever be 8 or 4 and that reg_idx will never
 712                  * be greater then 128. The code without the power of 2
 713                  * optimizations would be:
 714                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 715                  */
 716                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 717                 tc >>= 9 - (reg_idx >> 5);
 718         }
 719
 720         return tc;
 721 }
 722
 723 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 724 {
 725         struct ixgbe_hw *hw = &adapter->hw;
 726         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 727         u32 data = 0;
 728         u32 xoff[8] = {0};
 729         int i;
 730
 731         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 732             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 733                 switch (hw->mac.type) {
 734                 case ixgbe_mac_82598EB:
 735                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 736                         break;
 737                 default:
 738                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 739                 }
 740                 hwstats->lxoffrxc += data;
 741
 742                 /* refill credits (no tx hang) if we received xoff */
 743                 if (!data)
 744                         return;
 745
 746                 for (i = 0; i < adapter->num_tx_queues; i++)
 747                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 748                                   &adapter->tx_ring[i]->state);
 749                 return;
 750         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 751                 return;
 752
 753         /* update stats for each tc, only valid with PFC enabled */
 754         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 755                 switch (hw->mac.type) {
 756                 case ixgbe_mac_82598EB:
 757                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 758                         break;
 759                 default:
 760                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 761                 }
 762                 hwstats->pxoffrxc[i] += xoff[i];
 763         }
 764
 765         /* disarm tx queues that have received xoff frames */
 766         for (i = 0; i < adapter->num_tx_queues; i++) {
 767                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 768                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 769
 770                 if (xoff[tc])
 771                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 772         }
 773 }
 774
 775 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 776 {
 777         return ring->tx_stats.completed;
 778 }
 779
 780 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 781 {
 782         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 783         struct ixgbe_hw *hw = &adapter->hw;
 784
 785         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 786         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 787
 788         if (head != tail)
 789                 return (head < tail) ?
 790                         tail - head : (tail + ring->count - head);
 791
 792         return 0;
 793 }
 794
 795 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 796 {
 797         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 798         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 799         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 800         bool ret = false;
 801
 802         clear_check_for_tx_hang(tx_ring);
 803
 804         /*
 805          * Check for a hung queue, but be thorough. This verifies
 806          * that a transmit has been completed since the previous
 807          * check AND there is at least one packet pending. The
 808          * ARMED bit is set to indicate a potential hang. The
 809          * bit is cleared if a pause frame is received to remove
 810          * false hang detection due to PFC or 802.3x frames. By
 811          * requiring this to fail twice we avoid races with
 812          * pfc clearing the ARMED bit and conditions where we
 813          * run the check_tx_hang logic with a transmit completion
 814          * pending but without time to complete it yet.
 815          */
 816         if ((tx_done_old == tx_done) && tx_pending) {
 817                 /* make sure it is true for two checks in a row */
 818                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 819                                        &tx_ring->state);
 820         } else {
 821                 /* update completed stats and continue */
 822                 tx_ring->tx_stats.tx_done_old = tx_done;
 823                 /* reset the countdown */
 824                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 825         }
 826
 827         return ret;
 828 }
 829
 830 #define IXGBE_MAX_TXD_PWR       14
 831 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 832
 833 /* Tx Descriptors needed, worst case */
 834 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 835                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 836 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 837         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 838
 839 /**
 840  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 841  * @adapter: driver private struct
 842  **/
 843 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 844 {
 845
 846         /* Do the reset outside of interrupt context */
 847         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 848                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 849                 ixgbe_service_event_schedule(adapter);
 850         }
 851 }
 852
 853 /**
 854  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 855  * @q_vector: structure containing interrupt and ring information
 856  * @tx_ring: tx ring to clean
 857  **/
 858 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 859                                struct ixgbe_ring *tx_ring)
 860 {
 861         struct ixgbe_adapter *adapter = q_vector->adapter;
 862         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 863         struct ixgbe_tx_buffer *tx_buffer_info;
 864         unsigned int total_bytes = 0, total_packets = 0;
 865         u16 i, eop, count = 0;
 866
 867         i = tx_ring->next_to_clean;
 868         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 869         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 870
 871         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 872                (count < tx_ring->work_limit)) {
 873                 bool cleaned = false;
 874                 rmb(); /* read buffer_info after eop_desc */
 875                 for ( ; !cleaned; count++) {
 876                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 877                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 878
 879                         tx_desc->wb.status = 0;
 880                         cleaned = (i == eop);
 881
 882                         i++;
 883                         if (i == tx_ring->count)
 884                                 i = 0;
 885
 886                         if (cleaned && tx_buffer_info->skb) {
 887                                 total_bytes += tx_buffer_info->bytecount;
 888                                 total_packets += tx_buffer_info->gso_segs;
 889                         }
 890
 891                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 892                                                          tx_buffer_info);
 893                 }
 894
 895                 tx_ring->tx_stats.completed++;
 896                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 897                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 898         }
 899
 900         tx_ring->next_to_clean = i;
 901         tx_ring->total_bytes += total_bytes;
 902         tx_ring->total_packets += total_packets;
 903         u64_stats_update_begin(&tx_ring->syncp);
 904         tx_ring->stats.packets += total_packets;
 905         tx_ring->stats.bytes += total_bytes;
 906         u64_stats_update_end(&tx_ring->syncp);
 907
 908         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 909                 /* schedule immediate reset if we believe we hung */
 910                 struct ixgbe_hw *hw = &adapter->hw;
 911                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 912                 e_err(drv, "Detected Tx Unit Hang\n"
 913                         "  Tx Queue             <%d>\n"
 914                         "  TDH, TDT             <%x>, <%x>\n"
 915                         "  next_to_use          <%x>\n"
 916                         "  next_to_clean        <%x>\n"
 917                         "tx_buffer_info[next_to_clean]\n"
 918                         "  time_stamp           <%lx>\n"
 919                         "  jiffies              <%lx>\n",
 920                         tx_ring->queue_index,
 921                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 922                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 923                         tx_ring->next_to_use, eop,
 924                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 925
 926                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 927
 928                 e_info(probe,
 929                        "tx hang %d detected on queue %d, resetting adapter\n",
 930                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 931
 932                 /* schedule immediate reset if we believe we hung */
 933                 ixgbe_tx_timeout_reset(adapter);
 934
 935                 /* the adapter is about to reset, no point in enabling stuff */
 936                 return true;
 937         }
 938
 939 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 940         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 941                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 942                 /* Make sure that anybody stopping the queue after this
 943                  * sees the new next_to_clean.
 944                  */
 945                 smp_mb();
 946                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 947                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 948                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 949                         ++tx_ring->tx_stats.restart_queue;
 950                 }
 951         }
 952
 953         return count < tx_ring->work_limit;
 954 }
 955
 956 #ifdef CONFIG_IXGBE_DCA
 957 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 958                                 struct ixgbe_ring *rx_ring,
 959                                 int cpu)
 960 {
 961         struct ixgbe_hw *hw = &adapter->hw;
 962         u32 rxctrl;
 963         u8 reg_idx = rx_ring->reg_idx;
 964
 965         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 966         switch (hw->mac.type) {
 967         case ixgbe_mac_82598EB:
 968                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 969                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 970                 break;
 971         case ixgbe_mac_82599EB:
 972         case ixgbe_mac_X540:
 973                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 974                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 975                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 976                 break;
 977         default:
 978                 break;
 979         }
 980         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 981         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 982         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 983         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 984 }
 985
 986 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 987                                 struct ixgbe_ring *tx_ring,
 988                                 int cpu)
 989 {
 990         struct ixgbe_hw *hw = &adapter->hw;
 991         u32 txctrl;
 992         u8 reg_idx = tx_ring->reg_idx;
 993
 994         switch (hw->mac.type) {
 995         case ixgbe_mac_82598EB:
 996                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 997                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 998                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 999                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1000                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
1001                 break;
1002         case ixgbe_mac_82599EB:
1003         case ixgbe_mac_X540:
1004                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1005                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1006                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1007                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1008                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1009                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1010                 break;
1011         default:
1012                 break;
1013         }
1014 }
1015
1016 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1017 {
1018         struct ixgbe_adapter *adapter = q_vector->adapter;
1019         int cpu = get_cpu();
1020         long r_idx;
1021         int i;
1022
1023         if (q_vector->cpu == cpu)
1024                 goto out_no_update;
1025
1026         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1027         for (i = 0; i < q_vector->txr_count; i++) {
1028                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1029                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1030                                       r_idx + 1);
1031         }
1032
1033         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1034         for (i = 0; i < q_vector->rxr_count; i++) {
1035                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1036                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1037                                       r_idx + 1);
1038         }
1039
1040         q_vector->cpu = cpu;
1041 out_no_update:
1042         put_cpu();
1043 }
1044
1045 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1046 {
1047         int num_q_vectors;
1048         int i;
1049
1050         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1051                 return;
1052
1053         /* always use CB2 mode, difference is masked in the CB driver */
1054         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1055
1056         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1057                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1058         else
1059                 num_q_vectors = 1;
1060
1061         for (i = 0; i < num_q_vectors; i++) {
1062                 adapter->q_vector[i]->cpu = -1;
1063                 ixgbe_update_dca(adapter->q_vector[i]);
1064         }
1065 }
1066
1067 static int __ixgbe_notify_dca(struct device *dev, void *data)
1068 {
1069         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1070         unsigned long event = *(unsigned long *)data;
1071
1072         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1073                 return 0;
1074
1075         switch (event) {
1076         case DCA_PROVIDER_ADD:
1077                 /* if we're already enabled, don't do it again */
1078                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1079                         break;
1080                 if (dca_add_requester(dev) == 0) {
1081                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1082                         ixgbe_setup_dca(adapter);
1083                         break;
1084                 }
1085                 /* Fall Through since DCA is disabled. */
1086         case DCA_PROVIDER_REMOVE:
1087                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1088                         dca_remove_requester(dev);
1089                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1090                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1091                 }
1092                 break;
1093         }
1094
1095         return 0;
1096 }
1097 #endif /* CONFIG_IXGBE_DCA */
1098
1099 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1100                                  struct sk_buff *skb)
1101 {
1102         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1103 }
1104
1105 /**
1106  * ixgbe_receive_skb - Send a completed packet up the stack
1107  * @adapter: board private structure
1108  * @skb: packet to send up
1109  * @status: hardware indication of status of receive
1110  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1111  * @rx_desc: rx descriptor
1112  **/
1113 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1114                               struct sk_buff *skb, u8 status,
1115                               struct ixgbe_ring *ring,
1116                               union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         struct ixgbe_adapter *adapter = q_vector->adapter;
1119         struct napi_struct *napi = &q_vector->napi;
1120         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1121         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1122
1123         if (is_vlan && (tag & VLAN_VID_MASK))
1124                 __vlan_hwaccel_put_tag(skb, tag);
1125
1126         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1127                 napi_gro_receive(napi, skb);
1128         else
1129                 netif_rx(skb);
1130 }
1131
1132 /**
1133  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1134  * @adapter: address of board private structure
1135  * @status_err: hardware indication of status of receive
1136  * @skb: skb currently being received and modified
1137  **/
1138 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1139                                      union ixgbe_adv_rx_desc *rx_desc,
1140                                      struct sk_buff *skb)
1141 {
1142         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1143
1144         skb_checksum_none_assert(skb);
1145
1146         /* Rx csum disabled */
1147         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1148                 return;
1149
1150         /* if IP and error */
1151         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1152             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1153                 adapter->hw_csum_rx_error++;
1154                 return;
1155         }
1156
1157         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1158                 return;
1159
1160         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1161                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1162
1163                 /*
1164                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1165                  * checksum errors.
1166                  */
1167                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1168                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1169                         return;
1170
1171                 adapter->hw_csum_rx_error++;
1172                 return;
1173         }
1174
1175         /* It must be a TCP or UDP packet with a valid checksum */
1176         skb->ip_summed = CHECKSUM_UNNECESSARY;
1177 }
1178
1179 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1180 {
1181         /*
1182          * Force memory writes to complete before letting h/w
1183          * know there are new descriptors to fetch.  (Only
1184          * applicable for weak-ordered memory model archs,
1185          * such as IA-64).
1186          */
1187         wmb();
1188         writel(val, rx_ring->tail);
1189 }
1190
1191 /**
1192  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1193  * @rx_ring: ring to place buffers on
1194  * @cleaned_count: number of buffers to replace
1195  **/
1196 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1197 {
1198         union ixgbe_adv_rx_desc *rx_desc;
1199         struct ixgbe_rx_buffer *bi;
1200         struct sk_buff *skb;
1201         u16 i = rx_ring->next_to_use;
1202
1203         /* do nothing if no valid netdev defined */
1204         if (!rx_ring->netdev)
1205                 return;
1206
1207         while (cleaned_count--) {
1208                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1209                 bi = &rx_ring->rx_buffer_info[i];
1210                 skb = bi->skb;
1211
1212                 if (!skb) {
1213                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1214                                                         rx_ring->rx_buf_len);
1215                         if (!skb) {
1216                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1217                                 goto no_buffers;
1218                         }
1219                         /* initialize queue mapping */
1220                         skb_record_rx_queue(skb, rx_ring->queue_index);
1221                         bi->skb = skb;
1222                 }
1223
1224                 if (!bi->dma) {
1225                         bi->dma = dma_map_single(rx_ring->dev,
1226                                                  skb->data,
1227                                                  rx_ring->rx_buf_len,
1228                                                  DMA_FROM_DEVICE);
1229                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1230                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1231                                 bi->dma = 0;
1232                                 goto no_buffers;
1233                         }
1234                 }
1235
1236                 if (ring_is_ps_enabled(rx_ring)) {
1237                         if (!bi->page) {
1238                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1239                                 if (!bi->page) {
1240                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1241                                         goto no_buffers;
1242                                 }
1243                         }
1244
1245                         if (!bi->page_dma) {
1246                                 /* use a half page if we're re-using */
1247                                 bi->page_offset ^= PAGE_SIZE / 2;
1248                                 bi->page_dma = dma_map_page(rx_ring->dev,
1249                                                             bi->page,
1250                                                             bi->page_offset,
1251                                                             PAGE_SIZE / 2,
1252                                                             DMA_FROM_DEVICE);
1253                                 if (dma_mapping_error(rx_ring->dev,
1254                                                       bi->page_dma)) {
1255                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1256                                         bi->page_dma = 0;
1257                                         goto no_buffers;
1258                                 }
1259                         }
1260
1261                         /* Refresh the desc even if buffer_addrs didn't change
1262                          * because each write-back erases this info. */
1263                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1264                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1265                 } else {
1266                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1267                         rx_desc->read.hdr_addr = 0;
1268                 }
1269
1270                 i++;
1271                 if (i == rx_ring->count)
1272                         i = 0;
1273         }
1274
1275 no_buffers:
1276         if (rx_ring->next_to_use != i) {
1277                 rx_ring->next_to_use = i;
1278                 ixgbe_release_rx_desc(rx_ring, i);
1279         }
1280 }
1281
1282 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1283 {
1284         /* HW will not DMA in data larger than the given buffer, even if it
1285          * parses the (NFS, of course) header to be larger.  In that case, it
1286          * fills the header buffer and spills the rest into the page.
1287          */
1288         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1289         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1290                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1291         if (hlen > IXGBE_RX_HDR_SIZE)
1292                 hlen = IXGBE_RX_HDR_SIZE;
1293         return hlen;
1294 }
1295
1296 /**
1297  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1298  * @skb: pointer to the last skb in the rsc queue
1299  *
1300  * This function changes a queue full of hw rsc buffers into a completed
1301  * packet.  It uses the ->prev pointers to find the first packet and then
1302  * turns it into the frag list owner.
1303  **/
1304 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1305 {
1306         unsigned int frag_list_size = 0;
1307         unsigned int skb_cnt = 1;
1308
1309         while (skb->prev) {
1310                 struct sk_buff *prev = skb->prev;
1311                 frag_list_size += skb->len;
1312                 skb->prev = NULL;
1313                 skb = prev;
1314                 skb_cnt++;
1315         }
1316
1317         skb_shinfo(skb)->frag_list = skb->next;
1318         skb->next = NULL;
1319         skb->len += frag_list_size;
1320         skb->data_len += frag_list_size;
1321         skb->truesize += frag_list_size;
1322         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1323
1324         return skb;
1325 }
1326
1327 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1328 {
1329         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1330                 IXGBE_RXDADV_RSCCNT_MASK);
1331 }
1332
1333 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1334                                struct ixgbe_ring *rx_ring,
1335                                int *work_done, int work_to_do)
1336 {
1337         struct ixgbe_adapter *adapter = q_vector->adapter;
1338         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1339         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1340         struct sk_buff *skb;
1341         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1342         const int current_node = numa_node_id();
1343 #ifdef IXGBE_FCOE
1344         int ddp_bytes = 0;
1345 #endif /* IXGBE_FCOE */
1346         u32 staterr;
1347         u16 i;
1348         u16 cleaned_count = 0;
1349         bool pkt_is_rsc = false;
1350
1351         i = rx_ring->next_to_clean;
1352         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1353         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1354
1355         while (staterr & IXGBE_RXD_STAT_DD) {
1356                 u32 upper_len = 0;
1357
1358                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1359
1360                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1361
1362                 skb = rx_buffer_info->skb;
1363                 rx_buffer_info->skb = NULL;
1364                 prefetch(skb->data);
1365
1366                 if (ring_is_rsc_enabled(rx_ring))
1367                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1368
1369                 /* linear means we are building an skb from multiple pages */
1370                 if (!skb_is_nonlinear(skb)) {
1371                         u16 hlen;
1372                         if (pkt_is_rsc &&
1373                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1374                             !skb->prev) {
1375                                 /*
1376                                  * When HWRSC is enabled, delay unmapping
1377                                  * of the first packet. It carries the
1378                                  * header information, HW may still
1379                                  * access the header after the writeback.
1380                                  * Only unmap it when EOP is reached
1381                                  */
1382                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1383                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1384                         } else {
1385                                 dma_unmap_single(rx_ring->dev,
1386                                                  rx_buffer_info->dma,
1387                                                  rx_ring->rx_buf_len,
1388                                                  DMA_FROM_DEVICE);
1389                         }
1390                         rx_buffer_info->dma = 0;
1391
1392                         if (ring_is_ps_enabled(rx_ring)) {
1393                                 hlen = ixgbe_get_hlen(rx_desc);
1394                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1395                         } else {
1396                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1397                         }
1398
1399                         skb_put(skb, hlen);
1400                 } else {
1401                         /* assume packet split since header is unmapped */
1402                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1403                 }
1404
1405                 if (upper_len) {
1406                         dma_unmap_page(rx_ring->dev,
1407                                        rx_buffer_info->page_dma,
1408                                        PAGE_SIZE / 2,
1409                                        DMA_FROM_DEVICE);
1410                         rx_buffer_info->page_dma = 0;
1411                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1412                                            rx_buffer_info->page,
1413                                            rx_buffer_info->page_offset,
1414                                            upper_len);
1415
1416                         if ((page_count(rx_buffer_info->page) == 1) &&
1417                             (page_to_nid(rx_buffer_info->page) == current_node))
1418                                 get_page(rx_buffer_info->page);
1419                         else
1420                                 rx_buffer_info->page = NULL;
1421
1422                         skb->len += upper_len;
1423                         skb->data_len += upper_len;
1424                         skb->truesize += upper_len;
1425                 }
1426
1427                 i++;
1428                 if (i == rx_ring->count)
1429                         i = 0;
1430
1431                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1432                 prefetch(next_rxd);
1433                 cleaned_count++;
1434
1435                 if (pkt_is_rsc) {
1436                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1437                                      IXGBE_RXDADV_NEXTP_SHIFT;
1438                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1439                 } else {
1440                         next_buffer = &rx_ring->rx_buffer_info[i];
1441                 }
1442
1443                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1444                         if (ring_is_ps_enabled(rx_ring)) {
1445                                 rx_buffer_info->skb = next_buffer->skb;
1446                                 rx_buffer_info->dma = next_buffer->dma;
1447                                 next_buffer->skb = skb;
1448                                 next_buffer->dma = 0;
1449                         } else {
1450                                 skb->next = next_buffer->skb;
1451                                 skb->next->prev = skb;
1452                         }
1453                         rx_ring->rx_stats.non_eop_descs++;
1454                         goto next_desc;
1455                 }
1456
1457                 if (skb->prev) {
1458                         skb = ixgbe_transform_rsc_queue(skb);
1459                         /* if we got here without RSC the packet is invalid */
1460                         if (!pkt_is_rsc) {
1461                                 __pskb_trim(skb, 0);
1462                                 rx_buffer_info->skb = skb;
1463                                 goto next_desc;
1464                         }
1465                 }
1466
1467                 if (ring_is_rsc_enabled(rx_ring)) {
1468                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1469                                 dma_unmap_single(rx_ring->dev,
1470                                                  IXGBE_RSC_CB(skb)->dma,
1471                                                  rx_ring->rx_buf_len,
1472                                                  DMA_FROM_DEVICE);
1473                                 IXGBE_RSC_CB(skb)->dma = 0;
1474                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1475                         }
1476                 }
1477                 if (pkt_is_rsc) {
1478                         if (ring_is_ps_enabled(rx_ring))
1479                                 rx_ring->rx_stats.rsc_count +=
1480                                         skb_shinfo(skb)->nr_frags;
1481                         else
1482                                 rx_ring->rx_stats.rsc_count +=
1483                                         IXGBE_RSC_CB(skb)->skb_cnt;
1484                         rx_ring->rx_stats.rsc_flush++;
1485                 }
1486
1487                 /* ERR_MASK will only have valid bits if EOP set */
1488                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1489                         /* trim packet back to size 0 and recycle it */
1490                         __pskb_trim(skb, 0);
1491                         rx_buffer_info->skb = skb;
1492                         goto next_desc;
1493                 }
1494
1495                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1496                 if (adapter->netdev->features & NETIF_F_RXHASH)
1497                         ixgbe_rx_hash(rx_desc, skb);
1498
1499                 /* probably a little skewed due to removing CRC */
1500                 total_rx_bytes += skb->len;
1501                 total_rx_packets++;
1502
1503                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1504 #ifdef IXGBE_FCOE
1505                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1506                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1507                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1508                         if (!ddp_bytes)
1509                                 goto next_desc;
1510                 }
1511 #endif /* IXGBE_FCOE */
1512                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1513
1514 next_desc:
1515                 rx_desc->wb.upper.status_error = 0;
1516
1517                 (*work_done)++;
1518                 if (*work_done >= work_to_do)
1519                         break;
1520
1521                 /* return some buffers to hardware, one at a time is too slow */
1522                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1523                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1524                         cleaned_count = 0;
1525                 }
1526
1527                 /* use prefetched values */
1528                 rx_desc = next_rxd;
1529                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1530         }
1531
1532         rx_ring->next_to_clean = i;
1533         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1534
1535         if (cleaned_count)
1536                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1537
1538 #ifdef IXGBE_FCOE
1539         /* include DDPed FCoE data */
1540         if (ddp_bytes > 0) {
1541                 unsigned int mss;
1542
1543                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1544                         sizeof(struct fc_frame_header) -
1545                         sizeof(struct fcoe_crc_eof);
1546                 if (mss > 512)
1547                         mss &= ~511;
1548                 total_rx_bytes += ddp_bytes;
1549                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1550         }
1551 #endif /* IXGBE_FCOE */
1552
1553         rx_ring->total_packets += total_rx_packets;
1554         rx_ring->total_bytes += total_rx_bytes;
1555         u64_stats_update_begin(&rx_ring->syncp);
1556         rx_ring->stats.packets += total_rx_packets;
1557         rx_ring->stats.bytes += total_rx_bytes;
1558         u64_stats_update_end(&rx_ring->syncp);
1559 }
1560
1561 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1562 /**
1563  * ixgbe_configure_msix - Configure MSI-X hardware
1564  * @adapter: board private structure
1565  *
1566  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1567  * interrupts.
1568  **/
1569 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1570 {
1571         struct ixgbe_q_vector *q_vector;
1572         int i, q_vectors, v_idx, r_idx;
1573         u32 mask;
1574
1575         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1576
1577         /*
1578          * Populate the IVAR table and set the ITR values to the
1579          * corresponding register.
1580          */
1581         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1582                 q_vector = adapter->q_vector[v_idx];
1583                 /* XXX for_each_set_bit(...) */
1584                 r_idx = find_first_bit(q_vector->rxr_idx,
1585                                        adapter->num_rx_queues);
1586
1587                 for (i = 0; i < q_vector->rxr_count; i++) {
1588                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1589                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1590                         r_idx = find_next_bit(q_vector->rxr_idx,
1591                                               adapter->num_rx_queues,
1592                                               r_idx + 1);
1593                 }
1594                 r_idx = find_first_bit(q_vector->txr_idx,
1595                                        adapter->num_tx_queues);
1596
1597                 for (i = 0; i < q_vector->txr_count; i++) {
1598                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1599                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1600                         r_idx = find_next_bit(q_vector->txr_idx,
1601                                               adapter->num_tx_queues,
1602                                               r_idx + 1);
1603                 }
1604
1605                 if (q_vector->txr_count && !q_vector->rxr_count)
1606                         /* tx only */
1607                         q_vector->eitr = adapter->tx_eitr_param;
1608                 else if (q_vector->rxr_count)
1609                         /* rx or mixed */
1610                         q_vector->eitr = adapter->rx_eitr_param;
1611
1612                 ixgbe_write_eitr(q_vector);
1613                 /* If Flow Director is enabled, set interrupt affinity */
1614                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1615                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1616                         /*
1617                          * Allocate the affinity_hint cpumask, assign the mask
1618                          * for this vector, and set our affinity_hint for
1619                          * this irq.
1620                          */
1621                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1622                                                GFP_KERNEL))
1623                                 return;
1624                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1625                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1626                                               q_vector->affinity_mask);
1627                 }
1628         }
1629
1630         switch (adapter->hw.mac.type) {
1631         case ixgbe_mac_82598EB:
1632                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1633                                v_idx);
1634                 break;
1635         case ixgbe_mac_82599EB:
1636         case ixgbe_mac_X540:
1637                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1638                 break;
1639
1640         default:
1641                 break;
1642         }
1643         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1644
1645         /* set up to autoclear timer, and the vectors */
1646         mask = IXGBE_EIMS_ENABLE_MASK;
1647         if (adapter->num_vfs)
1648                 mask &= ~(IXGBE_EIMS_OTHER |
1649                           IXGBE_EIMS_MAILBOX |
1650                           IXGBE_EIMS_LSC);
1651         else
1652                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1653         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1654 }
1655
1656 enum latency_range {
1657         lowest_latency = 0,
1658         low_latency = 1,
1659         bulk_latency = 2,
1660         latency_invalid = 255
1661 };
1662
1663 /**
1664  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1665  * @adapter: pointer to adapter
1666  * @eitr: eitr setting (ints per sec) to give last timeslice
1667  * @itr_setting: current throttle rate in ints/second
1668  * @packets: the number of packets during this measurement interval
1669  * @bytes: the number of bytes during this measurement interval
1670  *
1671  *      Stores a new ITR value based on packets and byte
1672  *      counts during the last interrupt.  The advantage of per interrupt
1673  *      computation is faster updates and more accurate ITR for the current
1674  *      traffic pattern.  Constants in this function were computed
1675  *      based on theoretical maximum wire speed and thresholds were set based
1676  *      on testing data as well as attempting to minimize response time
1677  *      while increasing bulk throughput.
1678  *      this functionality is controlled by the InterruptThrottleRate module
1679  *      parameter (see ixgbe_param.c)
1680  **/
1681 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1682                            u32 eitr, u8 itr_setting,
1683                            int packets, int bytes)
1684 {
1685         unsigned int retval = itr_setting;
1686         u32 timepassed_us;
1687         u64 bytes_perint;
1688
1689         if (packets == 0)
1690                 goto update_itr_done;
1691
1692
1693         /* simple throttlerate management
1694          *    0-20MB/s lowest (100000 ints/s)
1695          *   20-100MB/s low   (20000 ints/s)
1696          *  100-1249MB/s bulk (8000 ints/s)
1697          */
1698         /* what was last interrupt timeslice? */
1699         timepassed_us = 1000000/eitr;
1700         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1701
1702         switch (itr_setting) {
1703         case lowest_latency:
1704                 if (bytes_perint > adapter->eitr_low)
1705                         retval = low_latency;
1706                 break;
1707         case low_latency:
1708                 if (bytes_perint > adapter->eitr_high)
1709                         retval = bulk_latency;
1710                 else if (bytes_perint <= adapter->eitr_low)
1711                         retval = lowest_latency;
1712                 break;
1713         case bulk_latency:
1714                 if (bytes_perint <= adapter->eitr_high)
1715                         retval = low_latency;
1716                 break;
1717         }
1718
1719 update_itr_done:
1720         return retval;
1721 }
1722
1723 /**
1724  * ixgbe_write_eitr - write EITR register in hardware specific way
1725  * @q_vector: structure containing interrupt and ring information
1726  *
1727  * This function is made to be called by ethtool and by the driver
1728  * when it needs to update EITR registers at runtime.  Hardware
1729  * specific quirks/differences are taken care of here.
1730  */
1731 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1732 {
1733         struct ixgbe_adapter *adapter = q_vector->adapter;
1734         struct ixgbe_hw *hw = &adapter->hw;
1735         int v_idx = q_vector->v_idx;
1736         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1737
1738         switch (adapter->hw.mac.type) {
1739         case ixgbe_mac_82598EB:
1740                 /* must write high and low 16 bits to reset counter */
1741                 itr_reg |= (itr_reg << 16);
1742                 break;
1743         case ixgbe_mac_82599EB:
1744         case ixgbe_mac_X540:
1745                 /*
1746                  * 82599 and X540 can support a value of zero, so allow it for
1747                  * max interrupt rate, but there is an errata where it can
1748                  * not be zero with RSC
1749                  */
1750                 if (itr_reg == 8 &&
1751                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1752                         itr_reg = 0;
1753
1754                 /*
1755                  * set the WDIS bit to not clear the timer bits and cause an
1756                  * immediate assertion of the interrupt
1757                  */
1758                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1759                 break;
1760         default:
1761                 break;
1762         }
1763         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1764 }
1765
1766 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1767 {
1768         struct ixgbe_adapter *adapter = q_vector->adapter;
1769         int i, r_idx;
1770         u32 new_itr;
1771         u8 current_itr, ret_itr;
1772
1773         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1774         for (i = 0; i < q_vector->txr_count; i++) {
1775                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1776                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1777                                            q_vector->tx_itr,
1778                                            tx_ring->total_packets,
1779                                            tx_ring->total_bytes);
1780                 /* if the result for this queue would decrease interrupt
1781                  * rate for this vector then use that result */
1782                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1783                                     q_vector->tx_itr - 1 : ret_itr);
1784                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1785                                       r_idx + 1);
1786         }
1787
1788         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1789         for (i = 0; i < q_vector->rxr_count; i++) {
1790                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1791                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1792                                            q_vector->rx_itr,
1793                                            rx_ring->total_packets,
1794                                            rx_ring->total_bytes);
1795                 /* if the result for this queue would decrease interrupt
1796                  * rate for this vector then use that result */
1797                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1798                                     q_vector->rx_itr - 1 : ret_itr);
1799                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1800                                       r_idx + 1);
1801         }
1802
1803         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1804
1805         switch (current_itr) {
1806         /* counts and packets in update_itr are dependent on these numbers */
1807         case lowest_latency:
1808                 new_itr = 100000;
1809                 break;
1810         case low_latency:
1811                 new_itr = 20000; /* aka hwitr = ~200 */
1812                 break;
1813         case bulk_latency:
1814         default:
1815                 new_itr = 8000;
1816                 break;
1817         }
1818
1819         if (new_itr != q_vector->eitr) {
1820                 /* do an exponential smoothing */
1821                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1822
1823                 /* save the algorithm value here, not the smoothed one */
1824                 q_vector->eitr = new_itr;
1825
1826                 ixgbe_write_eitr(q_vector);
1827         }
1828 }
1829
1830 /**
1831  * ixgbe_check_overtemp_subtask - check for over tempurature
1832  * @adapter: pointer to adapter
1833  **/
1834 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1835 {
1836         struct ixgbe_hw *hw = &adapter->hw;
1837         u32 eicr = adapter->interrupt_event;
1838
1839         if (test_bit(__IXGBE_DOWN, &adapter->state))
1840                 return;
1841
1842         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1843             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1844                 return;
1845
1846         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1847
1848         switch (hw->device_id) {
1849         case IXGBE_DEV_ID_82599_T3_LOM:
1850                 /*
1851                  * Since the warning interrupt is for both ports
1852                  * we don't have to check if:
1853                  *  - This interrupt wasn't for our port.
1854                  *  - We may have missed the interrupt so always have to
1855                  *    check if we  got a LSC
1856                  */
1857                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1858                     !(eicr & IXGBE_EICR_LSC))
1859                         return;
1860
1861                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1862                         u32 autoneg;
1863                         bool link_up = false;
1864
1865                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1866
1867                         if (link_up)
1868                                 return;
1869                 }
1870
1871                 /* Check if this is not due to overtemp */
1872                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1873                         return;
1874
1875                 break;
1876         default:
1877                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1878                         return;
1879                 break;
1880         }
1881         e_crit(drv,
1882                "Network adapter has been stopped because it has over heated. "
1883                "Restart the computer. If the problem persists, "
1884                "power off the system and replace the adapter\n");
1885
1886         adapter->interrupt_event = 0;
1887 }
1888
1889 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1890 {
1891         struct ixgbe_hw *hw = &adapter->hw;
1892
1893         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1894             (eicr & IXGBE_EICR_GPI_SDP1)) {
1895                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1896                 /* write to clear the interrupt */
1897                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1898         }
1899 }
1900
1901 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1902 {
1903         struct ixgbe_hw *hw = &adapter->hw;
1904
1905         if (eicr & IXGBE_EICR_GPI_SDP2) {
1906                 /* Clear the interrupt */
1907                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1908                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1909                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1910                         ixgbe_service_event_schedule(adapter);
1911                 }
1912         }
1913
1914         if (eicr & IXGBE_EICR_GPI_SDP1) {
1915                 /* Clear the interrupt */
1916                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1917                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1918                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1919                         ixgbe_service_event_schedule(adapter);
1920                 }
1921         }
1922 }
1923
1924 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1925 {
1926         struct ixgbe_hw *hw = &adapter->hw;
1927
1928         adapter->lsc_int++;
1929         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1930         adapter->link_check_timeout = jiffies;
1931         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1932                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1933                 IXGBE_WRITE_FLUSH(hw);
1934                 ixgbe_service_event_schedule(adapter);
1935         }
1936 }
1937
1938 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1939 {
1940         struct net_device *netdev = data;
1941         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1942         struct ixgbe_hw *hw = &adapter->hw;
1943         u32 eicr;
1944
1945         /*
1946          * Workaround for Silicon errata.  Use clear-by-write instead
1947          * of clear-by-read.  Reading with EICS will return the
1948          * interrupt causes without clearing, which later be done
1949          * with the write to EICR.
1950          */
1951         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1952         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1953
1954         if (eicr & IXGBE_EICR_LSC)
1955                 ixgbe_check_lsc(adapter);
1956
1957         if (eicr & IXGBE_EICR_MAILBOX)
1958                 ixgbe_msg_task(adapter);
1959
1960         switch (hw->mac.type) {
1961         case ixgbe_mac_82599EB:
1962         case ixgbe_mac_X540:
1963                 /* Handle Flow Director Full threshold interrupt */
1964                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1965                         int reinit_count = 0;
1966                         int i;
1967                         for (i = 0; i < adapter->num_tx_queues; i++) {
1968                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1969                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1970                                                        &ring->state))
1971                                         reinit_count++;
1972                         }
1973                         if (reinit_count) {
1974                                 /* no more flow director interrupts until after init */
1975                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1976                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1977                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1978                                 ixgbe_service_event_schedule(adapter);
1979                         }
1980                 }
1981                 ixgbe_check_sfp_event(adapter, eicr);
1982                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1983                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1984                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1985                                 adapter->interrupt_event = eicr;
1986                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1987                                 ixgbe_service_event_schedule(adapter);
1988                         }
1989                 }
1990                 break;
1991         default:
1992                 break;
1993         }
1994
1995         ixgbe_check_fan_failure(adapter, eicr);
1996
1997         /* re-enable the original interrupt state, no lsc, no queues */
1998         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1999                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
2000                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
2001
2002         return IRQ_HANDLED;
2003 }
2004
2005 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2006                                            u64 qmask)
2007 {
2008         u32 mask;
2009         struct ixgbe_hw *hw = &adapter->hw;
2010
2011         switch (hw->mac.type) {
2012         case ixgbe_mac_82598EB:
2013                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2014                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2015                 break;
2016         case ixgbe_mac_82599EB:
2017         case ixgbe_mac_X540:
2018                 mask = (qmask & 0xFFFFFFFF);
2019                 if (mask)
2020                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2021                 mask = (qmask >> 32);
2022                 if (mask)
2023                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2024                 break;
2025         default:
2026                 break;
2027         }
2028         /* skip the flush */
2029 }
2030
2031 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2032                                             u64 qmask)
2033 {
2034         u32 mask;
2035         struct ixgbe_hw *hw = &adapter->hw;
2036
2037         switch (hw->mac.type) {
2038         case ixgbe_mac_82598EB:
2039                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2040                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2041                 break;
2042         case ixgbe_mac_82599EB:
2043         case ixgbe_mac_X540:
2044                 mask = (qmask & 0xFFFFFFFF);
2045                 if (mask)
2046                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2047                 mask = (qmask >> 32);
2048                 if (mask)
2049                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2050                 break;
2051         default:
2052                 break;
2053         }
2054         /* skip the flush */
2055 }
2056
2057 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2058 {
2059         struct ixgbe_q_vector *q_vector = data;
2060         struct ixgbe_adapter  *adapter = q_vector->adapter;
2061         struct ixgbe_ring     *tx_ring;
2062         int i, r_idx;
2063
2064         if (!q_vector->txr_count)
2065                 return IRQ_HANDLED;
2066
2067         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2068         for (i = 0; i < q_vector->txr_count; i++) {
2069                 tx_ring = adapter->tx_ring[r_idx];
2070                 tx_ring->total_bytes = 0;
2071                 tx_ring->total_packets = 0;
2072                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2073                                       r_idx + 1);
2074         }
2075
2076         /* EIAM disabled interrupts (on this vector) for us */
2077         napi_schedule(&q_vector->napi);
2078
2079         return IRQ_HANDLED;
2080 }
2081
2082 /**
2083  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2084  * @irq: unused
2085  * @data: pointer to our q_vector struct for this interrupt vector
2086  **/
2087 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2088 {
2089         struct ixgbe_q_vector *q_vector = data;
2090         struct ixgbe_adapter  *adapter = q_vector->adapter;
2091         struct ixgbe_ring  *rx_ring;
2092         int r_idx;
2093         int i;
2094
2095 #ifdef CONFIG_IXGBE_DCA
2096         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2097                 ixgbe_update_dca(q_vector);
2098 #endif
2099
2100         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2101         for (i = 0; i < q_vector->rxr_count; i++) {
2102                 rx_ring = adapter->rx_ring[r_idx];
2103                 rx_ring->total_bytes = 0;
2104                 rx_ring->total_packets = 0;
2105                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2106                                       r_idx + 1);
2107         }
2108
2109         if (!q_vector->rxr_count)
2110                 return IRQ_HANDLED;
2111
2112         /* EIAM disabled interrupts (on this vector) for us */
2113         napi_schedule(&q_vector->napi);
2114
2115         return IRQ_HANDLED;
2116 }
2117
2118 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2119 {
2120         struct ixgbe_q_vector *q_vector = data;
2121         struct ixgbe_adapter  *adapter = q_vector->adapter;
2122         struct ixgbe_ring  *ring;
2123         int r_idx;
2124         int i;
2125
2126         if (!q_vector->txr_count && !q_vector->rxr_count)
2127                 return IRQ_HANDLED;
2128
2129         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2130         for (i = 0; i < q_vector->txr_count; i++) {
2131                 ring = adapter->tx_ring[r_idx];
2132                 ring->total_bytes = 0;
2133                 ring->total_packets = 0;
2134                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2135                                       r_idx + 1);
2136         }
2137
2138         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2139         for (i = 0; i < q_vector->rxr_count; i++) {
2140                 ring = adapter->rx_ring[r_idx];
2141                 ring->total_bytes = 0;
2142                 ring->total_packets = 0;
2143                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2144                                       r_idx + 1);
2145         }
2146
2147         /* EIAM disabled interrupts (on this vector) for us */
2148         napi_schedule(&q_vector->napi);
2149
2150         return IRQ_HANDLED;
2151 }
2152
2153 /**
2154  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2155  * @napi: napi struct with our devices info in it
2156  * @budget: amount of work driver is allowed to do this pass, in packets
2157  *
2158  * This function is optimized for cleaning one queue only on a single
2159  * q_vector!!!
2160  **/
2161 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2162 {
2163         struct ixgbe_q_vector *q_vector =
2164                                container_of(napi, struct ixgbe_q_vector, napi);
2165         struct ixgbe_adapter *adapter = q_vector->adapter;
2166         struct ixgbe_ring *rx_ring = NULL;
2167         int work_done = 0;
2168         long r_idx;
2169
2170 #ifdef CONFIG_IXGBE_DCA
2171         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2172                 ixgbe_update_dca(q_vector);
2173 #endif
2174
2175         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2176         rx_ring = adapter->rx_ring[r_idx];
2177
2178         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2179
2180         /* If all Rx work done, exit the polling mode */
2181         if (work_done < budget) {
2182                 napi_complete(napi);
2183                 if (adapter->rx_itr_setting & 1)
2184                         ixgbe_set_itr_msix(q_vector);
2185                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2186                         ixgbe_irq_enable_queues(adapter,
2187                                                 ((u64)1 << q_vector->v_idx));
2188         }
2189
2190         return work_done;
2191 }
2192
2193 /**
2194  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2195  * @napi: napi struct with our devices info in it
2196  * @budget: amount of work driver is allowed to do this pass, in packets
2197  *
2198  * This function will clean more than one rx queue associated with a
2199  * q_vector.
2200  **/
2201 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2202 {
2203         struct ixgbe_q_vector *q_vector =
2204                                container_of(napi, struct ixgbe_q_vector, napi);
2205         struct ixgbe_adapter *adapter = q_vector->adapter;
2206         struct ixgbe_ring *ring = NULL;
2207         int work_done = 0, i;
2208         long r_idx;
2209         bool tx_clean_complete = true;
2210
2211 #ifdef CONFIG_IXGBE_DCA
2212         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2213                 ixgbe_update_dca(q_vector);
2214 #endif
2215
2216         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2217         for (i = 0; i < q_vector->txr_count; i++) {
2218                 ring = adapter->tx_ring[r_idx];
2219                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2220                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2221                                       r_idx + 1);
2222         }
2223
2224         /* attempt to distribute budget to each queue fairly, but don't allow
2225          * the budget to go below 1 because we'll exit polling */
2226         budget /= (q_vector->rxr_count ?: 1);
2227         budget = max(budget, 1);
2228         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2229         for (i = 0; i < q_vector->rxr_count; i++) {
2230                 ring = adapter->rx_ring[r_idx];
2231                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2232                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2233                                       r_idx + 1);
2234         }
2235
2236         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2237         ring = adapter->rx_ring[r_idx];
2238         /* If all Rx work done, exit the polling mode */
2239         if (work_done < budget) {
2240                 napi_complete(napi);
2241                 if (adapter->rx_itr_setting & 1)
2242                         ixgbe_set_itr_msix(q_vector);
2243                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2244                         ixgbe_irq_enable_queues(adapter,
2245                                                 ((u64)1 << q_vector->v_idx));
2246                 return 0;
2247         }
2248
2249         return work_done;
2250 }
2251
2252 /**
2253  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2254  * @napi: napi struct with our devices info in it
2255  * @budget: amount of work driver is allowed to do this pass, in packets
2256  *
2257  * This function is optimized for cleaning one queue only on a single
2258  * q_vector!!!
2259  **/
2260 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2261 {
2262         struct ixgbe_q_vector *q_vector =
2263                                container_of(napi, struct ixgbe_q_vector, napi);
2264         struct ixgbe_adapter *adapter = q_vector->adapter;
2265         struct ixgbe_ring *tx_ring = NULL;
2266         int work_done = 0;
2267         long r_idx;
2268
2269 #ifdef CONFIG_IXGBE_DCA
2270         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2271                 ixgbe_update_dca(q_vector);
2272 #endif
2273
2274         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2275         tx_ring = adapter->tx_ring[r_idx];
2276
2277         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2278                 work_done = budget;
2279
2280         /* If all Tx work done, exit the polling mode */
2281         if (work_done < budget) {
2282                 napi_complete(napi);
2283                 if (adapter->tx_itr_setting & 1)
2284                         ixgbe_set_itr_msix(q_vector);
2285                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2286                         ixgbe_irq_enable_queues(adapter,
2287                                                 ((u64)1 << q_vector->v_idx));
2288         }
2289
2290         return work_done;
2291 }
2292
2293 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2294                                      int r_idx)
2295 {
2296         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2297         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2298
2299         set_bit(r_idx, q_vector->rxr_idx);
2300         q_vector->rxr_count++;
2301         rx_ring->q_vector = q_vector;
2302 }
2303
2304 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2305                                      int t_idx)
2306 {
2307         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2308         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2309
2310         set_bit(t_idx, q_vector->txr_idx);
2311         q_vector->txr_count++;
2312         tx_ring->q_vector = q_vector;
2313 }
2314
2315 /**
2316  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2317  * @adapter: board private structure to initialize
2318  *
2319  * This function maps descriptor rings to the queue-specific vectors
2320  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2321  * one vector per ring/queue, but on a constrained vector budget, we
2322  * group the rings as "efficiently" as possible.  You would add new
2323  * mapping configurations in here.
2324  **/
2325 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2326 {
2327         int q_vectors;
2328         int v_start = 0;
2329         int rxr_idx = 0, txr_idx = 0;
2330         int rxr_remaining = adapter->num_rx_queues;
2331         int txr_remaining = adapter->num_tx_queues;
2332         int i, j;
2333         int rqpv, tqpv;
2334         int err = 0;
2335
2336         /* No mapping required if MSI-X is disabled. */
2337         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2338                 goto out;
2339
2340         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2341
2342         /*
2343          * The ideal configuration...
2344          * We have enough vectors to map one per queue.
2345          */
2346         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2347                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2348                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2349
2350                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2351                         map_vector_to_txq(adapter, v_start, txr_idx);
2352
2353                 goto out;
2354         }
2355
2356         /*
2357          * If we don't have enough vectors for a 1-to-1
2358          * mapping, we'll have to group them so there are
2359          * multiple queues per vector.
2360          */
2361         /* Re-adjusting *qpv takes care of the remainder. */
2362         for (i = v_start; i < q_vectors; i++) {
2363                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2364                 for (j = 0; j < rqpv; j++) {
2365                         map_vector_to_rxq(adapter, i, rxr_idx);
2366                         rxr_idx++;
2367                         rxr_remaining--;
2368                 }
2369                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2370                 for (j = 0; j < tqpv; j++) {
2371                         map_vector_to_txq(adapter, i, txr_idx);
2372                         txr_idx++;
2373                         txr_remaining--;
2374                 }
2375         }
2376 out:
2377         return err;
2378 }
2379
2380 /**
2381  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2382  * @adapter: board private structure
2383  *
2384  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2385  * interrupts from the kernel.
2386  **/
2387 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2388 {
2389         struct net_device *netdev = adapter->netdev;
2390         irqreturn_t (*handler)(int, void *);
2391         int i, vector, q_vectors, err;
2392         int ri = 0, ti = 0;
2393
2394         /* Decrement for Other and TCP Timer vectors */
2395         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2396
2397         err = ixgbe_map_rings_to_vectors(adapter);
2398         if (err)
2399                 return err;
2400
2401 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2402                                           ? &ixgbe_msix_clean_many : \
2403                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2404                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2405                           NULL)
2406         for (vector = 0; vector < q_vectors; vector++) {
2407                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2408                 handler = SET_HANDLER(q_vector);
2409
2410                 if (handler == &ixgbe_msix_clean_rx) {
2411                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2412                                  "%s-%s-%d", netdev->name, "rx", ri++);
2413                 } else if (handler == &ixgbe_msix_clean_tx) {
2414                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2415                                  "%s-%s-%d", netdev->name, "tx", ti++);
2416                 } else if (handler == &ixgbe_msix_clean_many) {
2417                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2418                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2419                         ti++;
2420                 } else {
2421                         /* skip this unused q_vector */
2422                         continue;
2423                 }
2424                 err = request_irq(adapter->msix_entries[vector].vector,
2425                                   handler, 0, q_vector->name,
2426                                   q_vector);
2427                 if (err) {
2428                         e_err(probe, "request_irq failed for MSIX interrupt "
2429                               "Error: %d\n", err);
2430                         goto free_queue_irqs;
2431                 }
2432         }
2433
2434         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2435         err = request_irq(adapter->msix_entries[vector].vector,
2436                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2437         if (err) {
2438                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2439                 goto free_queue_irqs;
2440         }
2441
2442         return 0;
2443
2444 free_queue_irqs:
2445         for (i = vector - 1; i >= 0; i--)
2446                 free_irq(adapter->msix_entries[--vector].vector,
2447                          adapter->q_vector[i]);
2448         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2449         pci_disable_msix(adapter->pdev);
2450         kfree(adapter->msix_entries);
2451         adapter->msix_entries = NULL;
2452         return err;
2453 }
2454
2455 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2456 {
2457         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2458         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2459         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2460         u32 new_itr = q_vector->eitr;
2461         u8 current_itr;
2462
2463         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2464                                             q_vector->tx_itr,
2465                                             tx_ring->total_packets,
2466                                             tx_ring->total_bytes);
2467         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2468                                             q_vector->rx_itr,
2469                                             rx_ring->total_packets,
2470                                             rx_ring->total_bytes);
2471
2472         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2473
2474         switch (current_itr) {
2475         /* counts and packets in update_itr are dependent on these numbers */
2476         case lowest_latency:
2477                 new_itr = 100000;
2478                 break;
2479         case low_latency:
2480                 new_itr = 20000; /* aka hwitr = ~200 */
2481                 break;
2482         case bulk_latency:
2483                 new_itr = 8000;
2484                 break;
2485         default:
2486                 break;
2487         }
2488
2489         if (new_itr != q_vector->eitr) {
2490                 /* do an exponential smoothing */
2491                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2492
2493                 /* save the algorithm value here */
2494                 q_vector->eitr = new_itr;
2495
2496                 ixgbe_write_eitr(q_vector);
2497         }
2498 }
2499
2500 /**
2501  * ixgbe_irq_enable - Enable default interrupt generation settings
2502  * @adapter: board private structure
2503  **/
2504 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2505                                     bool flush)
2506 {
2507         u32 mask;
2508
2509         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2510         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2511                 mask |= IXGBE_EIMS_GPI_SDP0;
2512         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2513                 mask |= IXGBE_EIMS_GPI_SDP1;
2514         switch (adapter->hw.mac.type) {
2515         case ixgbe_mac_82599EB:
2516         case ixgbe_mac_X540:
2517                 mask |= IXGBE_EIMS_ECC;
2518                 mask |= IXGBE_EIMS_GPI_SDP1;
2519                 mask |= IXGBE_EIMS_GPI_SDP2;
2520                 if (adapter->num_vfs)
2521                         mask |= IXGBE_EIMS_MAILBOX;
2522                 break;
2523         default:
2524                 break;
2525         }
2526         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2527             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2528                 mask |= IXGBE_EIMS_FLOW_DIR;
2529
2530         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2531         if (queues)
2532                 ixgbe_irq_enable_queues(adapter, ~0);
2533         if (flush)
2534                 IXGBE_WRITE_FLUSH(&adapter->hw);
2535
2536         if (adapter->num_vfs > 32) {
2537                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2538                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2539         }
2540 }
2541
2542 /**
2543  * ixgbe_intr - legacy mode Interrupt Handler
2544  * @irq: interrupt number
2545  * @data: pointer to a network interface device structure
2546  **/
2547 static irqreturn_t ixgbe_intr(int irq, void *data)
2548 {
2549         struct net_device *netdev = data;
2550         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2551         struct ixgbe_hw *hw = &adapter->hw;
2552         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2553         u32 eicr;
2554
2555         /*
2556          * Workaround for silicon errata on 82598.  Mask the interrupts
2557          * before the read of EICR.
2558          */
2559         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2560
2561         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2562          * therefore no explict interrupt disable is necessary */
2563         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2564         if (!eicr) {
2565                 /*
2566                  * shared interrupt alert!
2567                  * make sure interrupts are enabled because the read will
2568                  * have disabled interrupts due to EIAM
2569                  * finish the workaround of silicon errata on 82598.  Unmask
2570                  * the interrupt that we masked before the EICR read.
2571                  */
2572                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2573                         ixgbe_irq_enable(adapter, true, true);
2574                 return IRQ_NONE;        /* Not our interrupt */
2575         }
2576
2577         if (eicr & IXGBE_EICR_LSC)
2578                 ixgbe_check_lsc(adapter);
2579
2580         switch (hw->mac.type) {
2581         case ixgbe_mac_82599EB:
2582                 ixgbe_check_sfp_event(adapter, eicr);
2583                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2584                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2585                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2586                                 adapter->interrupt_event = eicr;
2587                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2588                                 ixgbe_service_event_schedule(adapter);
2589                         }
2590                 }
2591                 break;
2592         default:
2593                 break;
2594         }
2595
2596         ixgbe_check_fan_failure(adapter, eicr);
2597
2598         if (napi_schedule_prep(&(q_vector->napi))) {
2599                 adapter->tx_ring[0]->total_packets = 0;
2600                 adapter->tx_ring[0]->total_bytes = 0;
2601                 adapter->rx_ring[0]->total_packets = 0;
2602                 adapter->rx_ring[0]->total_bytes = 0;
2603                 /* would disable interrupts here but EIAM disabled it */
2604                 __napi_schedule(&(q_vector->napi));
2605         }
2606
2607         /*
2608          * re-enable link(maybe) and non-queue interrupts, no flush.
2609          * ixgbe_poll will re-enable the queue interrupts
2610          */
2611
2612         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2613                 ixgbe_irq_enable(adapter, false, false);
2614
2615         return IRQ_HANDLED;
2616 }
2617
2618 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2619 {
2620         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2621
2622         for (i = 0; i < q_vectors; i++) {
2623                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2624                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2625                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2626                 q_vector->rxr_count = 0;
2627                 q_vector->txr_count = 0;
2628         }
2629 }
2630
2631 /**
2632  * ixgbe_request_irq - initialize interrupts
2633  * @adapter: board private structure
2634  *
2635  * Attempts to configure interrupts using the best available
2636  * capabilities of the hardware and kernel.
2637  **/
2638 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2639 {
2640         struct net_device *netdev = adapter->netdev;
2641         int err;
2642
2643         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2644                 err = ixgbe_request_msix_irqs(adapter);
2645         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2646                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2647                                   netdev->name, netdev);
2648         } else {
2649                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2650                                   netdev->name, netdev);
2651         }
2652
2653         if (err)
2654                 e_err(probe, "request_irq failed, Error %d\n", err);
2655
2656         return err;
2657 }
2658
2659 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2660 {
2661         struct net_device *netdev = adapter->netdev;
2662
2663         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2664                 int i, q_vectors;
2665
2666                 q_vectors = adapter->num_msix_vectors;
2667
2668                 i = q_vectors - 1;
2669                 free_irq(adapter->msix_entries[i].vector, netdev);
2670
2671                 i--;
2672                 for (; i >= 0; i--) {
2673                         /* free only the irqs that were actually requested */
2674                         if (!adapter->q_vector[i]->rxr_count &&
2675                             !adapter->q_vector[i]->txr_count)
2676                                 continue;
2677
2678                         free_irq(adapter->msix_entries[i].vector,
2679                                  adapter->q_vector[i]);
2680                 }
2681
2682                 ixgbe_reset_q_vectors(adapter);
2683         } else {
2684                 free_irq(adapter->pdev->irq, netdev);
2685         }
2686 }
2687
2688 /**
2689  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2690  * @adapter: board private structure
2691  **/
2692 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2693 {
2694         switch (adapter->hw.mac.type) {
2695         case ixgbe_mac_82598EB:
2696                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2697                 break;
2698         case ixgbe_mac_82599EB:
2699         case ixgbe_mac_X540:
2700                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2701                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2702                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2703                 if (adapter->num_vfs > 32)
2704                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2705                 break;
2706         default:
2707                 break;
2708         }
2709         IXGBE_WRITE_FLUSH(&adapter->hw);
2710         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2711                 int i;
2712                 for (i = 0; i < adapter->num_msix_vectors; i++)
2713                         synchronize_irq(adapter->msix_entries[i].vector);
2714         } else {
2715                 synchronize_irq(adapter->pdev->irq);
2716         }
2717 }
2718
2719 /**
2720  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2721  *
2722  **/
2723 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2724 {
2725         struct ixgbe_hw *hw = &adapter->hw;
2726
2727         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2728                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2729
2730         ixgbe_set_ivar(adapter, 0, 0, 0);
2731         ixgbe_set_ivar(adapter, 1, 0, 0);
2732
2733         map_vector_to_rxq(adapter, 0, 0);
2734         map_vector_to_txq(adapter, 0, 0);
2735
2736         e_info(hw, "Legacy interrupt IVAR setup done\n");
2737 }
2738
2739 /**
2740  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2741  * @adapter: board private structure
2742  * @ring: structure containing ring specific data
2743  *
2744  * Configure the Tx descriptor ring after a reset.
2745  **/
2746 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2747                              struct ixgbe_ring *ring)
2748 {
2749         struct ixgbe_hw *hw = &adapter->hw;
2750         u64 tdba = ring->dma;
2751         int wait_loop = 10;
2752         u32 txdctl;
2753         u8 reg_idx = ring->reg_idx;
2754
2755         /* disable queue to avoid issues while updating state */
2756         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2757         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2758                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2759         IXGBE_WRITE_FLUSH(hw);
2760
2761         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2762                         (tdba & DMA_BIT_MASK(32)));
2763         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2764         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2765                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2766         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2767         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2768         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2769
2770         /* configure fetching thresholds */
2771         if (adapter->rx_itr_setting == 0) {
2772                 /* cannot set wthresh when itr==0 */
2773                 txdctl &= ~0x007F0000;
2774         } else {
2775                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2776                 txdctl |= (8 << 16);
2777         }
2778         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2779                 /* PThresh workaround for Tx hang with DFP enabled. */
2780                 txdctl |= 32;
2781         }
2782
2783         /* reinitialize flowdirector state */
2784         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2785             adapter->atr_sample_rate) {
2786                 ring->atr_sample_rate = adapter->atr_sample_rate;
2787                 ring->atr_count = 0;
2788                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2789         } else {
2790                 ring->atr_sample_rate = 0;
2791         }
2792
2793         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2794
2795         /* enable queue */
2796         txdctl |= IXGBE_TXDCTL_ENABLE;
2797         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2798
2799         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2800         if (hw->mac.type == ixgbe_mac_82598EB &&
2801             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2802                 return;
2803
2804         /* poll to verify queue is enabled */
2805         do {
2806                 usleep_range(1000, 2000);
2807                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2808         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2809         if (!wait_loop)
2810                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2811 }
2812
2813 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2814 {
2815         struct ixgbe_hw *hw = &adapter->hw;
2816         u32 rttdcs;
2817         u32 mask;
2818
2819         if (hw->mac.type == ixgbe_mac_82598EB)
2820                 return;
2821
2822         /* disable the arbiter while setting MTQC */
2823         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2824         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2825         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2826
2827         /* set transmit pool layout */
2828         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2829         switch (adapter->flags & mask) {
2830
2831         case (IXGBE_FLAG_SRIOV_ENABLED):
2832                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2833                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2834                 break;
2835
2836         case (IXGBE_FLAG_DCB_ENABLED):
2837                 /* We enable 8 traffic classes, DCB only */
2838                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2839                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2840                 break;
2841
2842         default:
2843                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2844                 break;
2845         }
2846
2847         /* re-enable the arbiter */
2848         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2849         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2850 }
2851
2852 /**
2853  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2854  * @adapter: board private structure
2855  *
2856  * Configure the Tx unit of the MAC after a reset.
2857  **/
2858 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2859 {
2860         struct ixgbe_hw *hw = &adapter->hw;
2861         u32 dmatxctl;
2862         u32 i;
2863
2864         ixgbe_setup_mtqc(adapter);
2865
2866         if (hw->mac.type != ixgbe_mac_82598EB) {
2867                 /* DMATXCTL.EN must be before Tx queues are enabled */
2868                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2869                 dmatxctl |= IXGBE_DMATXCTL_TE;
2870                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2871         }
2872
2873         /* Setup the HW Tx Head and Tail descriptor pointers */
2874         for (i = 0; i < adapter->num_tx_queues; i++)
2875                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2876 }
2877
2878 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2879
2880 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2881                                    struct ixgbe_ring *rx_ring)
2882 {
2883         u32 srrctl;
2884         u8 reg_idx = rx_ring->reg_idx;
2885
2886         switch (adapter->hw.mac.type) {
2887         case ixgbe_mac_82598EB: {
2888                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2889                 const int mask = feature[RING_F_RSS].mask;
2890                 reg_idx = reg_idx & mask;
2891         }
2892                 break;
2893         case ixgbe_mac_82599EB:
2894         case ixgbe_mac_X540:
2895         default:
2896                 break;
2897         }
2898
2899         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2900
2901         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2902         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2903         if (adapter->num_vfs)
2904                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2905
2906         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2907                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2908
2909         if (ring_is_ps_enabled(rx_ring)) {
2910 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2911                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2912 #else
2913                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2914 #endif
2915                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2916         } else {
2917                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2918                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2919                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2920         }
2921
2922         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2923 }
2924
2925 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2926 {
2927         struct ixgbe_hw *hw = &adapter->hw;
2928         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2929                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2930                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2931         u32 mrqc = 0, reta = 0;
2932         u32 rxcsum;
2933         int i, j;
2934         int mask;
2935
2936         /* Fill out hash function seeds */
2937         for (i = 0; i < 10; i++)
2938                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2939
2940         /* Fill out redirection table */
2941         for (i = 0, j = 0; i < 128; i++, j++) {
2942                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2943                         j = 0;
2944                 /* reta = 4-byte sliding window of
2945                  * 0x00..(indices-1)(indices-1)00..etc. */
2946                 reta = (reta << 8) | (j * 0x11);
2947                 if ((i & 3) == 3)
2948                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2949         }
2950
2951         /* Disable indicating checksum in descriptor, enables RSS hash */
2952         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2953         rxcsum |= IXGBE_RXCSUM_PCSD;
2954         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2955
2956         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2957                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2958         else
2959                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2960 #ifdef CONFIG_IXGBE_DCB
2961                                          | IXGBE_FLAG_DCB_ENABLED
2962 #endif
2963                                          | IXGBE_FLAG_SRIOV_ENABLED
2964                                         );
2965
2966         switch (mask) {
2967 #ifdef CONFIG_IXGBE_DCB
2968         case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2969                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2970                 break;
2971         case (IXGBE_FLAG_DCB_ENABLED):
2972                 mrqc = IXGBE_MRQC_RT8TCEN;
2973                 break;
2974 #endif /* CONFIG_IXGBE_DCB */
2975         case (IXGBE_FLAG_RSS_ENABLED):
2976                 mrqc = IXGBE_MRQC_RSSEN;
2977                 break;
2978         case (IXGBE_FLAG_SRIOV_ENABLED):
2979                 mrqc = IXGBE_MRQC_VMDQEN;
2980                 break;
2981         default:
2982                 break;
2983         }
2984
2985         /* Perform hash on these packet types */
2986         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2987               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2988               | IXGBE_MRQC_RSS_FIELD_IPV6
2989               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2990
2991         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2992 }
2993
2994 /**
2995  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2996  * @adapter: address of board private structure
2997  * @ring: structure containing ring specific data
2998  **/
2999 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
3000                         struct ixgbe_ring *ring)
3001 {
3002         struct ixgbe_hw *hw = &adapter->hw;
3003         u32 rscctrl;
3004         u8 reg_idx = ring->reg_idx;
3005
3006         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3007         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
3008         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3009 }
3010
3011 /**
3012  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3013  * @adapter:    address of board private structure
3014  * @index:      index of ring to set
3015  **/
3016 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3017                                    struct ixgbe_ring *ring)
3018 {
3019         struct ixgbe_hw *hw = &adapter->hw;
3020         u32 rscctrl;
3021         int rx_buf_len;
3022         u8 reg_idx = ring->reg_idx;
3023
3024         if (!ring_is_rsc_enabled(ring))
3025                 return;
3026
3027         rx_buf_len = ring->rx_buf_len;
3028         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3029         rscctrl |= IXGBE_RSCCTL_RSCEN;
3030         /*
3031          * we must limit the number of descriptors so that the
3032          * total size of max desc * buf_len is not greater
3033          * than 65535
3034          */
3035         if (ring_is_ps_enabled(ring)) {
3036 #if (MAX_SKB_FRAGS > 16)
3037                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3038 #elif (MAX_SKB_FRAGS > 8)
3039                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3040 #elif (MAX_SKB_FRAGS > 4)
3041                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3042 #else
3043                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3044 #endif
3045         } else {
3046                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3047                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3048                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3049                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3050                 else
3051                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3052         }
3053         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3054 }
3055
3056 /**
3057  *  ixgbe_set_uta - Set unicast filter table address
3058  *  @adapter: board private structure
3059  *
3060  *  The unicast table address is a register array of 32-bit registers.
3061  *  The table is meant to be used in a way similar to how the MTA is used
3062  *  however due to certain limitations in the hardware it is necessary to
3063  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3064  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
3065  **/
3066 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3067 {
3068         struct ixgbe_hw *hw = &adapter->hw;
3069         int i;
3070
3071         /* The UTA table only exists on 82599 hardware and newer */
3072         if (hw->mac.type < ixgbe_mac_82599EB)
3073                 return;
3074
3075         /* we only need to do this if VMDq is enabled */
3076         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3077                 return;
3078
3079         for (i = 0; i < 128; i++)
3080                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3081 }
3082
3083 #define IXGBE_MAX_RX_DESC_POLL 10
3084 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3085                                        struct ixgbe_ring *ring)
3086 {
3087         struct ixgbe_hw *hw = &adapter->hw;
3088         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3089         u32 rxdctl;
3090         u8 reg_idx = ring->reg_idx;
3091
3092         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3093         if (hw->mac.type == ixgbe_mac_82598EB &&
3094             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3095                 return;
3096
3097         do {
3098                 usleep_range(1000, 2000);
3099                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3100         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3101
3102         if (!wait_loop) {
3103                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3104                       "the polling period\n", reg_idx);
3105         }
3106 }
3107
3108 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3109                             struct ixgbe_ring *ring)
3110 {
3111         struct ixgbe_hw *hw = &adapter->hw;
3112         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3113         u32 rxdctl;
3114         u8 reg_idx = ring->reg_idx;
3115
3116         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3117         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3118
3119         /* write value back with RXDCTL.ENABLE bit cleared */
3120         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3121
3122         if (hw->mac.type == ixgbe_mac_82598EB &&
3123             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3124                 return;
3125
3126         /* the hardware may take up to 100us to really disable the rx queue */
3127         do {
3128                 udelay(10);
3129                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3130         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3131
3132         if (!wait_loop) {
3133                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3134                       "the polling period\n", reg_idx);
3135         }
3136 }
3137
3138 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3139                              struct ixgbe_ring *ring)
3140 {
3141         struct ixgbe_hw *hw = &adapter->hw;
3142         u64 rdba = ring->dma;
3143         u32 rxdctl;
3144         u8 reg_idx = ring->reg_idx;
3145
3146         /* disable queue to avoid issues while updating state */
3147         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3148         ixgbe_disable_rx_queue(adapter, ring);
3149
3150         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3151         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3152         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3153                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3154         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3155         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3156         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3157
3158         ixgbe_configure_srrctl(adapter, ring);
3159         ixgbe_configure_rscctl(adapter, ring);
3160
3161         /* If operating in IOV mode set RLPML for X540 */
3162         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3163             hw->mac.type == ixgbe_mac_X540) {
3164                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3165                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3166                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3167         }
3168
3169         if (hw->mac.type == ixgbe_mac_82598EB) {
3170                 /*
3171                  * enable cache line friendly hardware writes:
3172                  * PTHRESH=32 descriptors (half the internal cache),
3173                  * this also removes ugly rx_no_buffer_count increment
3174                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3175                  * WTHRESH=8 burst writeback up to two cache lines
3176                  */
3177                 rxdctl &= ~0x3FFFFF;
3178                 rxdctl |=  0x080420;
3179         }
3180
3181         /* enable receive descriptor ring */
3182         rxdctl |= IXGBE_RXDCTL_ENABLE;
3183         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3184
3185         ixgbe_rx_desc_queue_enable(adapter, ring);
3186         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3187 }
3188
3189 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3190 {
3191         struct ixgbe_hw *hw = &adapter->hw;
3192         int p;
3193
3194         /* PSRTYPE must be initialized in non 82598 adapters */
3195         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3196                       IXGBE_PSRTYPE_UDPHDR |
3197                       IXGBE_PSRTYPE_IPV4HDR |
3198                       IXGBE_PSRTYPE_L2HDR |
3199                       IXGBE_PSRTYPE_IPV6HDR;
3200
3201         if (hw->mac.type == ixgbe_mac_82598EB)
3202                 return;
3203
3204         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3205                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3206
3207         for (p = 0; p < adapter->num_rx_pools; p++)
3208                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3209                                 psrtype);
3210 }
3211
3212 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3213 {
3214         struct ixgbe_hw *hw = &adapter->hw;
3215         u32 gcr_ext;
3216         u32 vt_reg_bits;
3217         u32 reg_offset, vf_shift;
3218         u32 vmdctl;
3219
3220         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3221                 return;
3222
3223         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3224         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3225         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3226         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3227
3228         vf_shift = adapter->num_vfs % 32;
3229         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3230
3231         /* Enable only the PF's pool for Tx/Rx */
3232         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3233         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3234         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3235         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3236         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3237
3238         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3239         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3240
3241         /*
3242          * Set up VF register offsets for selected VT Mode,
3243          * i.e. 32 or 64 VFs for SR-IOV
3244          */
3245         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3246         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3247         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3248         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3249
3250         /* enable Tx loopback for VF/PF communication */
3251         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3252         /* Enable MAC Anti-Spoofing */
3253         hw->mac.ops.set_mac_anti_spoofing(hw,
3254                                           (adapter->antispoofing_enabled =
3255                                            (adapter->num_vfs != 0)),
3256                                           adapter->num_vfs);
3257 }
3258
3259 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3260 {
3261         struct ixgbe_hw *hw = &adapter->hw;
3262         struct net_device *netdev = adapter->netdev;
3263         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3264         int rx_buf_len;
3265         struct ixgbe_ring *rx_ring;
3266         int i;
3267         u32 mhadd, hlreg0;
3268
3269         /* Decide whether to use packet split mode or not */
3270         /* On by default */
3271         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3272
3273         /* Do not use packet split if we're in SR-IOV Mode */
3274         if (adapter->num_vfs)
3275                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3276
3277         /* Disable packet split due to 82599 erratum #45 */
3278         if (hw->mac.type == ixgbe_mac_82599EB)
3279                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3280
3281         /* Set the RX buffer length according to the mode */
3282         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3283                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3284         } else {
3285                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3286                     (netdev->mtu <= ETH_DATA_LEN))
3287                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3288                 else
3289                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3290         }
3291
3292 #ifdef IXGBE_FCOE
3293         /* adjust max frame to be able to do baby jumbo for FCoE */
3294         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3295             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3296                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3297
3298 #endif /* IXGBE_FCOE */
3299         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3300         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3301                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3302                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3303
3304                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3305         }
3306
3307         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3308         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3309         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3310         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3311
3312         /*
3313          * Setup the HW Rx Head and Tail Descriptor Pointers and
3314          * the Base and Length of the Rx Descriptor Ring
3315          */
3316         for (i = 0; i < adapter->num_rx_queues; i++) {
3317                 rx_ring = adapter->rx_ring[i];
3318                 rx_ring->rx_buf_len = rx_buf_len;
3319
3320                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3321                         set_ring_ps_enabled(rx_ring);
3322                 else
3323                         clear_ring_ps_enabled(rx_ring);
3324
3325                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3326                         set_ring_rsc_enabled(rx_ring);
3327                 else
3328                         clear_ring_rsc_enabled(rx_ring);
3329
3330 #ifdef IXGBE_FCOE
3331                 if (netdev->features & NETIF_F_FCOE_MTU) {
3332                         struct ixgbe_ring_feature *f;
3333                         f = &adapter->ring_feature[RING_F_FCOE];
3334                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3335                                 clear_ring_ps_enabled(rx_ring);
3336                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3337                                         rx_ring->rx_buf_len =
3338                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3339                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3340                                    !ring_is_ps_enabled(rx_ring)) {
3341                                 rx_ring->rx_buf_len =
3342                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3343                         }
3344                 }
3345 #endif /* IXGBE_FCOE */
3346         }
3347 }
3348
3349 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3350 {
3351         struct ixgbe_hw *hw = &adapter->hw;
3352         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3353
3354         switch (hw->mac.type) {
3355         case ixgbe_mac_82598EB:
3356                 /*
3357                  * For VMDq support of different descriptor types or
3358                  * buffer sizes through the use of multiple SRRCTL
3359                  * registers, RDRXCTL.MVMEN must be set to 1
3360                  *
3361                  * also, the manual doesn't mention it clearly but DCA hints
3362                  * will only use queue 0's tags unless this bit is set.  Side
3363                  * effects of setting this bit are only that SRRCTL must be
3364                  * fully programmed [0..15]
3365                  */
3366                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3367                 break;
3368         case ixgbe_mac_82599EB:
3369         case ixgbe_mac_X540:
3370                 /* Disable RSC for ACK packets */
3371                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3372                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3373                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3374                 /* hardware requires some bits to be set by default */
3375                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3376                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3377                 break;
3378         default:
3379                 /* We should do nothing since we don't know this hardware */
3380                 return;
3381         }
3382
3383         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3384 }
3385
3386 /**
3387  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3388  * @adapter: board private structure
3389  *
3390  * Configure the Rx unit of the MAC after a reset.
3391  **/
3392 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3393 {
3394         struct ixgbe_hw *hw = &adapter->hw;
3395         int i;
3396         u32 rxctrl;
3397
3398         /* disable receives while setting up the descriptors */
3399         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3400         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3401
3402         ixgbe_setup_psrtype(adapter);
3403         ixgbe_setup_rdrxctl(adapter);
3404
3405         /* Program registers for the distribution of queues */
3406         ixgbe_setup_mrqc(adapter);
3407
3408         ixgbe_set_uta(adapter);
3409
3410         /* set_rx_buffer_len must be called before ring initialization */
3411         ixgbe_set_rx_buffer_len(adapter);
3412
3413         /*
3414          * Setup the HW Rx Head and Tail Descriptor Pointers and
3415          * the Base and Length of the Rx Descriptor Ring
3416          */
3417         for (i = 0; i < adapter->num_rx_queues; i++)
3418                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3419
3420         /* disable drop enable for 82598 parts */
3421         if (hw->mac.type == ixgbe_mac_82598EB)
3422                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3423
3424         /* enable all receives */
3425         rxctrl |= IXGBE_RXCTRL_RXEN;
3426         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3427 }
3428
3429 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3430 {
3431         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3432         struct ixgbe_hw *hw = &adapter->hw;
3433         int pool_ndx = adapter->num_vfs;
3434
3435         /* add VID to filter table */
3436         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3437         set_bit(vid, adapter->active_vlans);
3438 }
3439
3440 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3441 {
3442         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3443         struct ixgbe_hw *hw = &adapter->hw;
3444         int pool_ndx = adapter->num_vfs;
3445
3446         /* remove VID from filter table */
3447         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3448         clear_bit(vid, adapter->active_vlans);
3449 }
3450
3451 /**
3452  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3453  * @adapter: driver data
3454  */
3455 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3456 {
3457         struct ixgbe_hw *hw = &adapter->hw;
3458         u32 vlnctrl;
3459
3460         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3461         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3462         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3463 }
3464
3465 /**
3466  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3467  * @adapter: driver data
3468  */
3469 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3470 {
3471         struct ixgbe_hw *hw = &adapter->hw;
3472         u32 vlnctrl;
3473
3474         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3475         vlnctrl |= IXGBE_VLNCTRL_VFE;
3476         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3477         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3478 }
3479
3480 /**
3481  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3482  * @adapter: driver data
3483  */
3484 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3485 {
3486         struct ixgbe_hw *hw = &adapter->hw;
3487         u32 vlnctrl;
3488         int i, j;
3489
3490         switch (hw->mac.type) {
3491         case ixgbe_mac_82598EB:
3492                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3493                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3494                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3495                 break;
3496         case ixgbe_mac_82599EB:
3497         case ixgbe_mac_X540:
3498                 for (i = 0; i < adapter->num_rx_queues; i++) {
3499                         j = adapter->rx_ring[i]->reg_idx;
3500                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3501                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3502                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3503                 }
3504                 break;
3505         default:
3506                 break;
3507         }
3508 }
3509
3510 /**
3511  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3512  * @adapter: driver data
3513  */
3514 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3515 {
3516         struct ixgbe_hw *hw = &adapter->hw;
3517         u32 vlnctrl;
3518         int i, j;
3519
3520         switch (hw->mac.type) {
3521         case ixgbe_mac_82598EB:
3522                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3523                 vlnctrl |= IXGBE_VLNCTRL_VME;
3524                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3525                 break;
3526         case ixgbe_mac_82599EB:
3527         case ixgbe_mac_X540:
3528                 for (i = 0; i < adapter->num_rx_queues; i++) {
3529                         j = adapter->rx_ring[i]->reg_idx;
3530                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3531                         vlnctrl |= IXGBE_RXDCTL_VME;
3532                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3533                 }
3534                 break;
3535         default:
3536                 break;
3537         }
3538 }
3539
3540 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3541 {
3542         u16 vid;
3543
3544         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3545
3546         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3547                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3548 }
3549
3550 /**
3551  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3552  * @netdev: network interface device structure
3553  *
3554  * Writes unicast address list to the RAR table.
3555  * Returns: -ENOMEM on failure/insufficient address space
3556  *                0 on no addresses written
3557  *                X on writing X addresses to the RAR table
3558  **/
3559 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3560 {
3561         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3562         struct ixgbe_hw *hw = &adapter->hw;
3563         unsigned int vfn = adapter->num_vfs;
3564         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3565         int count = 0;
3566
3567         /* return ENOMEM indicating insufficient memory for addresses */
3568         if (netdev_uc_count(netdev) > rar_entries)
3569                 return -ENOMEM;
3570
3571         if (!netdev_uc_empty(netdev) && rar_entries) {
3572                 struct netdev_hw_addr *ha;
3573                 /* return error if we do not support writing to RAR table */
3574                 if (!hw->mac.ops.set_rar)
3575                         return -ENOMEM;
3576
3577                 netdev_for_each_uc_addr(ha, netdev) {
3578                         if (!rar_entries)
3579                                 break;
3580                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3581                                             vfn, IXGBE_RAH_AV);
3582                         count++;
3583                 }
3584         }
3585         /* write the addresses in reverse order to avoid write combining */
3586         for (; rar_entries > 0 ; rar_entries--)
3587                 hw->mac.ops.clear_rar(hw, rar_entries);
3588
3589         return count;
3590 }
3591
3592 /**
3593  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3594  * @netdev: network interface device structure
3595  *
3596  * The set_rx_method entry point is called whenever the unicast/multicast
3597  * address list or the network interface flags are updated.  This routine is
3598  * responsible for configuring the hardware for proper unicast, multicast and
3599  * promiscuous mode.
3600  **/
3601 void ixgbe_set_rx_mode(struct net_device *netdev)
3602 {
3603         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3604         struct ixgbe_hw *hw = &adapter->hw;
3605         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3606         int count;
3607
3608         /* Check for Promiscuous and All Multicast modes */
3609
3610         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611
3612         /* set all bits that we expect to always be set */
3613         fctrl |= IXGBE_FCTRL_BAM;
3614         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3615         fctrl |= IXGBE_FCTRL_PMCF;
3616
3617         /* clear the bits we are changing the status of */
3618         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3619
3620         if (netdev->flags & IFF_PROMISC) {
3621                 hw->addr_ctrl.user_set_promisc = true;
3622                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3623                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3624                 /* don't hardware filter vlans in promisc mode */
3625                 ixgbe_vlan_filter_disable(adapter);
3626         } else {
3627                 if (netdev->flags & IFF_ALLMULTI) {
3628                         fctrl |= IXGBE_FCTRL_MPE;
3629                         vmolr |= IXGBE_VMOLR_MPE;
3630                 } else {
3631                         /*
3632                          * Write addresses to the MTA, if the attempt fails
3633                          * then we should just turn on promiscuous mode so
3634                          * that we can at least receive multicast traffic
3635                          */
3636                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3637                         vmolr |= IXGBE_VMOLR_ROMPE;
3638                 }
3639                 ixgbe_vlan_filter_enable(adapter);
3640                 hw->addr_ctrl.user_set_promisc = false;
3641                 /*
3642                  * Write addresses to available RAR registers, if there is not
3643                  * sufficient space to store all the addresses then enable
3644                  * unicast promiscuous mode
3645                  */
3646                 count = ixgbe_write_uc_addr_list(netdev);
3647                 if (count < 0) {
3648                         fctrl |= IXGBE_FCTRL_UPE;
3649                         vmolr |= IXGBE_VMOLR_ROPE;
3650                 }
3651         }
3652
3653         if (adapter->num_vfs) {
3654                 ixgbe_restore_vf_multicasts(adapter);
3655                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3656                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3657                            IXGBE_VMOLR_ROPE);
3658                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3659         }
3660
3661         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3662
3663         if (netdev->features & NETIF_F_HW_VLAN_RX)
3664                 ixgbe_vlan_strip_enable(adapter);
3665         else
3666                 ixgbe_vlan_strip_disable(adapter);
3667 }
3668
3669 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3670 {
3671         int q_idx;
3672         struct ixgbe_q_vector *q_vector;
3673         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3674
3675         /* legacy and MSI only use one vector */
3676         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3677                 q_vectors = 1;
3678
3679         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3680                 struct napi_struct *napi;
3681                 q_vector = adapter->q_vector[q_idx];
3682                 napi = &q_vector->napi;
3683                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3684                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3685                                 if (q_vector->txr_count == 1)
3686                                         napi->poll = &ixgbe_clean_txonly;
3687                                 else if (q_vector->rxr_count == 1)
3688                                         napi->poll = &ixgbe_clean_rxonly;
3689                         }
3690                 }
3691
3692                 napi_enable(napi);
3693         }
3694 }
3695
3696 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3697 {
3698         int q_idx;
3699         struct ixgbe_q_vector *q_vector;
3700         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3701
3702         /* legacy and MSI only use one vector */
3703         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3704                 q_vectors = 1;
3705
3706         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3707                 q_vector = adapter->q_vector[q_idx];
3708                 napi_disable(&q_vector->napi);
3709         }
3710 }
3711
3712 #ifdef CONFIG_IXGBE_DCB
3713 /*
3714  * ixgbe_configure_dcb - Configure DCB hardware
3715  * @adapter: ixgbe adapter struct
3716  *
3717  * This is called by the driver on open to configure the DCB hardware.
3718  * This is also called by the gennetlink interface when reconfiguring
3719  * the DCB state.
3720  */
3721 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3722 {
3723         struct ixgbe_hw *hw = &adapter->hw;
3724         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3725
3726         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3727                 if (hw->mac.type == ixgbe_mac_82598EB)
3728                         netif_set_gso_max_size(adapter->netdev, 65536);
3729                 return;
3730         }
3731
3732         if (hw->mac.type == ixgbe_mac_82598EB)
3733                 netif_set_gso_max_size(adapter->netdev, 32768);
3734
3735
3736         /* Enable VLAN tag insert/strip */
3737         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3738
3739         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3740
3741         /* reconfigure the hardware */
3742         if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3743 #ifdef CONFIG_FCOE
3744                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3745                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3746 #endif
3747                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3748                                                 DCB_TX_CONFIG);
3749                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3750                                                 DCB_RX_CONFIG);
3751                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3752         } else {
3753                 struct net_device *dev = adapter->netdev;
3754
3755                 if (adapter->ixgbe_ieee_ets)
3756                         dev->dcbnl_ops->ieee_setets(dev,
3757                                                     adapter->ixgbe_ieee_ets);
3758                 if (adapter->ixgbe_ieee_pfc)
3759                         dev->dcbnl_ops->ieee_setpfc(dev,
3760                                                     adapter->ixgbe_ieee_pfc);
3761         }
3762
3763         /* Enable RSS Hash per TC */
3764         if (hw->mac.type != ixgbe_mac_82598EB) {
3765                 int i;
3766                 u32 reg = 0;
3767
3768                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3769                         u8 msb = 0;
3770                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3771
3772                         while (cnt >>= 1)
3773                                 msb++;
3774
3775                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3776                 }
3777                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3778         }
3779 }
3780
3781 #endif
3782 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3783 {
3784         struct net_device *netdev = adapter->netdev;
3785         struct ixgbe_hw *hw = &adapter->hw;
3786         int i;
3787
3788 #ifdef CONFIG_IXGBE_DCB
3789         ixgbe_configure_dcb(adapter);
3790 #endif
3791
3792         ixgbe_set_rx_mode(netdev);
3793         ixgbe_restore_vlan(adapter);
3794
3795 #ifdef IXGBE_FCOE
3796         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3797                 ixgbe_configure_fcoe(adapter);
3798
3799 #endif /* IXGBE_FCOE */
3800         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3801                 for (i = 0; i < adapter->num_tx_queues; i++)
3802                         adapter->tx_ring[i]->atr_sample_rate =
3803                                                        adapter->atr_sample_rate;
3804                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3805         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3806                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3807         }
3808         ixgbe_configure_virtualization(adapter);
3809
3810         ixgbe_configure_tx(adapter);
3811         ixgbe_configure_rx(adapter);
3812 }
3813
3814 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3815 {
3816         switch (hw->phy.type) {
3817         case ixgbe_phy_sfp_avago:
3818         case ixgbe_phy_sfp_ftl:
3819         case ixgbe_phy_sfp_intel:
3820         case ixgbe_phy_sfp_unknown:
3821         case ixgbe_phy_sfp_passive_tyco:
3822         case ixgbe_phy_sfp_passive_unknown:
3823         case ixgbe_phy_sfp_active_unknown:
3824         case ixgbe_phy_sfp_ftl_active:
3825                 return true;
3826         default:
3827                 return false;
3828         }
3829 }
3830
3831 /**
3832  * ixgbe_sfp_link_config - set up SFP+ link
3833  * @adapter: pointer to private adapter struct
3834  **/
3835 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3836 {
3837         /*
3838          * We are assuming the worst case scenerio here, and that
3839          * is that an SFP was inserted/removed after the reset
3840          * but before SFP detection was enabled.  As such the best
3841          * solution is to just start searching as soon as we start
3842          */
3843         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3844                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3845
3846         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3847 }
3848
3849 /**
3850  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3851  * @hw: pointer to private hardware struct
3852  *
3853  * Returns 0 on success, negative on failure
3854  **/
3855 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3856 {
3857         u32 autoneg;
3858         bool negotiation, link_up = false;
3859         u32 ret = IXGBE_ERR_LINK_SETUP;
3860
3861         if (hw->mac.ops.check_link)
3862                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3863
3864         if (ret)
3865                 goto link_cfg_out;
3866
3867         autoneg = hw->phy.autoneg_advertised;
3868         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3869                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3870                                                         &negotiation);
3871         if (ret)
3872                 goto link_cfg_out;
3873
3874         if (hw->mac.ops.setup_link)
3875                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3876 link_cfg_out:
3877         return ret;
3878 }
3879
3880 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3881 {
3882         struct ixgbe_hw *hw = &adapter->hw;
3883         u32 gpie = 0;
3884
3885         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3886                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3887                        IXGBE_GPIE_OCD;
3888                 gpie |= IXGBE_GPIE_EIAME;
3889                 /*
3890                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3891                  * this saves a register write for every interrupt
3892                  */
3893                 switch (hw->mac.type) {
3894                 case ixgbe_mac_82598EB:
3895                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3896                         break;
3897                 case ixgbe_mac_82599EB:
3898                 case ixgbe_mac_X540:
3899                 default:
3900                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3901                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3902                         break;
3903                 }
3904         } else {
3905                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3906                  * specifically only auto mask tx and rx interrupts */
3907                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3908         }
3909
3910         /* XXX: to interrupt immediately for EICS writes, enable this */
3911         /* gpie |= IXGBE_GPIE_EIMEN; */
3912
3913         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3914                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3915                 gpie |= IXGBE_GPIE_VTMODE_64;
3916         }
3917
3918         /* Enable fan failure interrupt */
3919         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3920                 gpie |= IXGBE_SDP1_GPIEN;
3921
3922         if (hw->mac.type == ixgbe_mac_82599EB) {
3923                 gpie |= IXGBE_SDP1_GPIEN;
3924                 gpie |= IXGBE_SDP2_GPIEN;
3925         }
3926
3927         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3928 }
3929
3930 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3931 {
3932         struct ixgbe_hw *hw = &adapter->hw;
3933         int err;
3934         u32 ctrl_ext;
3935
3936         ixgbe_get_hw_control(adapter);
3937         ixgbe_setup_gpie(adapter);
3938
3939         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3940                 ixgbe_configure_msix(adapter);
3941         else
3942                 ixgbe_configure_msi_and_legacy(adapter);
3943
3944         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3945         if (hw->mac.ops.enable_tx_laser &&
3946             ((hw->phy.multispeed_fiber) ||
3947              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3948               (hw->mac.type == ixgbe_mac_82599EB))))
3949                 hw->mac.ops.enable_tx_laser(hw);
3950
3951         clear_bit(__IXGBE_DOWN, &adapter->state);
3952         ixgbe_napi_enable_all(adapter);
3953
3954         if (ixgbe_is_sfp(hw)) {
3955                 ixgbe_sfp_link_config(adapter);
3956         } else {
3957                 err = ixgbe_non_sfp_link_config(hw);
3958                 if (err)
3959                         e_err(probe, "link_config FAILED %d\n", err);
3960         }
3961
3962         /* clear any pending interrupts, may auto mask */
3963         IXGBE_READ_REG(hw, IXGBE_EICR);
3964         ixgbe_irq_enable(adapter, true, true);
3965
3966         /*
3967          * If this adapter has a fan, check to see if we had a failure
3968          * before we enabled the interrupt.
3969          */
3970         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3971                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3972                 if (esdp & IXGBE_ESDP_SDP1)
3973                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3974         }
3975
3976         /* enable transmits */
3977         netif_tx_start_all_queues(adapter->netdev);
3978
3979         /* bring the link up in the watchdog, this could race with our first
3980          * link up interrupt but shouldn't be a problem */
3981         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3982         adapter->link_check_timeout = jiffies;
3983         mod_timer(&adapter->service_timer, jiffies);
3984
3985         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3986         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3987         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3988         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3989
3990         return 0;
3991 }
3992
3993 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3994 {
3995         WARN_ON(in_interrupt());
3996         /* put off any impending NetWatchDogTimeout */
3997         adapter->netdev->trans_start = jiffies;
3998
3999         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4000                 usleep_range(1000, 2000);
4001         ixgbe_down(adapter);
4002         /*
4003          * If SR-IOV enabled then wait a bit before bringing the adapter
4004          * back up to give the VFs time to respond to the reset.  The
4005          * two second wait is based upon the watchdog timer cycle in
4006          * the VF driver.
4007          */
4008         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4009                 msleep(2000);
4010         ixgbe_up(adapter);
4011         clear_bit(__IXGBE_RESETTING, &adapter->state);
4012 }
4013
4014 int ixgbe_up(struct ixgbe_adapter *adapter)
4015 {
4016         /* hardware has been reset, we need to reload some things */
4017         ixgbe_configure(adapter);
4018
4019         return ixgbe_up_complete(adapter);
4020 }
4021
4022 void ixgbe_reset(struct ixgbe_adapter *adapter)
4023 {
4024         struct ixgbe_hw *hw = &adapter->hw;
4025         int err;
4026
4027         /* lock SFP init bit to prevent race conditions with the watchdog */
4028         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4029                 usleep_range(1000, 2000);
4030
4031         /* clear all SFP and link config related flags while holding SFP_INIT */
4032         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4033                              IXGBE_FLAG2_SFP_NEEDS_RESET);
4034         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4035
4036         err = hw->mac.ops.init_hw(hw);
4037         switch (err) {
4038         case 0:
4039         case IXGBE_ERR_SFP_NOT_PRESENT:
4040         case IXGBE_ERR_SFP_NOT_SUPPORTED:
4041                 break;
4042         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4043                 e_dev_err("master disable timed out\n");
4044                 break;
4045         case IXGBE_ERR_EEPROM_VERSION:
4046                 /* We are running on a pre-production device, log a warning */
4047                 e_dev_warn("This device is a pre-production adapter/LOM. "
4048                            "Please be aware there may be issuesassociated with "
4049                            "your hardware.  If you are experiencing problems "
4050                            "please contact your Intel or hardware "
4051                            "representative who provided you with this "
4052                            "hardware.\n");
4053                 break;
4054         default:
4055                 e_dev_err("Hardware Error: %d\n", err);
4056         }
4057
4058         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4059
4060         /* reprogram the RAR[0] in case user changed it. */
4061         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4062                             IXGBE_RAH_AV);
4063 }
4064
4065 /**
4066  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4067  * @rx_ring: ring to free buffers from
4068  **/
4069 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4070 {
4071         struct device *dev = rx_ring->dev;
4072         unsigned long size;
4073         u16 i;
4074
4075         /* ring already cleared, nothing to do */
4076         if (!rx_ring->rx_buffer_info)
4077                 return;
4078
4079         /* Free all the Rx ring sk_buffs */
4080         for (i = 0; i < rx_ring->count; i++) {
4081                 struct ixgbe_rx_buffer *rx_buffer_info;
4082
4083                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4084                 if (rx_buffer_info->dma) {
4085                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4086                                          rx_ring->rx_buf_len,
4087                                          DMA_FROM_DEVICE);
4088                         rx_buffer_info->dma = 0;
4089                 }
4090                 if (rx_buffer_info->skb) {
4091                         struct sk_buff *skb = rx_buffer_info->skb;
4092                         rx_buffer_info->skb = NULL;
4093                         do {
4094                                 struct sk_buff *this = skb;
4095                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4096                                         dma_unmap_single(dev,
4097                                                          IXGBE_RSC_CB(this)->dma,
4098                                                          rx_ring->rx_buf_len,
4099                                                          DMA_FROM_DEVICE);
4100                                         IXGBE_RSC_CB(this)->dma = 0;
4101                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4102                                 }
4103                                 skb = skb->prev;
4104                                 dev_kfree_skb(this);
4105                         } while (skb);
4106                 }
4107                 if (!rx_buffer_info->page)
4108                         continue;
4109                 if (rx_buffer_info->page_dma) {
4110                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4111                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4112                         rx_buffer_info->page_dma = 0;
4113                 }
4114                 put_page(rx_buffer_info->page);
4115                 rx_buffer_info->page = NULL;
4116                 rx_buffer_info->page_offset = 0;
4117         }
4118
4119         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4120         memset(rx_ring->rx_buffer_info, 0, size);
4121
4122         /* Zero out the descriptor ring */
4123         memset(rx_ring->desc, 0, rx_ring->size);
4124
4125         rx_ring->next_to_clean = 0;
4126         rx_ring->next_to_use = 0;
4127 }
4128
4129 /**
4130  * ixgbe_clean_tx_ring - Free Tx Buffers
4131  * @tx_ring: ring to be cleaned
4132  **/
4133 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4134 {
4135         struct ixgbe_tx_buffer *tx_buffer_info;
4136         unsigned long size;
4137         u16 i;
4138
4139         /* ring already cleared, nothing to do */
4140         if (!tx_ring->tx_buffer_info)
4141                 return;
4142
4143         /* Free all the Tx ring sk_buffs */
4144         for (i = 0; i < tx_ring->count; i++) {
4145                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4146                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4147         }
4148
4149         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4150         memset(tx_ring->tx_buffer_info, 0, size);
4151
4152         /* Zero out the descriptor ring */
4153         memset(tx_ring->desc, 0, tx_ring->size);
4154
4155         tx_ring->next_to_use = 0;
4156         tx_ring->next_to_clean = 0;
4157 }
4158
4159 /**
4160  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4161  * @adapter: board private structure
4162  **/
4163 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4164 {
4165         int i;
4166
4167         for (i = 0; i < adapter->num_rx_queues; i++)
4168                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4169 }
4170
4171 /**
4172  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4173  * @adapter: board private structure
4174  **/
4175 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4176 {
4177         int i;
4178
4179         for (i = 0; i < adapter->num_tx_queues; i++)
4180                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4181 }
4182
4183 void ixgbe_down(struct ixgbe_adapter *adapter)
4184 {
4185         struct net_device *netdev = adapter->netdev;
4186         struct ixgbe_hw *hw = &adapter->hw;
4187         u32 rxctrl;
4188         int i;
4189         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4190
4191         /* signal that we are down to the interrupt handler */
4192         set_bit(__IXGBE_DOWN, &adapter->state);
4193
4194         /* disable receives */
4195         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4196         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4197
4198         /* disable all enabled rx queues */
4199         for (i = 0; i < adapter->num_rx_queues; i++)
4200                 /* this call also flushes the previous write */
4201                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4202
4203         usleep_range(10000, 20000);
4204
4205         netif_tx_stop_all_queues(netdev);
4206
4207         /* call carrier off first to avoid false dev_watchdog timeouts */
4208         netif_carrier_off(netdev);
4209         netif_tx_disable(netdev);
4210
4211         ixgbe_irq_disable(adapter);
4212
4213         ixgbe_napi_disable_all(adapter);
4214
4215         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4216                              IXGBE_FLAG2_RESET_REQUESTED);
4217         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4218
4219         del_timer_sync(&adapter->service_timer);
4220
4221         /* disable receive for all VFs and wait one second */
4222         if (adapter->num_vfs) {
4223                 /* ping all the active vfs to let them know we are going down */
4224                 ixgbe_ping_all_vfs(adapter);
4225
4226                 /* Disable all VFTE/VFRE TX/RX */
4227                 ixgbe_disable_tx_rx(adapter);
4228
4229                 /* Mark all the VFs as inactive */
4230                 for (i = 0 ; i < adapter->num_vfs; i++)
4231                         adapter->vfinfo[i].clear_to_send = 0;
4232         }
4233
4234         /* Cleanup the affinity_hint CPU mask memory and callback */
4235         for (i = 0; i < num_q_vectors; i++) {
4236                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4237                 /* clear the affinity_mask in the IRQ descriptor */
4238                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4239                 /* release the CPU mask memory */
4240                 free_cpumask_var(q_vector->affinity_mask);
4241         }
4242
4243         /* disable transmits in the hardware now that interrupts are off */
4244         for (i = 0; i < adapter->num_tx_queues; i++) {
4245                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4246                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4247         }
4248
4249         /* Disable the Tx DMA engine on 82599 and X540 */
4250         switch (hw->mac.type) {
4251         case ixgbe_mac_82599EB:
4252         case ixgbe_mac_X540:
4253                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4254                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4255                                  ~IXGBE_DMATXCTL_TE));
4256                 break;
4257         default:
4258                 break;
4259         }
4260
4261         if (!pci_channel_offline(adapter->pdev))
4262                 ixgbe_reset(adapter);
4263
4264         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4265         if (hw->mac.ops.disable_tx_laser &&
4266             ((hw->phy.multispeed_fiber) ||
4267              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4268               (hw->mac.type == ixgbe_mac_82599EB))))
4269                 hw->mac.ops.disable_tx_laser(hw);
4270
4271         ixgbe_clean_all_tx_rings(adapter);
4272         ixgbe_clean_all_rx_rings(adapter);
4273
4274 #ifdef CONFIG_IXGBE_DCA
4275         /* since we reset the hardware DCA settings were cleared */
4276         ixgbe_setup_dca(adapter);
4277 #endif
4278 }
4279
4280 /**
4281  * ixgbe_poll - NAPI Rx polling callback
4282  * @napi: structure for representing this polling device
4283  * @budget: how many packets driver is allowed to clean
4284  *
4285  * This function is used for legacy and MSI, NAPI mode
4286  **/
4287 static int ixgbe_poll(struct napi_struct *napi, int budget)
4288 {
4289         struct ixgbe_q_vector *q_vector =
4290                                 container_of(napi, struct ixgbe_q_vector, napi);
4291         struct ixgbe_adapter *adapter = q_vector->adapter;
4292         int tx_clean_complete, work_done = 0;
4293
4294 #ifdef CONFIG_IXGBE_DCA
4295         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4296                 ixgbe_update_dca(q_vector);
4297 #endif
4298
4299         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4300         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4301
4302         if (!tx_clean_complete)
4303                 work_done = budget;
4304
4305         /* If budget not fully consumed, exit the polling mode */
4306         if (work_done < budget) {
4307                 napi_complete(napi);
4308                 if (adapter->rx_itr_setting & 1)
4309                         ixgbe_set_itr(adapter);
4310                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4311                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4312         }
4313         return work_done;
4314 }
4315
4316 /**
4317  * ixgbe_tx_timeout - Respond to a Tx Hang
4318  * @netdev: network interface device structure
4319  **/
4320 static void ixgbe_tx_timeout(struct net_device *netdev)
4321 {
4322         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4323
4324         /* Do the reset outside of interrupt context */
4325         ixgbe_tx_timeout_reset(adapter);
4326 }
4327
4328 /**
4329  * ixgbe_set_rss_queues: Allocate queues for RSS
4330  * @adapter: board private structure to initialize
4331  *
4332  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4333  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4334  *
4335  **/
4336 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4337 {
4338         bool ret = false;
4339         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4340
4341         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4342                 f->mask = 0xF;
4343                 adapter->num_rx_queues = f->indices;
4344                 adapter->num_tx_queues = f->indices;
4345                 ret = true;
4346         } else {
4347                 ret = false;
4348         }
4349
4350         return ret;
4351 }
4352
4353 /**
4354  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4355  * @adapter: board private structure to initialize
4356  *
4357  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4358  * to the original CPU that initiated the Tx session.  This runs in addition
4359  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4360  * Rx load across CPUs using RSS.
4361  *
4362  **/
4363 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4364 {
4365         bool ret = false;
4366         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4367
4368         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4369         f_fdir->mask = 0;
4370
4371         /* Flow Director must have RSS enabled */
4372         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4373             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4374              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4375                 adapter->num_tx_queues = f_fdir->indices;
4376                 adapter->num_rx_queues = f_fdir->indices;
4377                 ret = true;
4378         } else {
4379                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4380                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4381         }
4382         return ret;
4383 }
4384
4385 #ifdef IXGBE_FCOE
4386 /**
4387  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4388  * @adapter: board private structure to initialize
4389  *
4390  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4391  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4392  * rx queues out of the max number of rx queues, instead, it is used as the
4393  * index of the first rx queue used by FCoE.
4394  *
4395  **/
4396 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4397 {
4398         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4399
4400         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4401                 return false;
4402
4403         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4404 #ifdef CONFIG_IXGBE_DCB
4405                 int tc;
4406                 struct net_device *dev = adapter->netdev;
4407
4408                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4409                 f->indices = dev->tc_to_txq[tc].count;
4410                 f->mask = dev->tc_to_txq[tc].offset;
4411 #endif
4412         } else {
4413                 f->indices = min((int)num_online_cpus(), f->indices);
4414
4415                 adapter->num_rx_queues = 1;
4416                 adapter->num_tx_queues = 1;
4417
4418                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4419                         e_info(probe, "FCoE enabled with RSS\n");
4420                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4421                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4422                                 ixgbe_set_fdir_queues(adapter);
4423                         else
4424                                 ixgbe_set_rss_queues(adapter);
4425                 }
4426                 /* adding FCoE rx rings to the end */
4427                 f->mask = adapter->num_rx_queues;
4428                 adapter->num_rx_queues += f->indices;
4429                 adapter->num_tx_queues += f->indices;
4430         }
4431
4432         return true;
4433 }
4434 #endif /* IXGBE_FCOE */
4435
4436 #ifdef CONFIG_IXGBE_DCB
4437 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4438 {
4439         bool ret = false;
4440         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4441         int i, q;
4442
4443         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4444                 return ret;
4445
4446         f->indices = 0;
4447         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4448                 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4449                 f->indices += q;
4450         }
4451
4452         f->mask = 0x7 << 3;
4453         adapter->num_rx_queues = f->indices;
4454         adapter->num_tx_queues = f->indices;
4455         ret = true;
4456
4457 #ifdef IXGBE_FCOE
4458         /* FCoE enabled queues require special configuration done through
4459          * configure_fcoe() and others. Here we map FCoE indices onto the
4460          * DCB queue pairs allowing FCoE to own configuration later.
4461          */
4462         ixgbe_set_fcoe_queues(adapter);
4463 #endif
4464
4465         return ret;
4466 }
4467 #endif
4468
4469 /**
4470  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4471  * @adapter: board private structure to initialize
4472  *
4473  * IOV doesn't actually use anything, so just NAK the
4474  * request for now and let the other queue routines
4475  * figure out what to do.
4476  */
4477 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4478 {
4479         return false;
4480 }
4481
4482 /*
4483  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4484  * @adapter: board private structure to initialize
4485  *
4486  * This is the top level queue allocation routine.  The order here is very
4487  * important, starting with the "most" number of features turned on at once,
4488  * and ending with the smallest set of features.  This way large combinations
4489  * can be allocated if they're turned on, and smaller combinations are the
4490  * fallthrough conditions.
4491  *
4492  **/
4493 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4494 {
4495         /* Start with base case */
4496         adapter->num_rx_queues = 1;
4497         adapter->num_tx_queues = 1;
4498         adapter->num_rx_pools = adapter->num_rx_queues;
4499         adapter->num_rx_queues_per_pool = 1;
4500
4501         if (ixgbe_set_sriov_queues(adapter))
4502                 goto done;
4503
4504 #ifdef CONFIG_IXGBE_DCB
4505         if (ixgbe_set_dcb_queues(adapter))
4506                 goto done;
4507
4508 #endif
4509 #ifdef IXGBE_FCOE
4510         if (ixgbe_set_fcoe_queues(adapter))
4511                 goto done;
4512
4513 #endif /* IXGBE_FCOE */
4514         if (ixgbe_set_fdir_queues(adapter))
4515                 goto done;
4516
4517         if (ixgbe_set_rss_queues(adapter))
4518                 goto done;
4519
4520         /* fallback to base case */
4521         adapter->num_rx_queues = 1;
4522         adapter->num_tx_queues = 1;
4523
4524 done:
4525         /* Notify the stack of the (possibly) reduced queue counts. */
4526         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4527         return netif_set_real_num_rx_queues(adapter->netdev,
4528                                             adapter->num_rx_queues);
4529 }
4530
4531 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4532                                        int vectors)
4533 {
4534         int err, vector_threshold;
4535
4536         /* We'll want at least 3 (vector_threshold):
4537          * 1) TxQ[0] Cleanup
4538          * 2) RxQ[0] Cleanup
4539          * 3) Other (Link Status Change, etc.)
4540          * 4) TCP Timer (optional)
4541          */
4542         vector_threshold = MIN_MSIX_COUNT;
4543
4544         /* The more we get, the more we will assign to Tx/Rx Cleanup
4545          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4546          * Right now, we simply care about how many we'll get; we'll
4547          * set them up later while requesting irq's.
4548          */
4549         while (vectors >= vector_threshold) {
4550                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4551                                       vectors);
4552                 if (!err) /* Success in acquiring all requested vectors. */
4553                         break;
4554                 else if (err < 0)
4555                         vectors = 0; /* Nasty failure, quit now */
4556                 else /* err == number of vectors we should try again with */
4557                         vectors = err;
4558         }
4559
4560         if (vectors < vector_threshold) {
4561                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4562                  * This just means we'll go with either a single MSI
4563                  * vector or fall back to legacy interrupts.
4564                  */
4565                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4566                              "Unable to allocate MSI-X interrupts\n");
4567                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4568                 kfree(adapter->msix_entries);
4569                 adapter->msix_entries = NULL;
4570         } else {
4571                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4572                 /*
4573                  * Adjust for only the vectors we'll use, which is minimum
4574                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4575                  * vectors we were allocated.
4576                  */
4577                 adapter->num_msix_vectors = min(vectors,
4578                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4579         }
4580 }
4581
4582 /**
4583  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4584  * @adapter: board private structure to initialize
4585  *
4586  * Cache the descriptor ring offsets for RSS to the assigned rings.
4587  *
4588  **/
4589 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4590 {
4591         int i;
4592
4593         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4594                 return false;
4595
4596         for (i = 0; i < adapter->num_rx_queues; i++)
4597                 adapter->rx_ring[i]->reg_idx = i;
4598         for (i = 0; i < adapter->num_tx_queues; i++)
4599                 adapter->tx_ring[i]->reg_idx = i;
4600
4601         return true;
4602 }
4603
4604 #ifdef CONFIG_IXGBE_DCB
4605
4606 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4607 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4608                                     unsigned int *tx, unsigned int *rx)
4609 {
4610         struct net_device *dev = adapter->netdev;
4611         struct ixgbe_hw *hw = &adapter->hw;
4612         u8 num_tcs = netdev_get_num_tc(dev);
4613
4614         *tx = 0;
4615         *rx = 0;
4616
4617         switch (hw->mac.type) {
4618         case ixgbe_mac_82598EB:
4619                 *tx = tc << 3;
4620                 *rx = tc << 2;
4621                 break;
4622         case ixgbe_mac_82599EB:
4623         case ixgbe_mac_X540:
4624                 if (num_tcs == 8) {
4625                         if (tc < 3) {
4626                                 *tx = tc << 5;
4627                                 *rx = tc << 4;
4628                         } else if (tc <  5) {
4629                                 *tx = ((tc + 2) << 4);
4630                                 *rx = tc << 4;
4631                         } else if (tc < num_tcs) {
4632                                 *tx = ((tc + 8) << 3);
4633                                 *rx = tc << 4;
4634                         }
4635                 } else if (num_tcs == 4) {
4636                         *rx =  tc << 5;
4637                         switch (tc) {
4638                         case 0:
4639                                 *tx =  0;
4640                                 break;
4641                         case 1:
4642                                 *tx = 64;
4643                                 break;
4644                         case 2:
4645                                 *tx = 96;
4646                                 break;
4647                         case 3:
4648                                 *tx = 112;
4649                                 break;
4650                         default:
4651                                 break;
4652                         }
4653                 }
4654                 break;
4655         default:
4656                 break;
4657         }
4658 }
4659
4660 #define IXGBE_MAX_Q_PER_TC      (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4661
4662 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4663  * classes.
4664  *
4665  * @netdev: net device to configure
4666  * @tc: number of traffic classes to enable
4667  */
4668 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4669 {
4670         int i;
4671         unsigned int q, offset = 0;
4672
4673         if (!tc) {
4674                 netdev_reset_tc(dev);
4675         } else {
4676                 struct ixgbe_adapter *adapter = netdev_priv(dev);
4677
4678                 /* Hardware supports up to 8 traffic classes */
4679                 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4680                         return -EINVAL;
4681
4682                 /* Partition Tx queues evenly amongst traffic classes */
4683                 for (i = 0; i < tc; i++) {
4684                         q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4685                         netdev_set_prio_tc_map(dev, i, i);
4686                         netdev_set_tc_queue(dev, i, q, offset);
4687                         offset += q;
4688                 }
4689
4690                 /* This enables multiple traffic class support in the hardware
4691                  * which defaults to strict priority transmission by default.
4692                  * If traffic classes are already enabled perhaps through DCB
4693                  * code path then existing configuration will be used.
4694                  */
4695                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4696                     dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4697                         struct ieee_ets ets = {
4698                                         .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4699                                               };
4700                         u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4701
4702                         dev->dcbnl_ops->setdcbx(dev, mode);
4703                         dev->dcbnl_ops->ieee_setets(dev, &ets);
4704                 }
4705         }
4706         return 0;
4707 }
4708
4709 /**
4710  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4711  * @adapter: board private structure to initialize
4712  *
4713  * Cache the descriptor ring offsets for DCB to the assigned rings.
4714  *
4715  **/
4716 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4717 {
4718         struct net_device *dev = adapter->netdev;
4719         int i, j, k;
4720         u8 num_tcs = netdev_get_num_tc(dev);
4721
4722         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4723                 return false;
4724
4725         for (i = 0, k = 0; i < num_tcs; i++) {
4726                 unsigned int tx_s, rx_s;
4727                 u16 count = dev->tc_to_txq[i].count;
4728
4729                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4730                 for (j = 0; j < count; j++, k++) {
4731                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4732                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4733                         adapter->tx_ring[k]->dcb_tc = i;
4734                         adapter->rx_ring[k]->dcb_tc = i;
4735                 }
4736         }
4737
4738         return true;
4739 }
4740 #endif
4741
4742 /**
4743  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4744  * @adapter: board private structure to initialize
4745  *
4746  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4747  *
4748  **/
4749 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4750 {
4751         int i;
4752         bool ret = false;
4753
4754         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4755             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4756              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4757                 for (i = 0; i < adapter->num_rx_queues; i++)
4758                         adapter->rx_ring[i]->reg_idx = i;
4759                 for (i = 0; i < adapter->num_tx_queues; i++)
4760                         adapter->tx_ring[i]->reg_idx = i;
4761                 ret = true;
4762         }
4763
4764         return ret;
4765 }
4766
4767 #ifdef IXGBE_FCOE
4768 /**
4769  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4770  * @adapter: board private structure to initialize
4771  *
4772  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4773  *
4774  */
4775 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4776 {
4777         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4778         int i;
4779         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4780
4781         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4782                 return false;
4783
4784         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4785                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4786                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4787                         ixgbe_cache_ring_fdir(adapter);
4788                 else
4789                         ixgbe_cache_ring_rss(adapter);
4790
4791                 fcoe_rx_i = f->mask;
4792                 fcoe_tx_i = f->mask;
4793         }
4794         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4795                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4796                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4797         }
4798         return true;
4799 }
4800
4801 #endif /* IXGBE_FCOE */
4802 /**
4803  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4804  * @adapter: board private structure to initialize
4805  *
4806  * SR-IOV doesn't use any descriptor rings but changes the default if
4807  * no other mapping is used.
4808  *
4809  */
4810 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4811 {
4812         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4813         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4814         if (adapter->num_vfs)
4815                 return true;
4816         else
4817                 return false;
4818 }
4819
4820 /**
4821  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4822  * @adapter: board private structure to initialize
4823  *
4824  * Once we know the feature-set enabled for the device, we'll cache
4825  * the register offset the descriptor ring is assigned to.
4826  *
4827  * Note, the order the various feature calls is important.  It must start with
4828  * the "most" features enabled at the same time, then trickle down to the
4829  * least amount of features turned on at once.
4830  **/
4831 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4832 {
4833         /* start with default case */
4834         adapter->rx_ring[0]->reg_idx = 0;
4835         adapter->tx_ring[0]->reg_idx = 0;
4836
4837         if (ixgbe_cache_ring_sriov(adapter))
4838                 return;
4839
4840 #ifdef CONFIG_IXGBE_DCB
4841         if (ixgbe_cache_ring_dcb(adapter))
4842                 return;
4843 #endif
4844
4845 #ifdef IXGBE_FCOE
4846         if (ixgbe_cache_ring_fcoe(adapter))
4847                 return;
4848 #endif /* IXGBE_FCOE */
4849
4850         if (ixgbe_cache_ring_fdir(adapter))
4851                 return;
4852
4853         if (ixgbe_cache_ring_rss(adapter))
4854                 return;
4855 }
4856
4857 /**
4858  * ixgbe_alloc_queues - Allocate memory for all rings
4859  * @adapter: board private structure to initialize
4860  *
4861  * We allocate one ring per queue at run-time since we don't know the
4862  * number of queues at compile-time.  The polling_netdev array is
4863  * intended for Multiqueue, but should work fine with a single queue.
4864  **/
4865 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4866 {
4867         int rx = 0, tx = 0, nid = adapter->node;
4868
4869         if (nid < 0 || !node_online(nid))
4870                 nid = first_online_node;
4871
4872         for (; tx < adapter->num_tx_queues; tx++) {
4873                 struct ixgbe_ring *ring;
4874
4875                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4876                 if (!ring)
4877                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4878                 if (!ring)
4879                         goto err_allocation;
4880                 ring->count = adapter->tx_ring_count;
4881                 ring->queue_index = tx;
4882                 ring->numa_node = nid;
4883                 ring->dev = &adapter->pdev->dev;
4884                 ring->netdev = adapter->netdev;
4885
4886                 adapter->tx_ring[tx] = ring;
4887         }
4888
4889         for (; rx < adapter->num_rx_queues; rx++) {
4890                 struct ixgbe_ring *ring;
4891
4892                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4893                 if (!ring)
4894                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4895                 if (!ring)
4896                         goto err_allocation;
4897                 ring->count = adapter->rx_ring_count;
4898                 ring->queue_index = rx;
4899                 ring->numa_node = nid;
4900                 ring->dev = &adapter->pdev->dev;
4901                 ring->netdev = adapter->netdev;
4902
4903                 adapter->rx_ring[rx] = ring;
4904         }
4905
4906         ixgbe_cache_ring_register(adapter);
4907
4908         return 0;
4909
4910 err_allocation:
4911         while (tx)
4912                 kfree(adapter->tx_ring[--tx]);
4913
4914         while (rx)
4915                 kfree(adapter->rx_ring[--rx]);
4916         return -ENOMEM;
4917 }
4918
4919 /**
4920  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4921  * @adapter: board private structure to initialize
4922  *
4923  * Attempt to configure the interrupts using the best available
4924  * capabilities of the hardware and the kernel.
4925  **/
4926 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4927 {
4928         struct ixgbe_hw *hw = &adapter->hw;
4929         int err = 0;
4930         int vector, v_budget;
4931
4932         /*
4933          * It's easy to be greedy for MSI-X vectors, but it really
4934          * doesn't do us much good if we have a lot more vectors
4935          * than CPU's.  So let's be conservative and only ask for
4936          * (roughly) the same number of vectors as there are CPU's.
4937          */
4938         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4939                        (int)num_online_cpus()) + NON_Q_VECTORS;
4940
4941         /*
4942          * At the same time, hardware can only support a maximum of
4943          * hw.mac->max_msix_vectors vectors.  With features
4944          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4945          * descriptor queues supported by our device.  Thus, we cap it off in
4946          * those rare cases where the cpu count also exceeds our vector limit.
4947          */
4948         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4949
4950         /* A failure in MSI-X entry allocation isn't fatal, but it does
4951          * mean we disable MSI-X capabilities of the adapter. */
4952         adapter->msix_entries = kcalloc(v_budget,
4953                                         sizeof(struct msix_entry), GFP_KERNEL);
4954         if (adapter->msix_entries) {
4955                 for (vector = 0; vector < v_budget; vector++)
4956                         adapter->msix_entries[vector].entry = vector;
4957
4958                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4959
4960                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4961                         goto out;
4962         }
4963
4964         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4965         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4966         if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4967                               IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4968                 e_err(probe,
4969                       "Flow Director is not supported while multiple "
4970                       "queues are disabled.  Disabling Flow Director\n");
4971         }
4972         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4973         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4974         adapter->atr_sample_rate = 0;
4975         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4976                 ixgbe_disable_sriov(adapter);
4977
4978         err = ixgbe_set_num_queues(adapter);
4979         if (err)
4980                 return err;
4981
4982         err = pci_enable_msi(adapter->pdev);
4983         if (!err) {
4984                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4985         } else {
4986                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4987                              "Unable to allocate MSI interrupt, "
4988                              "falling back to legacy.  Error: %d\n", err);
4989                 /* reset err */
4990                 err = 0;
4991         }
4992
4993 out:
4994         return err;
4995 }
4996
4997 /**
4998  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4999  * @adapter: board private structure to initialize
5000  *
5001  * We allocate one q_vector per queue interrupt.  If allocation fails we
5002  * return -ENOMEM.
5003  **/
5004 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
5005 {
5006         int q_idx, num_q_vectors;
5007         struct ixgbe_q_vector *q_vector;
5008         int (*poll)(struct napi_struct *, int);
5009
5010         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5011                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5012                 poll = &ixgbe_clean_rxtx_many;
5013         } else {
5014                 num_q_vectors = 1;
5015                 poll = &ixgbe_poll;
5016         }
5017
5018         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5019                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
5020                                         GFP_KERNEL, adapter->node);
5021                 if (!q_vector)
5022                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
5023                                            GFP_KERNEL);
5024                 if (!q_vector)
5025                         goto err_out;
5026                 q_vector->adapter = adapter;
5027                 if (q_vector->txr_count && !q_vector->rxr_count)
5028                         q_vector->eitr = adapter->tx_eitr_param;
5029                 else
5030                         q_vector->eitr = adapter->rx_eitr_param;
5031                 q_vector->v_idx = q_idx;
5032                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
5033                 adapter->q_vector[q_idx] = q_vector;
5034         }
5035
5036         return 0;
5037
5038 err_out:
5039         while (q_idx) {
5040                 q_idx--;
5041                 q_vector = adapter->q_vector[q_idx];
5042                 netif_napi_del(&q_vector->napi);
5043                 kfree(q_vector);
5044                 adapter->q_vector[q_idx] = NULL;
5045         }
5046         return -ENOMEM;
5047 }
5048
5049 /**
5050  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5051  * @adapter: board private structure to initialize
5052  *
5053  * This function frees the memory allocated to the q_vectors.  In addition if
5054  * NAPI is enabled it will delete any references to the NAPI struct prior
5055  * to freeing the q_vector.
5056  **/
5057 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5058 {
5059         int q_idx, num_q_vectors;
5060
5061         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5062                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5063         else
5064                 num_q_vectors = 1;
5065
5066         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5067                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5068                 adapter->q_vector[q_idx] = NULL;
5069                 netif_napi_del(&q_vector->napi);
5070                 kfree(q_vector);
5071         }
5072 }
5073
5074 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5075 {
5076         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5077                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5078                 pci_disable_msix(adapter->pdev);
5079                 kfree(adapter->msix_entries);
5080                 adapter->msix_entries = NULL;
5081         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5082                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5083                 pci_disable_msi(adapter->pdev);
5084         }
5085 }
5086
5087 /**
5088  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5089  * @adapter: board private structure to initialize
5090  *
5091  * We determine which interrupt scheme to use based on...
5092  * - Kernel support (MSI, MSI-X)
5093  *   - which can be user-defined (via MODULE_PARAM)
5094  * - Hardware queue count (num_*_queues)
5095  *   - defined by miscellaneous hardware support/features (RSS, etc.)
5096  **/
5097 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5098 {
5099         int err;
5100
5101         /* Number of supported queues */
5102         err = ixgbe_set_num_queues(adapter);
5103         if (err)
5104                 return err;
5105
5106         err = ixgbe_set_interrupt_capability(adapter);
5107         if (err) {
5108                 e_dev_err("Unable to setup interrupt capabilities\n");
5109                 goto err_set_interrupt;
5110         }
5111
5112         err = ixgbe_alloc_q_vectors(adapter);
5113         if (err) {
5114                 e_dev_err("Unable to allocate memory for queue vectors\n");
5115                 goto err_alloc_q_vectors;
5116         }
5117
5118         err = ixgbe_alloc_queues(adapter);
5119         if (err) {
5120                 e_dev_err("Unable to allocate memory for queues\n");
5121                 goto err_alloc_queues;
5122         }
5123
5124         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5125                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5126                    adapter->num_rx_queues, adapter->num_tx_queues);
5127
5128         set_bit(__IXGBE_DOWN, &adapter->state);
5129
5130         return 0;
5131
5132 err_alloc_queues:
5133         ixgbe_free_q_vectors(adapter);
5134 err_alloc_q_vectors:
5135         ixgbe_reset_interrupt_capability(adapter);
5136 err_set_interrupt:
5137         return err;
5138 }
5139
5140 /**
5141  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5142  * @adapter: board private structure to clear interrupt scheme on
5143  *
5144  * We go through and clear interrupt specific resources and reset the structure
5145  * to pre-load conditions
5146  **/
5147 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5148 {
5149         int i;
5150
5151         for (i = 0; i < adapter->num_tx_queues; i++) {
5152                 kfree(adapter->tx_ring[i]);
5153                 adapter->tx_ring[i] = NULL;
5154         }
5155         for (i = 0; i < adapter->num_rx_queues; i++) {
5156                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5157
5158                 /* ixgbe_get_stats64() might access this ring, we must wait
5159                  * a grace period before freeing it.
5160                  */
5161                 kfree_rcu(ring, rcu);
5162                 adapter->rx_ring[i] = NULL;
5163         }
5164
5165         adapter->num_tx_queues = 0;
5166         adapter->num_rx_queues = 0;
5167
5168         ixgbe_free_q_vectors(adapter);
5169         ixgbe_reset_interrupt_capability(adapter);
5170 }
5171
5172 /**
5173  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5174  * @adapter: board private structure to initialize
5175  *
5176  * ixgbe_sw_init initializes the Adapter private data structure.
5177  * Fields are initialized based on PCI device information and
5178  * OS network device settings (MTU size).
5179  **/
5180 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5181 {
5182         struct ixgbe_hw *hw = &adapter->hw;
5183         struct pci_dev *pdev = adapter->pdev;
5184         struct net_device *dev = adapter->netdev;
5185         unsigned int rss;
5186 #ifdef CONFIG_IXGBE_DCB
5187         int j;
5188         struct tc_configuration *tc;
5189 #endif
5190         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5191
5192         /* PCI config space info */
5193
5194         hw->vendor_id = pdev->vendor;
5195         hw->device_id = pdev->device;
5196         hw->revision_id = pdev->revision;
5197         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5198         hw->subsystem_device_id = pdev->subsystem_device;
5199
5200         /* Set capability flags */
5201         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5202         adapter->ring_feature[RING_F_RSS].indices = rss;
5203         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5204         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5205         switch (hw->mac.type) {
5206         case ixgbe_mac_82598EB:
5207                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5208                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5209                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5210                 break;
5211         case ixgbe_mac_82599EB:
5212         case ixgbe_mac_X540:
5213                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5214                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5215                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5216                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5217                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5218                 /* n-tuple support exists, always init our spinlock */
5219                 spin_lock_init(&adapter->fdir_perfect_lock);
5220                 /* Flow Director hash filters enabled */
5221                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5222                 adapter->atr_sample_rate = 20;
5223                 adapter->ring_feature[RING_F_FDIR].indices =
5224                                                          IXGBE_MAX_FDIR_INDICES;
5225                 adapter->fdir_pballoc = 0;
5226 #ifdef IXGBE_FCOE
5227                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5228                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5229                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5230 #ifdef CONFIG_IXGBE_DCB
5231                 /* Default traffic class to use for FCoE */
5232                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5233                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5234 #endif
5235 #endif /* IXGBE_FCOE */
5236                 break;
5237         default:
5238                 break;
5239         }
5240
5241 #ifdef CONFIG_IXGBE_DCB
5242         /* Configure DCB traffic classes */
5243         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5244                 tc = &adapter->dcb_cfg.tc_config[j];
5245                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5246                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5247                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5248                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5249                 tc->dcb_pfc = pfc_disabled;
5250         }
5251         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5252         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5253         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5254         adapter->dcb_cfg.pfc_mode_enable = false;
5255         adapter->dcb_set_bitmap = 0x00;
5256         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5257         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5258                            MAX_TRAFFIC_CLASS);
5259
5260 #endif
5261
5262         /* default flow control settings */
5263         hw->fc.requested_mode = ixgbe_fc_full;
5264         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5265 #ifdef CONFIG_DCB
5266         adapter->last_lfc_mode = hw->fc.current_mode;
5267 #endif
5268         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5269         hw->fc.low_water = FC_LOW_WATER(max_frame);
5270         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5271         hw->fc.send_xon = true;
5272         hw->fc.disable_fc_autoneg = false;
5273
5274         /* enable itr by default in dynamic mode */
5275         adapter->rx_itr_setting = 1;
5276         adapter->rx_eitr_param = 20000;
5277         adapter->tx_itr_setting = 1;
5278         adapter->tx_eitr_param = 10000;
5279
5280         /* set defaults for eitr in MegaBytes */
5281         adapter->eitr_low = 10;
5282         adapter->eitr_high = 20;
5283
5284         /* set default ring sizes */
5285         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5286         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5287
5288         /* initialize eeprom parameters */
5289         if (ixgbe_init_eeprom_params_generic(hw)) {
5290                 e_dev_err("EEPROM initialization failed\n");
5291                 return -EIO;
5292         }
5293
5294         /* enable rx csum by default */
5295         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5296
5297         /* get assigned NUMA node */
5298         adapter->node = dev_to_node(&pdev->dev);
5299
5300         set_bit(__IXGBE_DOWN, &adapter->state);
5301
5302         return 0;
5303 }
5304
5305 /**
5306  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5307  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5308  *
5309  * Return 0 on success, negative on failure
5310  **/
5311 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5312 {
5313         struct device *dev = tx_ring->dev;
5314         int size;
5315
5316         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5317         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5318         if (!tx_ring->tx_buffer_info)
5319                 tx_ring->tx_buffer_info = vzalloc(size);
5320         if (!tx_ring->tx_buffer_info)
5321                 goto err;
5322
5323         /* round up to nearest 4K */
5324         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5325         tx_ring->size = ALIGN(tx_ring->size, 4096);
5326
5327         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5328                                            &tx_ring->dma, GFP_KERNEL);
5329         if (!tx_ring->desc)
5330                 goto err;
5331
5332         tx_ring->next_to_use = 0;
5333         tx_ring->next_to_clean = 0;
5334         tx_ring->work_limit = tx_ring->count;
5335         return 0;
5336
5337 err:
5338         vfree(tx_ring->tx_buffer_info);
5339         tx_ring->tx_buffer_info = NULL;
5340         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5341         return -ENOMEM;
5342 }
5343
5344 /**
5345  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5346  * @adapter: board private structure
5347  *
5348  * If this function returns with an error, then it's possible one or
5349  * more of the rings is populated (while the rest are not).  It is the
5350  * callers duty to clean those orphaned rings.
5351  *
5352  * Return 0 on success, negative on failure
5353  **/
5354 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5355 {
5356         int i, err = 0;
5357
5358         for (i = 0; i < adapter->num_tx_queues; i++) {
5359                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5360                 if (!err)
5361                         continue;
5362                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5363                 break;
5364         }
5365
5366         return err;
5367 }
5368
5369 /**
5370  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5371  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5372  *
5373  * Returns 0 on success, negative on failure
5374  **/
5375 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5376 {
5377         struct device *dev = rx_ring->dev;
5378         int size;
5379
5380         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5381         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5382         if (!rx_ring->rx_buffer_info)
5383                 rx_ring->rx_buffer_info = vzalloc(size);
5384         if (!rx_ring->rx_buffer_info)
5385                 goto err;
5386
5387         /* Round up to nearest 4K */
5388         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5389         rx_ring->size = ALIGN(rx_ring->size, 4096);
5390
5391         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5392                                            &rx_ring->dma, GFP_KERNEL);
5393
5394         if (!rx_ring->desc)
5395                 goto err;
5396
5397         rx_ring->next_to_clean = 0;
5398         rx_ring->next_to_use = 0;
5399
5400         return 0;
5401 err:
5402         vfree(rx_ring->rx_buffer_info);
5403         rx_ring->rx_buffer_info = NULL;
5404         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5405         return -ENOMEM;
5406 }
5407
5408 /**
5409  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5410  * @adapter: board private structure
5411  *
5412  * If this function returns with an error, then it's possible one or
5413  * more of the rings is populated (while the rest are not).  It is the
5414  * callers duty to clean those orphaned rings.
5415  *
5416  * Return 0 on success, negative on failure
5417  **/
5418 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5419 {
5420         int i, err = 0;
5421
5422         for (i = 0; i < adapter->num_rx_queues; i++) {
5423                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5424                 if (!err)
5425                         continue;
5426                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5427                 break;
5428         }
5429
5430         return err;
5431 }
5432
5433 /**
5434  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5435  * @tx_ring: Tx descriptor ring for a specific queue
5436  *
5437  * Free all transmit software resources
5438  **/
5439 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5440 {
5441         ixgbe_clean_tx_ring(tx_ring);
5442
5443         vfree(tx_ring->tx_buffer_info);
5444         tx_ring->tx_buffer_info = NULL;
5445
5446         /* if not set, then don't free */
5447         if (!tx_ring->desc)
5448                 return;
5449
5450         dma_free_coherent(tx_ring->dev, tx_ring->size,
5451                           tx_ring->desc, tx_ring->dma);
5452
5453         tx_ring->desc = NULL;
5454 }
5455
5456 /**
5457  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5458  * @adapter: board private structure
5459  *
5460  * Free all transmit software resources
5461  **/
5462 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5463 {
5464         int i;
5465
5466         for (i = 0; i < adapter->num_tx_queues; i++)
5467                 if (adapter->tx_ring[i]->desc)
5468                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5469 }
5470
5471 /**
5472  * ixgbe_free_rx_resources - Free Rx Resources
5473  * @rx_ring: ring to clean the resources from
5474  *
5475  * Free all receive software resources
5476  **/
5477 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5478 {
5479         ixgbe_clean_rx_ring(rx_ring);
5480
5481         vfree(rx_ring->rx_buffer_info);
5482         rx_ring->rx_buffer_info = NULL;
5483
5484         /* if not set, then don't free */
5485         if (!rx_ring->desc)
5486                 return;
5487
5488         dma_free_coherent(rx_ring->dev, rx_ring->size,
5489                           rx_ring->desc, rx_ring->dma);
5490
5491         rx_ring->desc = NULL;
5492 }
5493
5494 /**
5495  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5496  * @adapter: board private structure
5497  *
5498  * Free all receive software resources
5499  **/
5500 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5501 {
5502         int i;
5503
5504         for (i = 0; i < adapter->num_rx_queues; i++)
5505                 if (adapter->rx_ring[i]->desc)
5506                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5507 }
5508
5509 /**
5510  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5511  * @netdev: network interface device structure
5512  * @new_mtu: new value for maximum frame size
5513  *
5514  * Returns 0 on success, negative on failure
5515  **/
5516 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5517 {
5518         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5519         struct ixgbe_hw *hw = &adapter->hw;
5520         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5521
5522         /* MTU < 68 is an error and causes problems on some kernels */
5523         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5524             hw->mac.type != ixgbe_mac_X540) {
5525                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5526                         return -EINVAL;
5527         } else {
5528                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5529                         return -EINVAL;
5530         }
5531
5532         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5533         /* must set new MTU before calling down or up */
5534         netdev->mtu = new_mtu;
5535
5536         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5537         hw->fc.low_water = FC_LOW_WATER(max_frame);
5538
5539         if (netif_running(netdev))
5540                 ixgbe_reinit_locked(adapter);
5541
5542         return 0;
5543 }
5544
5545 /**
5546  * ixgbe_open - Called when a network interface is made active
5547  * @netdev: network interface device structure
5548  *
5549  * Returns 0 on success, negative value on failure
5550  *
5551  * The open entry point is called when a network interface is made
5552  * active by the system (IFF_UP).  At this point all resources needed
5553  * for transmit and receive operations are allocated, the interrupt
5554  * handler is registered with the OS, the watchdog timer is started,
5555  * and the stack is notified that the interface is ready.
5556  **/
5557 static int ixgbe_open(struct net_device *netdev)
5558 {
5559         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5560         int err;
5561
5562         /* disallow open during test */
5563         if (test_bit(__IXGBE_TESTING, &adapter->state))
5564                 return -EBUSY;
5565
5566         netif_carrier_off(netdev);
5567
5568         /* allocate transmit descriptors */
5569         err = ixgbe_setup_all_tx_resources(adapter);
5570         if (err)
5571                 goto err_setup_tx;
5572
5573         /* allocate receive descriptors */
5574         err = ixgbe_setup_all_rx_resources(adapter);
5575         if (err)
5576                 goto err_setup_rx;
5577
5578         ixgbe_configure(adapter);
5579
5580         err = ixgbe_request_irq(adapter);
5581         if (err)
5582                 goto err_req_irq;
5583
5584         err = ixgbe_up_complete(adapter);
5585         if (err)
5586                 goto err_up;
5587
5588         netif_tx_start_all_queues(netdev);
5589
5590         return 0;
5591
5592 err_up:
5593         ixgbe_release_hw_control(adapter);
5594         ixgbe_free_irq(adapter);
5595 err_req_irq:
5596 err_setup_rx:
5597         ixgbe_free_all_rx_resources(adapter);
5598 err_setup_tx:
5599         ixgbe_free_all_tx_resources(adapter);
5600         ixgbe_reset(adapter);
5601
5602         return err;
5603 }
5604
5605 /**
5606  * ixgbe_close - Disables a network interface
5607  * @netdev: network interface device structure
5608  *
5609  * Returns 0, this is not allowed to fail
5610  *
5611  * The close entry point is called when an interface is de-activated
5612  * by the OS.  The hardware is still under the drivers control, but
5613  * needs to be disabled.  A global MAC reset is issued to stop the
5614  * hardware, and all transmit and receive resources are freed.
5615  **/
5616 static int ixgbe_close(struct net_device *netdev)
5617 {
5618         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5619
5620         ixgbe_down(adapter);
5621         ixgbe_free_irq(adapter);
5622
5623         ixgbe_free_all_tx_resources(adapter);
5624         ixgbe_free_all_rx_resources(adapter);
5625
5626         ixgbe_release_hw_control(adapter);
5627
5628         return 0;
5629 }
5630
5631 #ifdef CONFIG_PM
5632 static int ixgbe_resume(struct pci_dev *pdev)
5633 {
5634         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5635         struct net_device *netdev = adapter->netdev;
5636         u32 err;
5637
5638         pci_set_power_state(pdev, PCI_D0);
5639         pci_restore_state(pdev);
5640         /*
5641          * pci_restore_state clears dev->state_saved so call
5642          * pci_save_state to restore it.
5643          */
5644         pci_save_state(pdev);
5645
5646         err = pci_enable_device_mem(pdev);
5647         if (err) {
5648                 e_dev_err("Cannot enable PCI device from suspend\n");
5649                 return err;
5650         }
5651         pci_set_master(pdev);
5652
5653         pci_wake_from_d3(pdev, false);
5654
5655         err = ixgbe_init_interrupt_scheme(adapter);
5656         if (err) {
5657                 e_dev_err("Cannot initialize interrupts for device\n");
5658                 return err;
5659         }
5660
5661         ixgbe_reset(adapter);
5662
5663         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5664
5665         if (netif_running(netdev)) {
5666                 err = ixgbe_open(netdev);
5667                 if (err)
5668                         return err;
5669         }
5670
5671         netif_device_attach(netdev);
5672
5673         return 0;
5674 }
5675 #endif /* CONFIG_PM */
5676
5677 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5678 {
5679         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5680         struct net_device *netdev = adapter->netdev;
5681         struct ixgbe_hw *hw = &adapter->hw;
5682         u32 ctrl, fctrl;
5683         u32 wufc = adapter->wol;
5684 #ifdef CONFIG_PM
5685         int retval = 0;
5686 #endif
5687
5688         netif_device_detach(netdev);
5689
5690         if (netif_running(netdev)) {
5691                 ixgbe_down(adapter);
5692                 ixgbe_free_irq(adapter);
5693                 ixgbe_free_all_tx_resources(adapter);
5694                 ixgbe_free_all_rx_resources(adapter);
5695         }
5696
5697         ixgbe_clear_interrupt_scheme(adapter);
5698 #ifdef CONFIG_DCB
5699         kfree(adapter->ixgbe_ieee_pfc);
5700         kfree(adapter->ixgbe_ieee_ets);
5701 #endif
5702
5703 #ifdef CONFIG_PM
5704         retval = pci_save_state(pdev);
5705         if (retval)
5706                 return retval;
5707
5708 #endif
5709         if (wufc) {
5710                 ixgbe_set_rx_mode(netdev);
5711
5712                 /* turn on all-multi mode if wake on multicast is enabled */
5713                 if (wufc & IXGBE_WUFC_MC) {
5714                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5715                         fctrl |= IXGBE_FCTRL_MPE;
5716                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5717                 }
5718
5719                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5720                 ctrl |= IXGBE_CTRL_GIO_DIS;
5721                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5722
5723                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5724         } else {
5725                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5726                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5727         }
5728
5729         switch (hw->mac.type) {
5730         case ixgbe_mac_82598EB:
5731                 pci_wake_from_d3(pdev, false);
5732                 break;
5733         case ixgbe_mac_82599EB:
5734         case ixgbe_mac_X540:
5735                 pci_wake_from_d3(pdev, !!wufc);
5736                 break;
5737         default:
5738                 break;
5739         }
5740
5741         *enable_wake = !!wufc;
5742
5743         ixgbe_release_hw_control(adapter);
5744
5745         pci_disable_device(pdev);
5746
5747         return 0;
5748 }
5749
5750 #ifdef CONFIG_PM
5751 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5752 {
5753         int retval;
5754         bool wake;
5755
5756         retval = __ixgbe_shutdown(pdev, &wake);
5757         if (retval)
5758                 return retval;
5759
5760         if (wake) {
5761                 pci_prepare_to_sleep(pdev);
5762         } else {
5763                 pci_wake_from_d3(pdev, false);
5764                 pci_set_power_state(pdev, PCI_D3hot);
5765         }
5766
5767         return 0;
5768 }
5769 #endif /* CONFIG_PM */
5770
5771 static void ixgbe_shutdown(struct pci_dev *pdev)
5772 {
5773         bool wake;
5774
5775         __ixgbe_shutdown(pdev, &wake);
5776
5777         if (system_state == SYSTEM_POWER_OFF) {
5778                 pci_wake_from_d3(pdev, wake);
5779                 pci_set_power_state(pdev, PCI_D3hot);
5780         }
5781 }
5782
5783 /**
5784  * ixgbe_update_stats - Update the board statistics counters.
5785  * @adapter: board private structure
5786  **/
5787 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5788 {
5789         struct net_device *netdev = adapter->netdev;
5790         struct ixgbe_hw *hw = &adapter->hw;
5791         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5792         u64 total_mpc = 0;
5793         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5794         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5795         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5796         u64 bytes = 0, packets = 0;
5797
5798         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5799             test_bit(__IXGBE_RESETTING, &adapter->state))
5800                 return;
5801
5802         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5803                 u64 rsc_count = 0;
5804                 u64 rsc_flush = 0;
5805                 for (i = 0; i < 16; i++)
5806                         adapter->hw_rx_no_dma_resources +=
5807                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5808                 for (i = 0; i < adapter->num_rx_queues; i++) {
5809                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5810                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5811                 }
5812                 adapter->rsc_total_count = rsc_count;
5813                 adapter->rsc_total_flush = rsc_flush;
5814         }
5815
5816         for (i = 0; i < adapter->num_rx_queues; i++) {
5817                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5818                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5819                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5820                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5821                 bytes += rx_ring->stats.bytes;
5822                 packets += rx_ring->stats.packets;
5823         }
5824         adapter->non_eop_descs = non_eop_descs;
5825         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5826         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5827         netdev->stats.rx_bytes = bytes;
5828         netdev->stats.rx_packets = packets;
5829
5830         bytes = 0;
5831         packets = 0;
5832         /* gather some stats to the adapter struct that are per queue */
5833         for (i = 0; i < adapter->num_tx_queues; i++) {
5834                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5835                 restart_queue += tx_ring->tx_stats.restart_queue;
5836                 tx_busy += tx_ring->tx_stats.tx_busy;
5837                 bytes += tx_ring->stats.bytes;
5838                 packets += tx_ring->stats.packets;
5839         }
5840         adapter->restart_queue = restart_queue;
5841         adapter->tx_busy = tx_busy;
5842         netdev->stats.tx_bytes = bytes;
5843         netdev->stats.tx_packets = packets;
5844
5845         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5846         for (i = 0; i < 8; i++) {
5847                 /* for packet buffers not used, the register should read 0 */
5848                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5849                 missed_rx += mpc;
5850                 hwstats->mpc[i] += mpc;
5851                 total_mpc += hwstats->mpc[i];
5852                 if (hw->mac.type == ixgbe_mac_82598EB)
5853                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5854                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5855                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5856                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5857                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5858                 switch (hw->mac.type) {
5859                 case ixgbe_mac_82598EB:
5860                         hwstats->pxonrxc[i] +=
5861                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5862                         break;
5863                 case ixgbe_mac_82599EB:
5864                 case ixgbe_mac_X540:
5865                         hwstats->pxonrxc[i] +=
5866                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5867                         break;
5868                 default:
5869                         break;
5870                 }
5871                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5872                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5873         }
5874         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5875         /* work around hardware counting issue */
5876         hwstats->gprc -= missed_rx;
5877
5878         ixgbe_update_xoff_received(adapter);
5879
5880         /* 82598 hardware only has a 32 bit counter in the high register */
5881         switch (hw->mac.type) {
5882         case ixgbe_mac_82598EB:
5883                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5884                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5885                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5886                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5887                 break;
5888         case ixgbe_mac_X540:
5889                 /* OS2BMC stats are X540 only*/
5890                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5891                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5892                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5893                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5894         case ixgbe_mac_82599EB:
5895                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5896                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5897                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5898                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5899                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5900                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5901                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5902                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5903                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5904 #ifdef IXGBE_FCOE
5905                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5906                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5907                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5908                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5909                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5910                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5911 #endif /* IXGBE_FCOE */
5912                 break;
5913         default:
5914                 break;
5915         }
5916         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5917         hwstats->bprc += bprc;
5918         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5919         if (hw->mac.type == ixgbe_mac_82598EB)
5920                 hwstats->mprc -= bprc;
5921         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5922         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5923         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5924         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5925         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5926         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5927         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5928         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5929         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5930         hwstats->lxontxc += lxon;
5931         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5932         hwstats->lxofftxc += lxoff;
5933         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5934         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5935         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5936         /*
5937          * 82598 errata - tx of flow control packets is included in tx counters
5938          */
5939         xon_off_tot = lxon + lxoff;
5940         hwstats->gptc -= xon_off_tot;
5941         hwstats->mptc -= xon_off_tot;
5942         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5943         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5944         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5945         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5946         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5947         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5948         hwstats->ptc64 -= xon_off_tot;
5949         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5950         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5951         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5952         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5953         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5954         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5955
5956         /* Fill out the OS statistics structure */
5957         netdev->stats.multicast = hwstats->mprc;
5958
5959         /* Rx Errors */
5960         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5961         netdev->stats.rx_dropped = 0;
5962         netdev->stats.rx_length_errors = hwstats->rlec;
5963         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5964         netdev->stats.rx_missed_errors = total_mpc;
5965 }
5966
5967 /**
5968  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5969  * @adapter - pointer to the device adapter structure
5970  **/
5971 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5972 {
5973         struct ixgbe_hw *hw = &adapter->hw;
5974         int i;
5975
5976         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5977                 return;
5978
5979         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5980
5981         /* if interface is down do nothing */
5982         if (test_bit(__IXGBE_DOWN, &adapter->state))
5983                 return;
5984
5985         /* do nothing if we are not using signature filters */
5986         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5987                 return;
5988
5989         adapter->fdir_overflow++;
5990
5991         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5992                 for (i = 0; i < adapter->num_tx_queues; i++)
5993                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5994                                 &(adapter->tx_ring[i]->state));
5995                 /* re-enable flow director interrupts */
5996                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5997         } else {
5998                 e_err(probe, "failed to finish FDIR re-initialization, "
5999                       "ignored adding FDIR ATR filters\n");
6000         }
6001 }
6002
6003 /**
6004  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6005  * @adapter - pointer to the device adapter structure
6006  *
6007  * This function serves two purposes.  First it strobes the interrupt lines
6008  * in order to make certain interrupts are occuring.  Secondly it sets the
6009  * bits needed to check for TX hangs.  As a result we should immediately
6010  * determine if a hang has occured.
6011  */
6012 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6013 {
6014         struct ixgbe_hw *hw = &adapter->hw;
6015         u64 eics = 0;
6016         int i;
6017
6018         /* If we're down or resetting, just bail */
6019         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6020             test_bit(__IXGBE_RESETTING, &adapter->state))
6021                 return;
6022
6023         /* Force detection of hung controller */
6024         if (netif_carrier_ok(adapter->netdev)) {
6025                 for (i = 0; i < adapter->num_tx_queues; i++)
6026                         set_check_for_tx_hang(adapter->tx_ring[i]);
6027         }
6028
6029         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6030                 /*
6031                  * for legacy and MSI interrupts don't set any bits
6032                  * that are enabled for EIAM, because this operation
6033                  * would set *both* EIMS and EICS for any bit in EIAM
6034                  */
6035                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6036                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6037         } else {
6038                 /* get one bit for every active tx/rx interrupt vector */
6039                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6040                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
6041                         if (qv->rxr_count || qv->txr_count)
6042                                 eics |= ((u64)1 << i);
6043                 }
6044         }
6045
6046         /* Cause software interrupt to ensure rings are cleaned */
6047         ixgbe_irq_rearm_queues(adapter, eics);
6048
6049 }
6050
6051 /**
6052  * ixgbe_watchdog_update_link - update the link status
6053  * @adapter - pointer to the device adapter structure
6054  * @link_speed - pointer to a u32 to store the link_speed
6055  **/
6056 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6057 {
6058         struct ixgbe_hw *hw = &adapter->hw;
6059         u32 link_speed = adapter->link_speed;
6060         bool link_up = adapter->link_up;
6061         int i;
6062
6063         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6064                 return;
6065
6066         if (hw->mac.ops.check_link) {
6067                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6068         } else {
6069                 /* always assume link is up, if no check link function */
6070                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6071                 link_up = true;
6072         }
6073         if (link_up) {
6074                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6075                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6076                                 hw->mac.ops.fc_enable(hw, i);
6077                 } else {
6078                         hw->mac.ops.fc_enable(hw, 0);
6079                 }
6080         }
6081
6082         if (link_up ||
6083             time_after(jiffies, (adapter->link_check_timeout +
6084                                  IXGBE_TRY_LINK_TIMEOUT))) {
6085                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6086                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6087                 IXGBE_WRITE_FLUSH(hw);
6088         }
6089
6090         adapter->link_up = link_up;
6091         adapter->link_speed = link_speed;
6092 }
6093
6094 /**
6095  * ixgbe_watchdog_link_is_up - update netif_carrier status and
6096  *                             print link up message
6097  * @adapter - pointer to the device adapter structure
6098  **/
6099 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6100 {
6101         struct net_device *netdev = adapter->netdev;
6102         struct ixgbe_hw *hw = &adapter->hw;
6103         u32 link_speed = adapter->link_speed;
6104         bool flow_rx, flow_tx;
6105
6106         /* only continue if link was previously down */
6107         if (netif_carrier_ok(netdev))
6108                 return;
6109
6110         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6111
6112         switch (hw->mac.type) {
6113         case ixgbe_mac_82598EB: {
6114                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6115                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6116                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6117                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6118         }
6119                 break;
6120         case ixgbe_mac_X540:
6121         case ixgbe_mac_82599EB: {
6122                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6123                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6124                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6125                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6126         }
6127                 break;
6128         default:
6129                 flow_tx = false;
6130                 flow_rx = false;
6131                 break;
6132         }
6133         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6134                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6135                "10 Gbps" :
6136                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6137                "1 Gbps" :
6138                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6139                "100 Mbps" :
6140                "unknown speed"))),
6141                ((flow_rx && flow_tx) ? "RX/TX" :
6142                (flow_rx ? "RX" :
6143                (flow_tx ? "TX" : "None"))));
6144
6145         netif_carrier_on(netdev);
6146 #ifdef HAVE_IPLINK_VF_CONFIG
6147         ixgbe_check_vf_rate_limit(adapter);
6148 #endif /* HAVE_IPLINK_VF_CONFIG */
6149 }
6150
6151 /**
6152  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6153  *                               print link down message
6154  * @adapter - pointer to the adapter structure
6155  **/
6156 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6157 {
6158         struct net_device *netdev = adapter->netdev;
6159         struct ixgbe_hw *hw = &adapter->hw;
6160
6161         adapter->link_up = false;
6162         adapter->link_speed = 0;
6163
6164         /* only continue if link was up previously */
6165         if (!netif_carrier_ok(netdev))
6166                 return;
6167
6168         /* poll for SFP+ cable when link is down */
6169         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6170                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6171
6172         e_info(drv, "NIC Link is Down\n");
6173         netif_carrier_off(netdev);
6174 }
6175
6176 /**
6177  * ixgbe_watchdog_flush_tx - flush queues on link down
6178  * @adapter - pointer to the device adapter structure
6179  **/
6180 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6181 {
6182         int i;
6183         int some_tx_pending = 0;
6184
6185         if (!netif_carrier_ok(adapter->netdev)) {
6186                 for (i = 0; i < adapter->num_tx_queues; i++) {
6187                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6188                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6189                                 some_tx_pending = 1;
6190                                 break;
6191                         }
6192                 }
6193
6194                 if (some_tx_pending) {
6195                         /* We've lost link, so the controller stops DMA,
6196                          * but we've got queued Tx work that's never going
6197                          * to get done, so reset controller to flush Tx.
6198                          * (Do the reset outside of interrupt context).
6199                          */
6200                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6201                 }
6202         }
6203 }
6204
6205 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6206 {
6207         u32 ssvpc;
6208
6209         /* Do not perform spoof check for 82598 */
6210         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6211                 return;
6212
6213         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6214
6215         /*
6216          * ssvpc register is cleared on read, if zero then no
6217          * spoofed packets in the last interval.
6218          */
6219         if (!ssvpc)
6220                 return;
6221
6222         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6223 }
6224
6225 /**
6226  * ixgbe_watchdog_subtask - check and bring link up
6227  * @adapter - pointer to the device adapter structure
6228  **/
6229 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6230 {
6231         /* if interface is down do nothing */
6232         if (test_bit(__IXGBE_DOWN, &adapter->state))
6233                 return;
6234
6235         ixgbe_watchdog_update_link(adapter);
6236
6237         if (adapter->link_up)
6238                 ixgbe_watchdog_link_is_up(adapter);
6239         else
6240                 ixgbe_watchdog_link_is_down(adapter);
6241
6242         ixgbe_spoof_check(adapter);
6243         ixgbe_update_stats(adapter);
6244
6245         ixgbe_watchdog_flush_tx(adapter);
6246 }
6247
6248 /**
6249  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6250  * @adapter - the ixgbe adapter structure
6251  **/
6252 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6253 {
6254         struct ixgbe_hw *hw = &adapter->hw;
6255         s32 err;
6256
6257         /* not searching for SFP so there is nothing to do here */
6258         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6259             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6260                 return;
6261
6262         /* someone else is in init, wait until next service event */
6263         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6264                 return;
6265
6266         err = hw->phy.ops.identify_sfp(hw);
6267         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6268                 goto sfp_out;
6269
6270         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6271                 /* If no cable is present, then we need to reset
6272                  * the next time we find a good cable. */
6273                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6274         }
6275
6276         /* exit on error */
6277         if (err)
6278                 goto sfp_out;
6279
6280         /* exit if reset not needed */
6281         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6282                 goto sfp_out;
6283
6284         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6285
6286         /*
6287          * A module may be identified correctly, but the EEPROM may not have
6288          * support for that module.  setup_sfp() will fail in that case, so
6289          * we should not allow that module to load.
6290          */
6291         if (hw->mac.type == ixgbe_mac_82598EB)
6292                 err = hw->phy.ops.reset(hw);
6293         else
6294                 err = hw->mac.ops.setup_sfp(hw);
6295
6296         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6297                 goto sfp_out;
6298
6299         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6300         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6301
6302 sfp_out:
6303         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6304
6305         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6306             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6307                 e_dev_err("failed to initialize because an unsupported "
6308                           "SFP+ module type was detected.\n");
6309                 e_dev_err("Reload the driver after installing a "
6310                           "supported module.\n");
6311                 unregister_netdev(adapter->netdev);
6312         }
6313 }
6314
6315 /**
6316  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6317  * @adapter - the ixgbe adapter structure
6318  **/
6319 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6320 {
6321         struct ixgbe_hw *hw = &adapter->hw;
6322         u32 autoneg;
6323         bool negotiation;
6324
6325         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6326                 return;
6327
6328         /* someone else is in init, wait until next service event */
6329         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6330                 return;
6331
6332         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6333
6334         autoneg = hw->phy.autoneg_advertised;
6335         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6336                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6337         hw->mac.autotry_restart = false;
6338         if (hw->mac.ops.setup_link)
6339                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6340
6341         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6342         adapter->link_check_timeout = jiffies;
6343         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6344 }
6345
6346 /**
6347  * ixgbe_service_timer - Timer Call-back
6348  * @data: pointer to adapter cast into an unsigned long
6349  **/
6350 static void ixgbe_service_timer(unsigned long data)
6351 {
6352         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6353         unsigned long next_event_offset;
6354
6355         /* poll faster when waiting for link */
6356         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6357                 next_event_offset = HZ / 10;
6358         else
6359                 next_event_offset = HZ * 2;
6360
6361         /* Reset the timer */
6362         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6363
6364         ixgbe_service_event_schedule(adapter);
6365 }
6366
6367 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6368 {
6369         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6370                 return;
6371
6372         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6373
6374         /* If we're already down or resetting, just bail */
6375         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6376             test_bit(__IXGBE_RESETTING, &adapter->state))
6377                 return;
6378
6379         ixgbe_dump(adapter);
6380         netdev_err(adapter->netdev, "Reset adapter\n");
6381         adapter->tx_timeout_count++;
6382
6383         ixgbe_reinit_locked(adapter);
6384 }
6385
6386 /**
6387  * ixgbe_service_task - manages and runs subtasks
6388  * @work: pointer to work_struct containing our data
6389  **/
6390 static void ixgbe_service_task(struct work_struct *work)
6391 {
6392         struct ixgbe_adapter *adapter = container_of(work,
6393                                                      struct ixgbe_adapter,
6394                                                      service_task);
6395
6396         ixgbe_reset_subtask(adapter);
6397         ixgbe_sfp_detection_subtask(adapter);
6398         ixgbe_sfp_link_config_subtask(adapter);
6399         ixgbe_check_overtemp_subtask(adapter);
6400         ixgbe_watchdog_subtask(adapter);
6401         ixgbe_fdir_reinit_subtask(adapter);
6402         ixgbe_check_hang_subtask(adapter);
6403
6404         ixgbe_service_event_complete(adapter);
6405 }
6406
6407 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6408                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6409                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6410 {
6411         struct ixgbe_adv_tx_context_desc *context_desc;
6412         unsigned int i;
6413         int err;
6414         struct ixgbe_tx_buffer *tx_buffer_info;
6415         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6416         u32 mss_l4len_idx, l4len;
6417
6418         if (skb_is_gso(skb)) {
6419                 if (skb_header_cloned(skb)) {
6420                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6421                         if (err)
6422                                 return err;
6423                 }
6424                 l4len = tcp_hdrlen(skb);
6425                 *hdr_len += l4len;
6426
6427                 if (protocol == htons(ETH_P_IP)) {
6428                         struct iphdr *iph = ip_hdr(skb);
6429                         iph->tot_len = 0;
6430                         iph->check = 0;
6431                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6432                                                                  iph->daddr, 0,
6433                                                                  IPPROTO_TCP,
6434                                                                  0);
6435                 } else if (skb_is_gso_v6(skb)) {
6436                         ipv6_hdr(skb)->payload_len = 0;
6437                         tcp_hdr(skb)->check =
6438                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6439                                              &ipv6_hdr(skb)->daddr,
6440                                              0, IPPROTO_TCP, 0);
6441                 }
6442
6443                 i = tx_ring->next_to_use;
6444
6445                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6446                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6447
6448                 /* VLAN MACLEN IPLEN */
6449                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6450                         vlan_macip_lens |=
6451                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6452                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6453                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6454                 *hdr_len += skb_network_offset(skb);
6455                 vlan_macip_lens |=
6456                     (skb_transport_header(skb) - skb_network_header(skb));
6457                 *hdr_len +=
6458                     (skb_transport_header(skb) - skb_network_header(skb));
6459                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6460                 context_desc->seqnum_seed = 0;
6461
6462                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6463                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6464                                    IXGBE_ADVTXD_DTYP_CTXT);
6465
6466                 if (protocol == htons(ETH_P_IP))
6467                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6468                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6469                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6470
6471                 /* MSS L4LEN IDX */
6472                 mss_l4len_idx =
6473                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6474                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6475                 /* use index 1 for TSO */
6476                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6477                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6478
6479                 tx_buffer_info->time_stamp = jiffies;
6480                 tx_buffer_info->next_to_watch = i;
6481
6482                 i++;
6483                 if (i == tx_ring->count)
6484                         i = 0;
6485                 tx_ring->next_to_use = i;
6486
6487                 return true;
6488         }
6489         return false;
6490 }
6491
6492 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6493                       __be16 protocol)
6494 {
6495         u32 rtn = 0;
6496
6497         switch (protocol) {
6498         case cpu_to_be16(ETH_P_IP):
6499                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6500                 switch (ip_hdr(skb)->protocol) {
6501                 case IPPROTO_TCP:
6502                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6503                         break;
6504                 case IPPROTO_SCTP:
6505                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6506                         break;
6507                 }
6508                 break;
6509         case cpu_to_be16(ETH_P_IPV6):
6510                 /* XXX what about other V6 headers?? */
6511                 switch (ipv6_hdr(skb)->nexthdr) {
6512                 case IPPROTO_TCP:
6513                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6514                         break;
6515                 case IPPROTO_SCTP:
6516                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6517                         break;
6518                 }
6519                 break;
6520         default:
6521                 if (unlikely(net_ratelimit()))
6522                         e_warn(probe, "partial checksum but proto=%x!\n",
6523                                protocol);
6524                 break;
6525         }
6526
6527         return rtn;
6528 }
6529
6530 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6531                           struct ixgbe_ring *tx_ring,
6532                           struct sk_buff *skb, u32 tx_flags,
6533                           __be16 protocol)
6534 {
6535         struct ixgbe_adv_tx_context_desc *context_desc;
6536         unsigned int i;
6537         struct ixgbe_tx_buffer *tx_buffer_info;
6538         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6539
6540         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6541             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6542                 i = tx_ring->next_to_use;
6543                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6544                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6545
6546                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6547                         vlan_macip_lens |=
6548                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6549                 vlan_macip_lens |= (skb_network_offset(skb) <<
6550                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6551                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6552                         vlan_macip_lens |= (skb_transport_header(skb) -
6553                                             skb_network_header(skb));
6554
6555                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6556                 context_desc->seqnum_seed = 0;
6557
6558                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6559                                     IXGBE_ADVTXD_DTYP_CTXT);
6560
6561                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6562                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6563
6564                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6565                 /* use index zero for tx checksum offload */
6566                 context_desc->mss_l4len_idx = 0;
6567
6568                 tx_buffer_info->time_stamp = jiffies;
6569                 tx_buffer_info->next_to_watch = i;
6570
6571                 i++;
6572                 if (i == tx_ring->count)
6573                         i = 0;
6574                 tx_ring->next_to_use = i;
6575
6576                 return true;
6577         }
6578
6579         return false;
6580 }
6581
6582 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6583                         struct ixgbe_ring *tx_ring,
6584                         struct sk_buff *skb, u32 tx_flags,
6585                         unsigned int first, const u8 hdr_len)
6586 {
6587         struct device *dev = tx_ring->dev;
6588         struct ixgbe_tx_buffer *tx_buffer_info;
6589         unsigned int len;
6590         unsigned int total = skb->len;
6591         unsigned int offset = 0, size, count = 0, i;
6592         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6593         unsigned int f;
6594         unsigned int bytecount = skb->len;
6595         u16 gso_segs = 1;
6596
6597         i = tx_ring->next_to_use;
6598
6599         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6600                 /* excluding fcoe_crc_eof for FCoE */
6601                 total -= sizeof(struct fcoe_crc_eof);
6602
6603         len = min(skb_headlen(skb), total);
6604         while (len) {
6605                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6606                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6607
6608                 tx_buffer_info->length = size;
6609                 tx_buffer_info->mapped_as_page = false;
6610                 tx_buffer_info->dma = dma_map_single(dev,
6611                                                      skb->data + offset,
6612                                                      size, DMA_TO_DEVICE);
6613                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6614                         goto dma_error;
6615                 tx_buffer_info->time_stamp = jiffies;
6616                 tx_buffer_info->next_to_watch = i;
6617
6618                 len -= size;
6619                 total -= size;
6620                 offset += size;
6621                 count++;
6622
6623                 if (len) {
6624                         i++;
6625                         if (i == tx_ring->count)
6626                                 i = 0;
6627                 }
6628         }
6629
6630         for (f = 0; f < nr_frags; f++) {
6631                 struct skb_frag_struct *frag;
6632
6633                 frag = &skb_shinfo(skb)->frags[f];
6634                 len = min((unsigned int)frag->size, total);
6635                 offset = frag->page_offset;
6636
6637                 while (len) {
6638                         i++;
6639                         if (i == tx_ring->count)
6640                                 i = 0;
6641
6642                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6643                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6644
6645                         tx_buffer_info->length = size;
6646                         tx_buffer_info->dma = dma_map_page(dev,
6647                                                            frag->page,
6648                                                            offset, size,
6649                                                            DMA_TO_DEVICE);
6650                         tx_buffer_info->mapped_as_page = true;
6651                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6652                                 goto dma_error;
6653                         tx_buffer_info->time_stamp = jiffies;
6654                         tx_buffer_info->next_to_watch = i;
6655
6656                         len -= size;
6657                         total -= size;
6658                         offset += size;
6659                         count++;
6660                 }
6661                 if (total == 0)
6662                         break;
6663         }
6664
6665         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6666                 gso_segs = skb_shinfo(skb)->gso_segs;
6667 #ifdef IXGBE_FCOE
6668         /* adjust for FCoE Sequence Offload */
6669         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6670                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6671                                         skb_shinfo(skb)->gso_size);
6672 #endif /* IXGBE_FCOE */
6673         bytecount += (gso_segs - 1) * hdr_len;
6674
6675         /* multiply data chunks by size of headers */
6676         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6677         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6678         tx_ring->tx_buffer_info[i].skb = skb;
6679         tx_ring->tx_buffer_info[first].next_to_watch = i;
6680
6681         return count;
6682
6683 dma_error:
6684         e_dev_err("TX DMA map failed\n");
6685
6686         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6687         tx_buffer_info->dma = 0;
6688         tx_buffer_info->time_stamp = 0;
6689         tx_buffer_info->next_to_watch = 0;
6690         if (count)
6691                 count--;
6692
6693         /* clear timestamp and dma mappings for remaining portion of packet */
6694         while (count--) {
6695                 if (i == 0)
6696                         i += tx_ring->count;
6697                 i--;
6698                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6699                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6700         }
6701
6702         return 0;
6703 }
6704
6705 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6706                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6707 {
6708         union ixgbe_adv_tx_desc *tx_desc = NULL;
6709         struct ixgbe_tx_buffer *tx_buffer_info;
6710         u32 olinfo_status = 0, cmd_type_len = 0;
6711         unsigned int i;
6712         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6713
6714         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6715
6716         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6717
6718         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6719                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6720
6721         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6722                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6723
6724                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6725                                  IXGBE_ADVTXD_POPTS_SHIFT;
6726
6727                 /* use index 1 context for tso */
6728                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6729                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6730                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6731                                          IXGBE_ADVTXD_POPTS_SHIFT;
6732
6733         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6734                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6735                                  IXGBE_ADVTXD_POPTS_SHIFT;
6736
6737         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6738                 olinfo_status |= IXGBE_ADVTXD_CC;
6739                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6740                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6741                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6742         }
6743
6744         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6745
6746         i = tx_ring->next_to_use;
6747         while (count--) {
6748                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6749                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6750                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6751                 tx_desc->read.cmd_type_len =
6752                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6753                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6754                 i++;
6755                 if (i == tx_ring->count)
6756                         i = 0;
6757         }
6758
6759         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6760
6761         /*
6762          * Force memory writes to complete before letting h/w
6763          * know there are new descriptors to fetch.  (Only
6764          * applicable for weak-ordered memory model archs,
6765          * such as IA-64).
6766          */
6767         wmb();
6768
6769         tx_ring->next_to_use = i;
6770         writel(i, tx_ring->tail);
6771 }
6772
6773 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6774                       u32 tx_flags, __be16 protocol)
6775 {
6776         struct ixgbe_q_vector *q_vector = ring->q_vector;
6777         union ixgbe_atr_hash_dword input = { .dword = 0 };
6778         union ixgbe_atr_hash_dword common = { .dword = 0 };
6779         union {
6780                 unsigned char *network;
6781                 struct iphdr *ipv4;
6782                 struct ipv6hdr *ipv6;
6783         } hdr;
6784         struct tcphdr *th;
6785         __be16 vlan_id;
6786
6787         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6788         if (!q_vector)
6789                 return;
6790
6791         /* do nothing if sampling is disabled */
6792         if (!ring->atr_sample_rate)
6793                 return;
6794
6795         ring->atr_count++;
6796
6797         /* snag network header to get L4 type and address */
6798         hdr.network = skb_network_header(skb);
6799
6800         /* Currently only IPv4/IPv6 with TCP is supported */
6801         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6802              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6803             (protocol != __constant_htons(ETH_P_IP) ||
6804              hdr.ipv4->protocol != IPPROTO_TCP))
6805                 return;
6806
6807         th = tcp_hdr(skb);
6808
6809         /* skip this packet since the socket is closing */
6810         if (th->fin)
6811                 return;
6812
6813         /* sample on all syn packets or once every atr sample count */
6814         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6815                 return;
6816
6817         /* reset sample count */
6818         ring->atr_count = 0;
6819
6820         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6821
6822         /*
6823          * src and dst are inverted, think how the receiver sees them
6824          *
6825          * The input is broken into two sections, a non-compressed section
6826          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6827          * is XORed together and stored in the compressed dword.
6828          */
6829         input.formatted.vlan_id = vlan_id;
6830
6831         /*
6832          * since src port and flex bytes occupy the same word XOR them together
6833          * and write the value to source port portion of compressed dword
6834          */
6835         if (vlan_id)
6836                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6837         else
6838                 common.port.src ^= th->dest ^ protocol;
6839         common.port.dst ^= th->source;
6840
6841         if (protocol == __constant_htons(ETH_P_IP)) {
6842                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6843                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6844         } else {
6845                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6846                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6847                              hdr.ipv6->saddr.s6_addr32[1] ^
6848                              hdr.ipv6->saddr.s6_addr32[2] ^
6849                              hdr.ipv6->saddr.s6_addr32[3] ^
6850                              hdr.ipv6->daddr.s6_addr32[0] ^
6851                              hdr.ipv6->daddr.s6_addr32[1] ^
6852                              hdr.ipv6->daddr.s6_addr32[2] ^
6853                              hdr.ipv6->daddr.s6_addr32[3];
6854         }
6855
6856         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6857         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6858                                               input, common, ring->queue_index);
6859 }
6860
6861 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6862 {
6863         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6864         /* Herbert's original patch had:
6865          *  smp_mb__after_netif_stop_queue();
6866          * but since that doesn't exist yet, just open code it. */
6867         smp_mb();
6868
6869         /* We need to check again in a case another CPU has just
6870          * made room available. */
6871         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6872                 return -EBUSY;
6873
6874         /* A reprieve! - use start_queue because it doesn't call schedule */
6875         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6876         ++tx_ring->tx_stats.restart_queue;
6877         return 0;
6878 }
6879
6880 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6881 {
6882         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6883                 return 0;
6884         return __ixgbe_maybe_stop_tx(tx_ring, size);
6885 }
6886
6887 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6888 {
6889         struct ixgbe_adapter *adapter = netdev_priv(dev);
6890         int txq = smp_processor_id();
6891 #ifdef IXGBE_FCOE
6892         __be16 protocol;
6893
6894         protocol = vlan_get_protocol(skb);
6895
6896         if (((protocol == htons(ETH_P_FCOE)) ||
6897             (protocol == htons(ETH_P_FIP))) &&
6898             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6899                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6900                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6901                 return txq;
6902         }
6903 #endif
6904
6905         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6906                 while (unlikely(txq >= dev->real_num_tx_queues))
6907                         txq -= dev->real_num_tx_queues;
6908                 return txq;
6909         }
6910
6911         return skb_tx_hash(dev, skb);
6912 }
6913
6914 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6915                           struct ixgbe_adapter *adapter,
6916                           struct ixgbe_ring *tx_ring)
6917 {
6918         unsigned int first;
6919         unsigned int tx_flags = 0;
6920         u8 hdr_len = 0;
6921         int tso;
6922         int count = 0;
6923         unsigned int f;
6924         __be16 protocol;
6925
6926         protocol = vlan_get_protocol(skb);
6927
6928         if (vlan_tx_tag_present(skb)) {
6929                 tx_flags |= vlan_tx_tag_get(skb);
6930                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6931                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6932                         tx_flags |= tx_ring->dcb_tc << 13;
6933                 }
6934                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6935                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6936         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6937                    skb->priority != TC_PRIO_CONTROL) {
6938                 tx_flags |= tx_ring->dcb_tc << 13;
6939                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6940                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6941         }
6942
6943 #ifdef IXGBE_FCOE
6944         /* for FCoE with DCB, we force the priority to what
6945          * was specified by the switch */
6946         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6947             (protocol == htons(ETH_P_FCOE)))
6948                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6949 #endif
6950
6951         /* four things can cause us to need a context descriptor */
6952         if (skb_is_gso(skb) ||
6953             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6954             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6955             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6956                 count++;
6957
6958         count += TXD_USE_COUNT(skb_headlen(skb));
6959         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6960                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6961
6962         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6963                 tx_ring->tx_stats.tx_busy++;
6964                 return NETDEV_TX_BUSY;
6965         }
6966
6967         first = tx_ring->next_to_use;
6968         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6969 #ifdef IXGBE_FCOE
6970                 /* setup tx offload for FCoE */
6971                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6972                 if (tso < 0) {
6973                         dev_kfree_skb_any(skb);
6974                         return NETDEV_TX_OK;
6975                 }
6976                 if (tso)
6977                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6978 #endif /* IXGBE_FCOE */
6979         } else {
6980                 if (protocol == htons(ETH_P_IP))
6981                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6982                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6983                                 protocol);
6984                 if (tso < 0) {
6985                         dev_kfree_skb_any(skb);
6986                         return NETDEV_TX_OK;
6987                 }
6988
6989                 if (tso)
6990                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6991                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6992                                        protocol) &&
6993                          (skb->ip_summed == CHECKSUM_PARTIAL))
6994                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6995         }
6996
6997         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6998         if (count) {
6999                 /* add the ATR filter if ATR is on */
7000                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7001                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7002                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
7003                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7004
7005         } else {
7006                 dev_kfree_skb_any(skb);
7007                 tx_ring->tx_buffer_info[first].time_stamp = 0;
7008                 tx_ring->next_to_use = first;
7009         }
7010
7011         return NETDEV_TX_OK;
7012 }
7013
7014 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7015 {
7016         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7017         struct ixgbe_ring *tx_ring;
7018
7019         tx_ring = adapter->tx_ring[skb->queue_mapping];
7020         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7021 }
7022
7023 /**
7024  * ixgbe_set_mac - Change the Ethernet Address of the NIC
7025  * @netdev: network interface device structure
7026  * @p: pointer to an address structure
7027  *
7028  * Returns 0 on success, negative on failure
7029  **/
7030 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7031 {
7032         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7033         struct ixgbe_hw *hw = &adapter->hw;
7034         struct sockaddr *addr = p;
7035
7036         if (!is_valid_ether_addr(addr->sa_data))
7037                 return -EADDRNOTAVAIL;
7038
7039         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7040         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7041
7042         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7043                             IXGBE_RAH_AV);
7044
7045         return 0;
7046 }
7047
7048 static int
7049 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7050 {
7051         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7052         struct ixgbe_hw *hw = &adapter->hw;
7053         u16 value;
7054         int rc;
7055
7056         if (prtad != hw->phy.mdio.prtad)
7057                 return -EINVAL;
7058         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7059         if (!rc)
7060                 rc = value;
7061         return rc;
7062 }
7063
7064 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7065                             u16 addr, u16 value)
7066 {
7067         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7068         struct ixgbe_hw *hw = &adapter->hw;
7069
7070         if (prtad != hw->phy.mdio.prtad)
7071                 return -EINVAL;
7072         return hw->phy.ops.write_reg(hw, addr, devad, value);
7073 }
7074
7075 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7076 {
7077         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7078
7079         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7080 }
7081
7082 /**
7083  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7084  * netdev->dev_addrs
7085  * @netdev: network interface device structure
7086  *
7087  * Returns non-zero on failure
7088  **/
7089 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7090 {
7091         int err = 0;
7092         struct ixgbe_adapter *adapter = netdev_priv(dev);
7093         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7094
7095         if (is_valid_ether_addr(mac->san_addr)) {
7096                 rtnl_lock();
7097                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7098                 rtnl_unlock();
7099         }
7100         return err;
7101 }
7102
7103 /**
7104  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7105  * netdev->dev_addrs
7106  * @netdev: network interface device structure
7107  *
7108  * Returns non-zero on failure
7109  **/
7110 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7111 {
7112         int err = 0;
7113         struct ixgbe_adapter *adapter = netdev_priv(dev);
7114         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7115
7116         if (is_valid_ether_addr(mac->san_addr)) {
7117                 rtnl_lock();
7118                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7119                 rtnl_unlock();
7120         }
7121         return err;
7122 }
7123
7124 #ifdef CONFIG_NET_POLL_CONTROLLER
7125 /*
7126  * Polling 'interrupt' - used by things like netconsole to send skbs
7127  * without having to re-enable interrupts. It's not called while
7128  * the interrupt routine is executing.
7129  */
7130 static void ixgbe_netpoll(struct net_device *netdev)
7131 {
7132         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7133         int i;
7134
7135         /* if interface is down do nothing */
7136         if (test_bit(__IXGBE_DOWN, &adapter->state))
7137                 return;
7138
7139         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7140         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7141                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7142                 for (i = 0; i < num_q_vectors; i++) {
7143                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7144                         ixgbe_msix_clean_many(0, q_vector);
7145                 }
7146         } else {
7147                 ixgbe_intr(adapter->pdev->irq, netdev);
7148         }
7149         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7150 }
7151 #endif
7152
7153 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7154                                                    struct rtnl_link_stats64 *stats)
7155 {
7156         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7157         int i;
7158
7159         rcu_read_lock();
7160         for (i = 0; i < adapter->num_rx_queues; i++) {
7161                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7162                 u64 bytes, packets;
7163                 unsigned int start;
7164
7165                 if (ring) {
7166                         do {
7167                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7168                                 packets = ring->stats.packets;
7169                                 bytes   = ring->stats.bytes;
7170                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7171                         stats->rx_packets += packets;
7172                         stats->rx_bytes   += bytes;
7173                 }
7174         }
7175
7176         for (i = 0; i < adapter->num_tx_queues; i++) {
7177                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7178                 u64 bytes, packets;
7179                 unsigned int start;
7180
7181                 if (ring) {
7182                         do {
7183                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7184                                 packets = ring->stats.packets;
7185                                 bytes   = ring->stats.bytes;
7186                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7187                         stats->tx_packets += packets;
7188                         stats->tx_bytes   += bytes;
7189                 }
7190         }
7191         rcu_read_unlock();
7192         /* following stats updated by ixgbe_watchdog_task() */
7193         stats->multicast        = netdev->stats.multicast;
7194         stats->rx_errors        = netdev->stats.rx_errors;
7195         stats->rx_length_errors = netdev->stats.rx_length_errors;
7196         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7197         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7198         return stats;
7199 }
7200
7201
7202 static const struct net_device_ops ixgbe_netdev_ops = {
7203         .ndo_open               = ixgbe_open,
7204         .ndo_stop               = ixgbe_close,
7205         .ndo_start_xmit         = ixgbe_xmit_frame,
7206         .ndo_select_queue       = ixgbe_select_queue,
7207         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7208         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7209         .ndo_validate_addr      = eth_validate_addr,
7210         .ndo_set_mac_address    = ixgbe_set_mac,
7211         .ndo_change_mtu         = ixgbe_change_mtu,
7212         .ndo_tx_timeout         = ixgbe_tx_timeout,
7213         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7214         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7215         .ndo_do_ioctl           = ixgbe_ioctl,
7216         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7217         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7218         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7219         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7220         .ndo_get_stats64        = ixgbe_get_stats64,
7221 #ifdef CONFIG_IXGBE_DCB
7222         .ndo_setup_tc           = ixgbe_setup_tc,
7223 #endif
7224 #ifdef CONFIG_NET_POLL_CONTROLLER
7225         .ndo_poll_controller    = ixgbe_netpoll,
7226 #endif
7227 #ifdef IXGBE_FCOE
7228         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7229         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7230         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7231         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7232         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7233         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7234 #endif /* IXGBE_FCOE */
7235 };
7236
7237 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7238                            const struct ixgbe_info *ii)
7239 {
7240 #ifdef CONFIG_PCI_IOV
7241         struct ixgbe_hw *hw = &adapter->hw;
7242         int err;
7243         int num_vf_macvlans, i;
7244         struct vf_macvlans *mv_list;
7245
7246         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7247                 return;
7248
7249         /* The 82599 supports up to 64 VFs per physical function
7250          * but this implementation limits allocation to 63 so that
7251          * basic networking resources are still available to the
7252          * physical function
7253          */
7254         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7255         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7256         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7257         if (err) {
7258                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7259                 goto err_novfs;
7260         }
7261
7262         num_vf_macvlans = hw->mac.num_rar_entries -
7263                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7264
7265         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7266                                              sizeof(struct vf_macvlans),
7267                                              GFP_KERNEL);
7268         if (mv_list) {
7269                 /* Initialize list of VF macvlans */
7270                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7271                 for (i = 0; i < num_vf_macvlans; i++) {
7272                         mv_list->vf = -1;
7273                         mv_list->free = true;
7274                         mv_list->rar_entry = hw->mac.num_rar_entries -
7275                                 (i + adapter->num_vfs + 1);
7276                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7277                         mv_list++;
7278                 }
7279         }
7280
7281         /* If call to enable VFs succeeded then allocate memory
7282          * for per VF control structures.
7283          */
7284         adapter->vfinfo =
7285                 kcalloc(adapter->num_vfs,
7286                         sizeof(struct vf_data_storage), GFP_KERNEL);
7287         if (adapter->vfinfo) {
7288                 /* Now that we're sure SR-IOV is enabled
7289                  * and memory allocated set up the mailbox parameters
7290                  */
7291                 ixgbe_init_mbx_params_pf(hw);
7292                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7293                        sizeof(hw->mbx.ops));
7294
7295                 /* Disable RSC when in SR-IOV mode */
7296                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7297                                      IXGBE_FLAG2_RSC_ENABLED);
7298                 return;
7299         }
7300
7301         /* Oh oh */
7302         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7303               "SRIOV disabled\n");
7304         pci_disable_sriov(adapter->pdev);
7305
7306 err_novfs:
7307         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7308         adapter->num_vfs = 0;
7309 #endif /* CONFIG_PCI_IOV */
7310 }
7311
7312 /**
7313  * ixgbe_probe - Device Initialization Routine
7314  * @pdev: PCI device information struct
7315  * @ent: entry in ixgbe_pci_tbl
7316  *
7317  * Returns 0 on success, negative on failure
7318  *
7319  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7320  * The OS initialization, configuring of the adapter private structure,
7321  * and a hardware reset occur.
7322  **/
7323 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7324                                  const struct pci_device_id *ent)
7325 {
7326         struct net_device *netdev;
7327         struct ixgbe_adapter *adapter = NULL;
7328         struct ixgbe_hw *hw;
7329         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7330         static int cards_found;
7331         int i, err, pci_using_dac;
7332         u8 part_str[IXGBE_PBANUM_LENGTH];
7333         unsigned int indices = num_possible_cpus();
7334 #ifdef IXGBE_FCOE
7335         u16 device_caps;
7336 #endif
7337         u32 eec;
7338
7339         /* Catch broken hardware that put the wrong VF device ID in
7340          * the PCIe SR-IOV capability.
7341          */
7342         if (pdev->is_virtfn) {
7343                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7344                      pci_name(pdev), pdev->vendor, pdev->device);
7345                 return -EINVAL;
7346         }
7347
7348         err = pci_enable_device_mem(pdev);
7349         if (err)
7350                 return err;
7351
7352         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7353             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7354                 pci_using_dac = 1;
7355         } else {
7356                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7357                 if (err) {
7358                         err = dma_set_coherent_mask(&pdev->dev,
7359                                                     DMA_BIT_MASK(32));
7360                         if (err) {
7361                                 dev_err(&pdev->dev,
7362                                         "No usable DMA configuration, aborting\n");
7363                                 goto err_dma;
7364                         }
7365                 }
7366                 pci_using_dac = 0;
7367         }
7368
7369         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7370                                            IORESOURCE_MEM), ixgbe_driver_name);
7371         if (err) {
7372                 dev_err(&pdev->dev,
7373                         "pci_request_selected_regions failed 0x%x\n", err);
7374                 goto err_pci_reg;
7375         }
7376
7377         pci_enable_pcie_error_reporting(pdev);
7378
7379         pci_set_master(pdev);
7380         pci_save_state(pdev);
7381
7382         if (ii->mac == ixgbe_mac_82598EB)
7383                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7384         else
7385                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7386
7387 #if defined(CONFIG_DCB)
7388         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7389 #elif defined(IXGBE_FCOE)
7390         indices += min_t(unsigned int, num_possible_cpus(),
7391                          IXGBE_MAX_FCOE_INDICES);
7392 #endif
7393         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7394         if (!netdev) {
7395                 err = -ENOMEM;
7396                 goto err_alloc_etherdev;
7397         }
7398
7399         SET_NETDEV_DEV(netdev, &pdev->dev);
7400
7401         adapter = netdev_priv(netdev);
7402         pci_set_drvdata(pdev, adapter);
7403
7404         adapter->netdev = netdev;
7405         adapter->pdev = pdev;
7406         hw = &adapter->hw;
7407         hw->back = adapter;
7408         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7409
7410         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7411                               pci_resource_len(pdev, 0));
7412         if (!hw->hw_addr) {
7413                 err = -EIO;
7414                 goto err_ioremap;
7415         }
7416
7417         for (i = 1; i <= 5; i++) {
7418                 if (pci_resource_len(pdev, i) == 0)
7419                         continue;
7420         }
7421
7422         netdev->netdev_ops = &ixgbe_netdev_ops;
7423         ixgbe_set_ethtool_ops(netdev);
7424         netdev->watchdog_timeo = 5 * HZ;
7425         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7426
7427         adapter->bd_number = cards_found;
7428
7429         /* Setup hw api */
7430         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7431         hw->mac.type  = ii->mac;
7432
7433         /* EEPROM */
7434         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7435         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7436         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7437         if (!(eec & (1 << 8)))
7438                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7439
7440         /* PHY */
7441         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7442         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7443         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7444         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7445         hw->phy.mdio.mmds = 0;
7446         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7447         hw->phy.mdio.dev = netdev;
7448         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7449         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7450
7451         ii->get_invariants(hw);
7452
7453         /* setup the private structure */
7454         err = ixgbe_sw_init(adapter);
7455         if (err)
7456                 goto err_sw_init;
7457
7458         /* Make it possible the adapter to be woken up via WOL */
7459         switch (adapter->hw.mac.type) {
7460         case ixgbe_mac_82599EB:
7461         case ixgbe_mac_X540:
7462                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7463                 break;
7464         default:
7465                 break;
7466         }
7467
7468         /*
7469          * If there is a fan on this device and it has failed log the
7470          * failure.
7471          */
7472         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7473                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7474                 if (esdp & IXGBE_ESDP_SDP1)
7475                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7476         }
7477
7478         /* reset_hw fills in the perm_addr as well */
7479         hw->phy.reset_if_overtemp = true;
7480         err = hw->mac.ops.reset_hw(hw);
7481         hw->phy.reset_if_overtemp = false;
7482         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7483             hw->mac.type == ixgbe_mac_82598EB) {
7484                 err = 0;
7485         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7486                 e_dev_err("failed to load because an unsupported SFP+ "
7487                           "module type was detected.\n");
7488                 e_dev_err("Reload the driver after installing a supported "
7489                           "module.\n");
7490                 goto err_sw_init;
7491         } else if (err) {
7492                 e_dev_err("HW Init failed: %d\n", err);
7493                 goto err_sw_init;
7494         }
7495
7496         ixgbe_probe_vf(adapter, ii);
7497
7498         netdev->features = NETIF_F_SG |
7499                            NETIF_F_IP_CSUM |
7500                            NETIF_F_HW_VLAN_TX |
7501                            NETIF_F_HW_VLAN_RX |
7502                            NETIF_F_HW_VLAN_FILTER;
7503
7504         netdev->features |= NETIF_F_IPV6_CSUM;
7505         netdev->features |= NETIF_F_TSO;
7506         netdev->features |= NETIF_F_TSO6;
7507         netdev->features |= NETIF_F_GRO;
7508         netdev->features |= NETIF_F_RXHASH;
7509
7510         switch (adapter->hw.mac.type) {
7511         case ixgbe_mac_82599EB:
7512         case ixgbe_mac_X540:
7513                 netdev->features |= NETIF_F_SCTP_CSUM;
7514                 break;
7515         default:
7516                 break;
7517         }
7518
7519         netdev->vlan_features |= NETIF_F_TSO;
7520         netdev->vlan_features |= NETIF_F_TSO6;
7521         netdev->vlan_features |= NETIF_F_IP_CSUM;
7522         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7523         netdev->vlan_features |= NETIF_F_SG;
7524
7525         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7526                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7527                                     IXGBE_FLAG_DCB_ENABLED);
7528
7529 #ifdef CONFIG_IXGBE_DCB
7530         netdev->dcbnl_ops = &dcbnl_ops;
7531 #endif
7532
7533 #ifdef IXGBE_FCOE
7534         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7535                 if (hw->mac.ops.get_device_caps) {
7536                         hw->mac.ops.get_device_caps(hw, &device_caps);
7537                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7538                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7539                 }
7540         }
7541         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7542                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7543                 netdev->vlan_features |= NETIF_F_FSO;
7544                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7545         }
7546 #endif /* IXGBE_FCOE */
7547         if (pci_using_dac) {
7548                 netdev->features |= NETIF_F_HIGHDMA;
7549                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7550         }
7551
7552         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7553                 netdev->features |= NETIF_F_LRO;
7554
7555         /* make sure the EEPROM is good */
7556         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7557                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7558                 err = -EIO;
7559                 goto err_eeprom;
7560         }
7561
7562         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7563         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7564
7565         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7566                 e_dev_err("invalid MAC address\n");
7567                 err = -EIO;
7568                 goto err_eeprom;
7569         }
7570
7571         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7572         if (hw->mac.ops.disable_tx_laser &&
7573             ((hw->phy.multispeed_fiber) ||
7574              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7575               (hw->mac.type == ixgbe_mac_82599EB))))
7576                 hw->mac.ops.disable_tx_laser(hw);
7577
7578         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7579                     (unsigned long) adapter);
7580
7581         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7582         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7583
7584         err = ixgbe_init_interrupt_scheme(adapter);
7585         if (err)
7586                 goto err_sw_init;
7587
7588         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7589                 netdev->features &= ~NETIF_F_RXHASH;
7590
7591         switch (pdev->device) {
7592         case IXGBE_DEV_ID_82599_SFP:
7593                 /* Only this subdevice supports WOL */
7594                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7595                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7596                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7597                 break;
7598         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7599                 /* All except this subdevice support WOL */
7600                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7601                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7602                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7603                 break;
7604         case IXGBE_DEV_ID_82599_KX4:
7605                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7606                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7607                 break;
7608         default:
7609                 adapter->wol = 0;
7610                 break;
7611         }
7612         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7613
7614         /* pick up the PCI bus settings for reporting later */
7615         hw->mac.ops.get_bus_info(hw);
7616
7617         /* print bus type/speed/width info */
7618         e_dev_info("(PCI Express:%s:%s) %pM\n",
7619                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7620                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7621                     "Unknown"),
7622                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7623                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7624                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7625                     "Unknown"),
7626                    netdev->dev_addr);
7627
7628         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7629         if (err)
7630                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7631         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7632                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7633                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7634                            part_str);
7635         else
7636                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7637                            hw->mac.type, hw->phy.type, part_str);
7638
7639         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7640                 e_dev_warn("PCI-Express bandwidth available for this card is "
7641                            "not sufficient for optimal performance.\n");
7642                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7643                            "is required.\n");
7644         }
7645
7646         /* save off EEPROM version number */
7647         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7648
7649         /* reset the hardware with the new settings */
7650         err = hw->mac.ops.start_hw(hw);
7651
7652         if (err == IXGBE_ERR_EEPROM_VERSION) {
7653                 /* We are running on a pre-production device, log a warning */
7654                 e_dev_warn("This device is a pre-production adapter/LOM. "
7655                            "Please be aware there may be issues associated "
7656                            "with your hardware.  If you are experiencing "
7657                            "problems please contact your Intel or hardware "
7658                            "representative who provided you with this "
7659                            "hardware.\n");
7660         }
7661         strcpy(netdev->name, "eth%d");
7662         err = register_netdev(netdev);
7663         if (err)
7664                 goto err_register;
7665
7666         /* carrier off reporting is important to ethtool even BEFORE open */
7667         netif_carrier_off(netdev);
7668
7669 #ifdef CONFIG_IXGBE_DCA
7670         if (dca_add_requester(&pdev->dev) == 0) {
7671                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7672                 ixgbe_setup_dca(adapter);
7673         }
7674 #endif
7675         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7676                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7677                 for (i = 0; i < adapter->num_vfs; i++)
7678                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7679         }
7680
7681         /* add san mac addr to netdev */
7682         ixgbe_add_sanmac_netdev(netdev);
7683
7684         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7685         cards_found++;
7686         return 0;
7687
7688 err_register:
7689         ixgbe_release_hw_control(adapter);
7690         ixgbe_clear_interrupt_scheme(adapter);
7691 err_sw_init:
7692 err_eeprom:
7693         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7694                 ixgbe_disable_sriov(adapter);
7695         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7696         iounmap(hw->hw_addr);
7697 err_ioremap:
7698         free_netdev(netdev);
7699 err_alloc_etherdev:
7700         pci_release_selected_regions(pdev,
7701                                      pci_select_bars(pdev, IORESOURCE_MEM));
7702 err_pci_reg:
7703 err_dma:
7704         pci_disable_device(pdev);
7705         return err;
7706 }
7707
7708 /**
7709  * ixgbe_remove - Device Removal Routine
7710  * @pdev: PCI device information struct
7711  *
7712  * ixgbe_remove is called by the PCI subsystem to alert the driver
7713  * that it should release a PCI device.  The could be caused by a
7714  * Hot-Plug event, or because the driver is going to be removed from
7715  * memory.
7716  **/
7717 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7718 {
7719         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7720         struct net_device *netdev = adapter->netdev;
7721
7722         set_bit(__IXGBE_DOWN, &adapter->state);
7723         cancel_work_sync(&adapter->service_task);
7724
7725 #ifdef CONFIG_IXGBE_DCA
7726         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7727                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7728                 dca_remove_requester(&pdev->dev);
7729                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7730         }
7731
7732 #endif
7733 #ifdef IXGBE_FCOE
7734         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7735                 ixgbe_cleanup_fcoe(adapter);
7736
7737 #endif /* IXGBE_FCOE */
7738
7739         /* remove the added san mac */
7740         ixgbe_del_sanmac_netdev(netdev);
7741
7742         if (netdev->reg_state == NETREG_REGISTERED)
7743                 unregister_netdev(netdev);
7744
7745         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7746                 ixgbe_disable_sriov(adapter);
7747
7748         ixgbe_clear_interrupt_scheme(adapter);
7749
7750         ixgbe_release_hw_control(adapter);
7751
7752         iounmap(adapter->hw.hw_addr);
7753         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7754                                      IORESOURCE_MEM));
7755
7756         e_dev_info("complete\n");
7757
7758         free_netdev(netdev);
7759
7760         pci_disable_pcie_error_reporting(pdev);
7761
7762         pci_disable_device(pdev);
7763 }
7764
7765 /**
7766  * ixgbe_io_error_detected - called when PCI error is detected
7767  * @pdev: Pointer to PCI device
7768  * @state: The current pci connection state
7769  *
7770  * This function is called after a PCI bus error affecting
7771  * this device has been detected.
7772  */
7773 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7774                                                 pci_channel_state_t state)
7775 {
7776         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7777         struct net_device *netdev = adapter->netdev;
7778
7779         netif_device_detach(netdev);
7780
7781         if (state == pci_channel_io_perm_failure)
7782                 return PCI_ERS_RESULT_DISCONNECT;
7783
7784         if (netif_running(netdev))
7785                 ixgbe_down(adapter);
7786         pci_disable_device(pdev);
7787
7788         /* Request a slot reset. */
7789         return PCI_ERS_RESULT_NEED_RESET;
7790 }
7791
7792 /**
7793  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7794  * @pdev: Pointer to PCI device
7795  *
7796  * Restart the card from scratch, as if from a cold-boot.
7797  */
7798 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7799 {
7800         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7801         pci_ers_result_t result;
7802         int err;
7803
7804         if (pci_enable_device_mem(pdev)) {
7805                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7806                 result = PCI_ERS_RESULT_DISCONNECT;
7807         } else {
7808                 pci_set_master(pdev);
7809                 pci_restore_state(pdev);
7810                 pci_save_state(pdev);
7811
7812                 pci_wake_from_d3(pdev, false);
7813
7814                 ixgbe_reset(adapter);
7815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7816                 result = PCI_ERS_RESULT_RECOVERED;
7817         }
7818
7819         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7820         if (err) {
7821                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7822                           "failed 0x%0x\n", err);
7823                 /* non-fatal, continue */
7824         }
7825
7826         return result;
7827 }
7828
7829 /**
7830  * ixgbe_io_resume - called when traffic can start flowing again.
7831  * @pdev: Pointer to PCI device
7832  *
7833  * This callback is called when the error recovery driver tells us that
7834  * its OK to resume normal operation.
7835  */
7836 static void ixgbe_io_resume(struct pci_dev *pdev)
7837 {
7838         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7839         struct net_device *netdev = adapter->netdev;
7840
7841         if (netif_running(netdev)) {
7842                 if (ixgbe_up(adapter)) {
7843                         e_info(probe, "ixgbe_up failed after reset\n");
7844                         return;
7845                 }
7846         }
7847
7848         netif_device_attach(netdev);
7849 }
7850
7851 static struct pci_error_handlers ixgbe_err_handler = {
7852         .error_detected = ixgbe_io_error_detected,
7853         .slot_reset = ixgbe_io_slot_reset,
7854         .resume = ixgbe_io_resume,
7855 };
7856
7857 static struct pci_driver ixgbe_driver = {
7858         .name     = ixgbe_driver_name,
7859         .id_table = ixgbe_pci_tbl,
7860         .probe    = ixgbe_probe,
7861         .remove   = __devexit_p(ixgbe_remove),
7862 #ifdef CONFIG_PM
7863         .suspend  = ixgbe_suspend,
7864         .resume   = ixgbe_resume,
7865 #endif
7866         .shutdown = ixgbe_shutdown,
7867         .err_handler = &ixgbe_err_handler
7868 };
7869
7870 /**
7871  * ixgbe_init_module - Driver Registration Routine
7872  *
7873  * ixgbe_init_module is the first routine called when the driver is
7874  * loaded. All it does is register with the PCI subsystem.
7875  **/
7876 static int __init ixgbe_init_module(void)
7877 {
7878         int ret;
7879         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7880         pr_info("%s\n", ixgbe_copyright);
7881
7882 #ifdef CONFIG_IXGBE_DCA
7883         dca_register_notify(&dca_notifier);
7884 #endif
7885
7886         ret = pci_register_driver(&ixgbe_driver);
7887         return ret;
7888 }
7889
7890 module_init(ixgbe_init_module);
7891
7892 /**
7893  * ixgbe_exit_module - Driver Exit Cleanup Routine
7894  *
7895  * ixgbe_exit_module is called just before the driver is removed
7896  * from memory.
7897  **/
7898 static void __exit ixgbe_exit_module(void)
7899 {
7900 #ifdef CONFIG_IXGBE_DCA
7901         dca_unregister_notify(&dca_notifier);
7902 #endif
7903         pci_unregister_driver(&ixgbe_driver);
7904         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7905 }
7906
7907 #ifdef CONFIG_IXGBE_DCA
7908 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7909                             void *p)
7910 {
7911         int ret_val;
7912
7913         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7914                                          __ixgbe_notify_dca);
7915
7916         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7917 }
7918
7919 #endif /* CONFIG_IXGBE_DCA */
7920
7921 module_exit(ixgbe_exit_module);
7922
7923 /* ixgbe_main.c */