drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright © 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #include <asm/mach/flash.h>
  41 #include <plat/gpmc.h>
  42 #include <plat/onenand.h>
  43 #include <mach/gpio.h>
  44
  45 #include <plat/dma.h>
  46
  47 #include <plat/board.h>
  48
  49 #define DRIVER_NAME "omap2-onenand"
  50
  51 #define ONENAND_IO_SIZE         SZ_128K
  52 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  53
  54 struct omap2_onenand {
  55         struct platform_device *pdev;
  56         int gpmc_cs;
  57         unsigned long phys_base;
  58         int gpio_irq;
  59         struct mtd_info mtd;
  60         struct mtd_partition *parts;
  61         struct onenand_chip onenand;
  62         struct completion irq_done;
  63         struct completion dma_done;
  64         int dma_channel;
  65         int freq;
  66         int (*setup)(void __iomem *base, int *freq_ptr);
  67         struct regulator *regulator;
  68 };
  69
  70 static const char *part_probes[] = { "cmdlinepart", NULL,  };
  71
  72 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  73 {
  74         struct omap2_onenand *c = data;
  75
  76         complete(&c->dma_done);
  77 }
  78
  79 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  80 {
  81         struct omap2_onenand *c = dev_id;
  82
  83         complete(&c->irq_done);
  84
  85         return IRQ_HANDLED;
  86 }
  87
  88 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  89 {
  90         return readw(c->onenand.base + reg);
  91 }
  92
  93 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  94                              int reg)
  95 {
  96         writew(value, c->onenand.base + reg);
  97 }
  98
  99 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
 100 {
 101         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
 102                msg, state, ctrl, intr);
 103 }
 104
 105 static void wait_warn(char *msg, int state, unsigned int ctrl,
 106                       unsigned int intr)
 107 {
 108         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 109                "intr 0x%04x\n", msg, state, ctrl, intr);
 110 }
 111
 112 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 113 {
 114         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 115         struct onenand_chip *this = mtd->priv;
 116         unsigned int intr = 0;
 117         unsigned int ctrl, ctrl_mask;
 118         unsigned long timeout;
 119         u32 syscfg;
 120
 121         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 122             state == FL_VERIFYING_ERASE) {
 123                 int i = 21;
 124                 unsigned int intr_flags = ONENAND_INT_MASTER;
 125
 126                 switch (state) {
 127                 case FL_RESETING:
 128                         intr_flags |= ONENAND_INT_RESET;
 129                         break;
 130                 case FL_PREPARING_ERASE:
 131                         intr_flags |= ONENAND_INT_ERASE;
 132                         break;
 133                 case FL_VERIFYING_ERASE:
 134                         i = 101;
 135                         break;
 136                 }
 137
 138                 while (--i) {
 139                         udelay(1);
 140                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 141                         if (intr & ONENAND_INT_MASTER)
 142                                 break;
 143                 }
 144                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 145                 if (ctrl & ONENAND_CTRL_ERROR) {
 146                         wait_err("controller error", state, ctrl, intr);
 147                         return -EIO;
 148                 }
 149                 if ((intr & intr_flags) == intr_flags)
 150                         return 0;
 151                 /* Continue in wait for interrupt branch */
 152         }
 153
 154         if (state != FL_READING) {
 155                 int result;
 156
 157                 /* Turn interrupts on */
 158                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 159                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 160                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 161                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 162                         if (cpu_is_omap34xx())
 163                                 /* Add a delay to let GPIO settle */
 164                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 165                 }
 166
 167                 INIT_COMPLETION(c->irq_done);
 168                 if (c->gpio_irq) {
 169                         result = gpio_get_value(c->gpio_irq);
 170                         if (result == -1) {
 171                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 172                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 173                                 wait_err("gpio error", state, ctrl, intr);
 174                                 return -EIO;
 175                         }
 176                 } else
 177                         result = 0;
 178                 if (result == 0) {
 179                         int retry_cnt = 0;
 180 retry:
 181                         result = wait_for_completion_timeout(&c->irq_done,
 182                                                     msecs_to_jiffies(20));
 183                         if (result == 0) {
 184                                 /* Timeout after 20ms */
 185                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 186                                 if (ctrl & ONENAND_CTRL_ONGO &&
 187                                     !this->ongoing) {
 188                                         /*
 189                                          * The operation seems to be still going
 190                                          * so give it some more time.
 191                                          */
 192                                         retry_cnt += 1;
 193                                         if (retry_cnt < 3)
 194                                                 goto retry;
 195                                         intr = read_reg(c,
 196                                                         ONENAND_REG_INTERRUPT);
 197                                         wait_err("timeout", state, ctrl, intr);
 198                                         return -EIO;
 199                                 }
 200                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 201                                 if ((intr & ONENAND_INT_MASTER) == 0)
 202                                         wait_warn("timeout", state, ctrl, intr);
 203                         }
 204                 }
 205         } else {
 206                 int retry_cnt = 0;
 207
 208                 /* Turn interrupts off */
 209                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 210                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 211                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 212
 213                 timeout = jiffies + msecs_to_jiffies(20);
 214                 while (1) {
 215                         if (time_before(jiffies, timeout)) {
 216                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 217                                 if (intr & ONENAND_INT_MASTER)
 218                                         break;
 219                         } else {
 220                                 /* Timeout after 20ms */
 221                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 222                                 if (ctrl & ONENAND_CTRL_ONGO) {
 223                                         /*
 224                                          * The operation seems to be still going
 225                                          * so give it some more time.
 226                                          */
 227                                         retry_cnt += 1;
 228                                         if (retry_cnt < 3) {
 229                                                 timeout = jiffies +
 230                                                           msecs_to_jiffies(20);
 231                                                 continue;
 232                                         }
 233                                 }
 234                                 break;
 235                         }
 236                 }
 237         }
 238
 239         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 240         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 241
 242         if (intr & ONENAND_INT_READ) {
 243                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 244
 245                 if (ecc) {
 246                         unsigned int addr1, addr8;
 247
 248                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 249                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 250                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 251                                 printk(KERN_ERR "onenand_wait: ECC error = "
 252                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 253                                        ecc, addr1, addr8);
 254                                 mtd->ecc_stats.failed++;
 255                                 return -EBADMSG;
 256                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 257                                 printk(KERN_NOTICE "onenand_wait: correctable "
 258                                        "ECC error = 0x%04x, addr1 %#x, "
 259                                        "addr8 %#x\n", ecc, addr1, addr8);
 260                                 mtd->ecc_stats.corrected++;
 261                         }
 262                 }
 263         } else if (state == FL_READING) {
 264                 wait_err("timeout", state, ctrl, intr);
 265                 return -EIO;
 266         }
 267
 268         if (ctrl & ONENAND_CTRL_ERROR) {
 269                 wait_err("controller error", state, ctrl, intr);
 270                 if (ctrl & ONENAND_CTRL_LOCK)
 271                         printk(KERN_ERR "onenand_wait: "
 272                                         "Device is write protected!!!\n");
 273                 return -EIO;
 274         }
 275
 276         ctrl_mask = 0xFE9F;
 277         if (this->ongoing)
 278                 ctrl_mask &= ~0x8000;
 279
 280         if (ctrl & ctrl_mask)
 281                 wait_warn("unexpected controller status", state, ctrl, intr);
 282
 283         return 0;
 284 }
 285
 286 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 287 {
 288         struct onenand_chip *this = mtd->priv;
 289
 290         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 291                 if (area == ONENAND_DATARAM)
 292                         return this->writesize;
 293                 if (area == ONENAND_SPARERAM)
 294                         return mtd->oobsize;
 295         }
 296
 297         return 0;
 298 }
 299
 300 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 301
 302 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 303                                         unsigned char *buffer, int offset,
 304                                         size_t count)
 305 {
 306         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 307         struct onenand_chip *this = mtd->priv;
 308         dma_addr_t dma_src, dma_dst;
 309         int bram_offset;
 310         unsigned long timeout;
 311         void *buf = (void *)buffer;
 312         size_t xtra;
 313         volatile unsigned *done;
 314
 315         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 316         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 317                 goto out_copy;
 318
 319         /* panic_write() may be in an interrupt context */
 320         if (in_interrupt() || oops_in_progress)
 321                 goto out_copy;
 322
 323         if (buf >= high_memory) {
 324                 struct page *p1;
 325
 326                 if (((size_t)buf & PAGE_MASK) !=
 327                     ((size_t)(buf + count - 1) & PAGE_MASK))
 328                         goto out_copy;
 329                 p1 = vmalloc_to_page(buf);
 330                 if (!p1)
 331                         goto out_copy;
 332                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 333         }
 334
 335         xtra = count & 3;
 336         if (xtra) {
 337                 count -= xtra;
 338                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 339         }
 340
 341         dma_src = c->phys_base + bram_offset;
 342         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 343         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 344                 dev_err(&c->pdev->dev,
 345                         "Couldn't DMA map a %d byte buffer\n",
 346                         count);
 347                 goto out_copy;
 348         }
 349
 350         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 351                                      count >> 2, 1, 0, 0, 0);
 352         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 353                                 dma_src, 0, 0);
 354         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 355                                  dma_dst, 0, 0);
 356
 357         INIT_COMPLETION(c->dma_done);
 358         omap_start_dma(c->dma_channel);
 359
 360         timeout = jiffies + msecs_to_jiffies(20);
 361         done = &c->dma_done.done;
 362         while (time_before(jiffies, timeout))
 363                 if (*done)
 364                         break;
 365
 366         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 367
 368         if (!*done) {
 369                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 370                 goto out_copy;
 371         }
 372
 373         return 0;
 374
 375 out_copy:
 376         memcpy(buf, this->base + bram_offset, count);
 377         return 0;
 378 }
 379
 380 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 381                                          const unsigned char *buffer,
 382                                          int offset, size_t count)
 383 {
 384         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 385         struct onenand_chip *this = mtd->priv;
 386         dma_addr_t dma_src, dma_dst;
 387         int bram_offset;
 388         unsigned long timeout;
 389         void *buf = (void *)buffer;
 390         volatile unsigned *done;
 391
 392         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 393         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 394                 goto out_copy;
 395
 396         /* panic_write() may be in an interrupt context */
 397         if (in_interrupt() || oops_in_progress)
 398                 goto out_copy;
 399
 400         if (buf >= high_memory) {
 401                 struct page *p1;
 402
 403                 if (((size_t)buf & PAGE_MASK) !=
 404                     ((size_t)(buf + count - 1) & PAGE_MASK))
 405                         goto out_copy;
 406                 p1 = vmalloc_to_page(buf);
 407                 if (!p1)
 408                         goto out_copy;
 409                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 410         }
 411
 412         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 413         dma_dst = c->phys_base + bram_offset;
 414         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 415                 dev_err(&c->pdev->dev,
 416                         "Couldn't DMA map a %d byte buffer\n",
 417                         count);
 418                 return -1;
 419         }
 420
 421         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 422                                      count >> 2, 1, 0, 0, 0);
 423         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 424                                 dma_src, 0, 0);
 425         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 426                                  dma_dst, 0, 0);
 427
 428         INIT_COMPLETION(c->dma_done);
 429         omap_start_dma(c->dma_channel);
 430
 431         timeout = jiffies + msecs_to_jiffies(20);
 432         done = &c->dma_done.done;
 433         while (time_before(jiffies, timeout))
 434                 if (*done)
 435                         break;
 436
 437         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 438
 439         if (!*done) {
 440                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 441                 goto out_copy;
 442         }
 443
 444         return 0;
 445
 446 out_copy:
 447         memcpy(this->base + bram_offset, buf, count);
 448         return 0;
 449 }
 450
 451 #else
 452
 453 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 454                                  unsigned char *buffer, int offset,
 455                                  size_t count);
 456
 457 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 458                                   const unsigned char *buffer,
 459                                   int offset, size_t count);
 460
 461 #endif
 462
 463 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
 464
 465 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 466                                         unsigned char *buffer, int offset,
 467                                         size_t count)
 468 {
 469         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 470         struct onenand_chip *this = mtd->priv;
 471         dma_addr_t dma_src, dma_dst;
 472         int bram_offset;
 473
 474         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 475         /* DMA is not used.  Revisit PM requirements before enabling it. */
 476         if (1 || (c->dma_channel < 0) ||
 477             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 478             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 479                 memcpy(buffer, (__force void *)(this->base + bram_offset),
 480                        count);
 481                 return 0;
 482         }
 483
 484         dma_src = c->phys_base + bram_offset;
 485         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
 486                                  DMA_FROM_DEVICE);
 487         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 488                 dev_err(&c->pdev->dev,
 489                         "Couldn't DMA map a %d byte buffer\n",
 490                         count);
 491                 return -1;
 492         }
 493
 494         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 495                                      count / 4, 1, 0, 0, 0);
 496         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 497                                 dma_src, 0, 0);
 498         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 499                                  dma_dst, 0, 0);
 500
 501         INIT_COMPLETION(c->dma_done);
 502         omap_start_dma(c->dma_channel);
 503         wait_for_completion(&c->dma_done);
 504
 505         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 506
 507         return 0;
 508 }
 509
 510 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 511                                          const unsigned char *buffer,
 512                                          int offset, size_t count)
 513 {
 514         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 515         struct onenand_chip *this = mtd->priv;
 516         dma_addr_t dma_src, dma_dst;
 517         int bram_offset;
 518
 519         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 520         /* DMA is not used.  Revisit PM requirements before enabling it. */
 521         if (1 || (c->dma_channel < 0) ||
 522             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 523             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 524                 memcpy((__force void *)(this->base + bram_offset), buffer,
 525                        count);
 526                 return 0;
 527         }
 528
 529         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
 530                                  DMA_TO_DEVICE);
 531         dma_dst = c->phys_base + bram_offset;
 532         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 533                 dev_err(&c->pdev->dev,
 534                         "Couldn't DMA map a %d byte buffer\n",
 535                         count);
 536                 return -1;
 537         }
 538
 539         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 540                                      count / 2, 1, 0, 0, 0);
 541         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 542                                 dma_src, 0, 0);
 543         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 544                                  dma_dst, 0, 0);
 545
 546         INIT_COMPLETION(c->dma_done);
 547         omap_start_dma(c->dma_channel);
 548         wait_for_completion(&c->dma_done);
 549
 550         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 551
 552         return 0;
 553 }
 554
 555 #else
 556
 557 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 558                                  unsigned char *buffer, int offset,
 559                                  size_t count);
 560
 561 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 562                                   const unsigned char *buffer,
 563                                   int offset, size_t count);
 564
 565 #endif
 566
 567 static struct platform_driver omap2_onenand_driver;
 568
 569 static int __adjust_timing(struct device *dev, void *data)
 570 {
 571         int ret = 0;
 572         struct omap2_onenand *c;
 573
 574         c = dev_get_drvdata(dev);
 575
 576         BUG_ON(c->setup == NULL);
 577
 578         /* DMA is not in use so this is all that is needed */
 579         /* Revisit for OMAP3! */
 580         ret = c->setup(c->onenand.base, &c->freq);
 581
 582         return ret;
 583 }
 584
 585 int omap2_onenand_rephase(void)
 586 {
 587         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 588                                       NULL, __adjust_timing);
 589 }
 590
 591 static void omap2_onenand_shutdown(struct platform_device *pdev)
 592 {
 593         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 594
 595         /* With certain content in the buffer RAM, the OMAP boot ROM code
 596          * can recognize the flash chip incorrectly. Zero it out before
 597          * soft reset.
 598          */
 599         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 600 }
 601
 602 static int omap2_onenand_enable(struct mtd_info *mtd)
 603 {
 604         int ret;
 605         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 606
 607         ret = regulator_enable(c->regulator);
 608         if (ret != 0)
 609                 dev_err(&c->pdev->dev, "can't enable regulator\n");
 610
 611         return ret;
 612 }
 613
 614 static int omap2_onenand_disable(struct mtd_info *mtd)
 615 {
 616         int ret;
 617         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 618
 619         ret = regulator_disable(c->regulator);
 620         if (ret != 0)
 621                 dev_err(&c->pdev->dev, "can't disable regulator\n");
 622
 623         return ret;
 624 }
 625
 626 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 627 {
 628         struct omap_onenand_platform_data *pdata;
 629         struct omap2_onenand *c;
 630         struct onenand_chip *this;
 631         int r;
 632
 633         pdata = pdev->dev.platform_data;
 634         if (pdata == NULL) {
 635                 dev_err(&pdev->dev, "platform data missing\n");
 636                 return -ENODEV;
 637         }
 638
 639         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 640         if (!c)
 641                 return -ENOMEM;
 642
 643         init_completion(&c->irq_done);
 644         init_completion(&c->dma_done);
 645         c->gpmc_cs = pdata->cs;
 646         c->gpio_irq = pdata->gpio_irq;
 647         c->dma_channel = pdata->dma_channel;
 648         if (c->dma_channel < 0) {
 649                 /* if -1, don't use DMA */
 650                 c->gpio_irq = 0;
 651         }
 652
 653         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
 654         if (r < 0) {
 655                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 656                 goto err_kfree;
 657         }
 658
 659         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
 660                                pdev->dev.driver->name) == NULL) {
 661                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
 662                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
 663                 r = -EBUSY;
 664                 goto err_free_cs;
 665         }
 666         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
 667         if (c->onenand.base == NULL) {
 668                 r = -ENOMEM;
 669                 goto err_release_mem_region;
 670         }
 671
 672         if (pdata->onenand_setup != NULL) {
 673                 r = pdata->onenand_setup(c->onenand.base, &c->freq);
 674                 if (r < 0) {
 675                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 676                                 "%d\n", r);
 677                         goto err_iounmap;
 678                 }
 679                 c->setup = pdata->onenand_setup;
 680         }
 681
 682         if (c->gpio_irq) {
 683                 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
 684                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 685                                 "OneNAND\n", c->gpio_irq);
 686                         goto err_iounmap;
 687         }
 688         gpio_direction_input(c->gpio_irq);
 689
 690         if ((r = request_irq(gpio_to_irq(c->gpio_irq),
 691                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 692                              pdev->dev.driver->name, c)) < 0)
 693                 goto err_release_gpio;
 694         }
 695
 696         if (c->dma_channel >= 0) {
 697                 r = omap_request_dma(0, pdev->dev.driver->name,
 698                                      omap2_onenand_dma_cb, (void *) c,
 699                                      &c->dma_channel);
 700                 if (r == 0) {
 701                         omap_set_dma_write_mode(c->dma_channel,
 702                                                 OMAP_DMA_WRITE_NON_POSTED);
 703                         omap_set_dma_src_data_pack(c->dma_channel, 1);
 704                         omap_set_dma_src_burst_mode(c->dma_channel,
 705                                                     OMAP_DMA_DATA_BURST_8);
 706                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
 707                         omap_set_dma_dest_burst_mode(c->dma_channel,
 708                                                      OMAP_DMA_DATA_BURST_8);
 709                 } else {
 710                         dev_info(&pdev->dev,
 711                                  "failed to allocate DMA for OneNAND, "
 712                                  "using PIO instead\n");
 713                         c->dma_channel = -1;
 714                 }
 715         }
 716
 717         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 718                  "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
 719                  c->onenand.base, c->freq);
 720
 721         c->pdev = pdev;
 722         c->mtd.name = dev_name(&pdev->dev);
 723         c->mtd.priv = &c->onenand;
 724         c->mtd.owner = THIS_MODULE;
 725
 726         c->mtd.dev.parent = &pdev->dev;
 727
 728         this = &c->onenand;
 729         if (c->dma_channel >= 0) {
 730                 this->wait = omap2_onenand_wait;
 731                 if (cpu_is_omap34xx()) {
 732                         this->read_bufferram = omap3_onenand_read_bufferram;
 733                         this->write_bufferram = omap3_onenand_write_bufferram;
 734                 } else {
 735                         this->read_bufferram = omap2_onenand_read_bufferram;
 736                         this->write_bufferram = omap2_onenand_write_bufferram;
 737                 }
 738         }
 739
 740         if (pdata->regulator_can_sleep) {
 741                 c->regulator = regulator_get(&pdev->dev, "vonenand");
 742                 if (IS_ERR(c->regulator)) {
 743                         dev_err(&pdev->dev,  "Failed to get regulator\n");
 744                         goto err_release_dma;
 745                 }
 746                 c->onenand.enable = omap2_onenand_enable;
 747                 c->onenand.disable = omap2_onenand_disable;
 748         }
 749
 750         if (pdata->skip_initial_unlocking)
 751                 this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
 752
 753         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 754                 goto err_release_regulator;
 755
 756         r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0);
 757         if (r > 0)
 758                 r = mtd_device_register(&c->mtd, c->parts, r);
 759         else if (pdata->parts != NULL)
 760                 r = mtd_device_register(&c->mtd, pdata->parts, pdata->nr_parts);
 761         else
 762                 r = mtd_device_register(&c->mtd, NULL, 0);
 763         if (r)
 764                 goto err_release_onenand;
 765
 766         platform_set_drvdata(pdev, c);
 767
 768         return 0;
 769
 770 err_release_onenand:
 771         onenand_release(&c->mtd);
 772 err_release_regulator:
 773         regulator_put(c->regulator);
 774 err_release_dma:
 775         if (c->dma_channel != -1)
 776                 omap_free_dma(c->dma_channel);
 777         if (c->gpio_irq)
 778                 free_irq(gpio_to_irq(c->gpio_irq), c);
 779 err_release_gpio:
 780         if (c->gpio_irq)
 781                 gpio_free(c->gpio_irq);
 782 err_iounmap:
 783         iounmap(c->onenand.base);
 784 err_release_mem_region:
 785         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 786 err_free_cs:
 787         gpmc_cs_free(c->gpmc_cs);
 788 err_kfree:
 789         kfree(c->parts);
 790         kfree(c);
 791
 792         return r;
 793 }
 794
 795 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 796 {
 797         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 798
 799         onenand_release(&c->mtd);
 800         regulator_put(c->regulator);
 801         if (c->dma_channel != -1)
 802                 omap_free_dma(c->dma_channel);
 803         omap2_onenand_shutdown(pdev);
 804         platform_set_drvdata(pdev, NULL);
 805         if (c->gpio_irq) {
 806                 free_irq(gpio_to_irq(c->gpio_irq), c);
 807                 gpio_free(c->gpio_irq);
 808         }
 809         iounmap(c->onenand.base);
 810         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 811         gpmc_cs_free(c->gpmc_cs);
 812         kfree(c->parts);
 813         kfree(c);
 814
 815         return 0;
 816 }
 817
 818 static struct platform_driver omap2_onenand_driver = {
 819         .probe          = omap2_onenand_probe,
 820         .remove         = __devexit_p(omap2_onenand_remove),
 821         .shutdown       = omap2_onenand_shutdown,
 822         .driver         = {
 823                 .name   = DRIVER_NAME,
 824                 .owner  = THIS_MODULE,
 825         },
 826 };
 827
 828 static int __init omap2_onenand_init(void)
 829 {
 830         printk(KERN_INFO "OneNAND driver initializing\n");
 831         return platform_driver_register(&omap2_onenand_driver);
 832 }
 833
 834 static void __exit omap2_onenand_exit(void)
 835 {
 836         platform_driver_unregister(&omap2_onenand_driver);
 837 }
 838
 839 module_init(omap2_onenand_init);
 840 module_exit(omap2_onenand_exit);
 841
 842 MODULE_ALIAS("platform:" DRIVER_NAME);
 843 MODULE_LICENSE("GPL");
 844 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 845 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");