drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.c

   1 /*
   2  * Samsung Exynos5 SoC series FIMC-IS driver
   3  *
   4  * exynos5 fimc-is helper functions
   5  *
   6  * Copyright (c) 2011 Samsung Electronics Co., Ltd
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/clk.h>
  17 #include <linux/irq.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/memory.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/videodev2.h>
  28 #include <media/v4l2-subdev.h>
  29 #include <linux/videodev2.h>
  30 #include <linux/videodev2_exynos_camera.h>
  31 #include <linux/gpio.h>
  32 #include <plat/gpio-cfg.h>
  33 #include <media/exynos_fimc_is.h>
  34
  35
  36 #include "fimc-is-core.h"
  37 #include "fimc-is-regs.h"
  38 #include "fimc-is-cmd.h"
  39 #include "fimc-is-param.h"
  40 #include "fimc-is-err.h"
  41 #include "fimc-is-helper.h"
  42 #include "fimc-is-misc.h"
  43
  44
  45
  46 /*
  47 Default setting values
  48 */
  49 static const struct sensor_param init_val_sensor_preview_still = {
  50         .frame_rate = {
  51                 .frame_rate = DEFAULT_PREVIEW_STILL_FRAMERATE,
  52         },
  53 };
  54
  55 static const struct isp_param init_val_isp_preview_still = {
  56         .control = {
  57                 .cmd = CONTROL_COMMAND_START,
  58                 .bypass = CONTROL_BYPASS_DISABLE,
  59                 .err = CONTROL_ERROR_NO,
  60         },
  61         .otf_input = {
  62                 .cmd = OTF_INPUT_COMMAND_ENABLE,
  63                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
  64                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
  65                 .format = OTF_INPUT_FORMAT_BAYER,
  66                 .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
  67                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
  68                 .crop_offset_x = 0,
  69                 .crop_offset_y = 0,
  70                 .crop_width = 0,
  71                 .crop_height = 0,
  72                 .frametime_min = 0,
  73                 .frametime_max = 33333,
  74                 .err = OTF_INPUT_ERROR_NO,
  75         },
  76         .dma1_input = {
  77                 .cmd = DMA_INPUT_COMMAND_DISABLE,
  78                 .width = 0,
  79                 .height = 0,
  80                 .format = 0,
  81                 .bitwidth = 0,
  82                 .plane = 0,
  83                 .order = 0,
  84                 .buffer_number = 0,
  85                 .buffer_address = 0,
  86                 .err = 0,
  87         },
  88         .dma2_input = {
  89                 .cmd = DMA_INPUT_COMMAND_DISABLE,
  90                 .width = 0, .height = 0,
  91                 .format = 0, .bitwidth = 0, .plane = 0,
  92                 .order = 0, .buffer_number = 0, .buffer_address = 0,
  93                 .err = 0,
  94         },
  95         .aa = {
  96                 .cmd = ISP_AA_COMMAND_START,
  97                 .target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
  98                                                 ISP_AA_TARGET_AWB,
  99                 .mode = 0,
 100                 .scene = 0,
 101                 .sleep = 0,
 102                 .face = 0,
 103                 .touch_x = 0, .touch_y = 0,
 104                 .manual_af_setting = 0,
 105                 .err = ISP_AF_ERROR_NO,
 106         },
 107         .flash = {
 108                 .cmd = ISP_FLASH_COMMAND_DISABLE,
 109                 .redeye = ISP_FLASH_REDEYE_DISABLE,
 110                 .err = ISP_FLASH_ERROR_NO,
 111         },
 112         .awb = {
 113                 .cmd = ISP_AWB_COMMAND_AUTO,
 114                 .illumination = 0,
 115                 .err = ISP_AWB_ERROR_NO,
 116         },
 117         .effect = {
 118                 .cmd = ISP_IMAGE_EFFECT_DISABLE,
 119                 .err = ISP_IMAGE_EFFECT_ERROR_NO,
 120         },
 121         .iso = {
 122                 .cmd = ISP_ISO_COMMAND_AUTO,
 123                 .value = 0,
 124                 .err = ISP_ISO_ERROR_NO,
 125         },
 126         .adjust = {
 127                 .cmd = ISP_ADJUST_COMMAND_AUTO,
 128                 .contrast = 0,
 129                 .saturation = 0,
 130                 .sharpness = 0,
 131                 .exposure = 0,
 132                 .brightness = 0,
 133                 .hue = 0,
 134                 .err = ISP_ADJUST_ERROR_NO,
 135         },
 136         .metering = {
 137                 .cmd = ISP_METERING_COMMAND_CENTER,
 138                 .win_pos_x = 0, .win_pos_y = 0,
 139                 .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
 140                 .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
 141                 .err = ISP_METERING_ERROR_NO,
 142         },
 143         .afc = {
 144                 .cmd = ISP_AFC_COMMAND_AUTO,
 145                 .manual = 0, .err = ISP_AFC_ERROR_NO,
 146         },
 147         .otf_output = {
 148                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 149                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 150                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 151                 .format = OTF_OUTPUT_FORMAT_YUV444,
 152                 .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
 153                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 154                 .err = OTF_OUTPUT_ERROR_NO,
 155         },
 156         .dma1_output = {
 157 #ifdef DZOOM_EVT0
 158                 .cmd = DMA_OUTPUT_COMMAND_ENABLE,
 159                 .dma_out_mask = 0xFFFFFFFF,
 160 #else
 161                 .cmd = DMA_OUTPUT_COMMAND_DISABLE,
 162                 .dma_out_mask = 0,
 163 #endif
 164                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 165                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 166                 .format = DMA_INPUT_FORMAT_YUV444,
 167                 .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
 168                 .plane = DMA_INPUT_PLANE_1,
 169                 .order = DMA_INPUT_ORDER_YCbCr,
 170                 .buffer_number = 0,
 171                 .buffer_address = 0,
 172                 .err = DMA_OUTPUT_ERROR_NO,
 173         },
 174         .dma2_output = {
 175                 .cmd = DMA_OUTPUT_COMMAND_DISABLE,
 176                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 177                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 178                 .format = DMA_OUTPUT_FORMAT_BAYER,
 179                 .bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
 180                 .plane = DMA_OUTPUT_PLANE_1,
 181                 .order = DMA_OUTPUT_ORDER_GB_BG,
 182                 .buffer_number = 0,
 183                 .buffer_address = 0,
 184                 .dma_out_mask = 0xFFFFFFFF,
 185                 .err = DMA_OUTPUT_ERROR_NO,
 186         },
 187 };
 188
 189 static const struct drc_param init_val_drc_preview_still = {
 190         .control = {
 191                 .cmd = CONTROL_COMMAND_START,
 192                 .bypass = CONTROL_BYPASS_DISABLE,
 193                 .err = CONTROL_ERROR_NO,
 194         },
 195         .otf_input = {
 196                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 197                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 198                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 199                 .format = OTF_INPUT_FORMAT_YUV444,
 200                 .bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
 201                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 202                 .err = OTF_INPUT_ERROR_NO,
 203         },
 204         .dma_input = {
 205                 .cmd = DMA_INPUT_COMMAND_DISABLE,
 206                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 207                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 208                 .format = DMA_INPUT_FORMAT_YUV444,
 209                 .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
 210                 .plane = DMA_INPUT_PLANE_1,
 211                 .order = DMA_INPUT_ORDER_YCbCr,
 212                 .buffer_number = 0,
 213                 .buffer_address = 0,
 214                 .err = 0,
 215         },
 216         .otf_output = {
 217                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 218                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 219                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 220                 .format = OTF_OUTPUT_FORMAT_YUV444,
 221                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 222                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 223                 .err = OTF_OUTPUT_ERROR_NO,
 224         },
 225 };
 226
 227 static const struct scalerc_param init_val_scalerc_preview_still = {
 228         .control = {
 229                 .cmd = CONTROL_COMMAND_START,
 230                 .bypass = CONTROL_BYPASS_ENABLE,
 231                 .err = CONTROL_ERROR_NO,
 232         },
 233         .otf_input = {
 234                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 235                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 236                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 237                 .format = OTF_INPUT_FORMAT_YUV444,
 238                 .bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
 239                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 240                 .crop_offset_x = 0,
 241                 .crop_offset_y = 0,
 242                 .crop_width = 0,
 243                 .crop_height = 0,
 244                 .err = OTF_INPUT_ERROR_NO,
 245         },
 246         .effect = {
 247                 .cmd = 0,
 248                 .err = 0,
 249         },
 250         .input_crop = {
 251                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 252                 .pos_x = 0,
 253                 .pos_y = 0,
 254                 .crop_width = DEFAULT_CAPTURE_STILL_CROP_WIDTH,
 255                 .crop_height = DEFAULT_CAPTURE_STILL_CROP_HEIGHT,
 256                 .in_width = DEFAULT_CAPTURE_STILL_WIDTH,
 257                 .in_height = DEFAULT_CAPTURE_STILL_HEIGHT,
 258                 .out_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 259                 .out_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 260                 .err = 0,
 261         },
 262         .output_crop = {
 263                 .cmd = OTF_INPUT_COMMAND_DISABLE,
 264                 .pos_x = 0,
 265                 .pos_y = 0,
 266                 .crop_width = DEFAULT_CAPTURE_STILL_WIDTH,
 267                 .crop_height = DEFAULT_CAPTURE_STILL_HEIGHT,
 268                 .format = DMA_OUTPUT_FORMAT_YUV422,
 269                 .err = 0,
 270         },
 271         .otf_output = {
 272                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 273                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 274                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 275                 .format = OTF_OUTPUT_FORMAT_YUV444,
 276                 .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
 277                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 278                 .err = OTF_OUTPUT_ERROR_NO,
 279         },
 280         .dma_output = {
 281                 .cmd = DMA_OUTPUT_COMMAND_DISABLE,
 282                 .width = DEFAULT_CAPTURE_STILL_WIDTH,
 283                 .height = DEFAULT_CAPTURE_STILL_HEIGHT,
 284                 .format = DMA_OUTPUT_FORMAT_YUV422,
 285                 .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
 286                 .plane = DMA_OUTPUT_PLANE_1,
 287                 .order = DMA_OUTPUT_ORDER_CrYCbY,
 288                 .buffer_number = 0,
 289                 .buffer_address = 0,
 290                 .dma_out_mask = 0xffff,
 291                 .reserved[0] = 2, /* unscaled*/
 292                 .err = DMA_OUTPUT_ERROR_NO,
 293         },
 294 };
 295
 296 static const struct odc_param init_val_odc_preview_still = {
 297         .control = {
 298                 .cmd = CONTROL_COMMAND_START,
 299                 .bypass = CONTROL_BYPASS_ENABLE,
 300                 .err = CONTROL_ERROR_NO,
 301         },
 302         .otf_input = {
 303                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 304                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 305                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 306                 .format = OTF_INPUT_FORMAT_YUV422,
 307                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 308                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 309                 .crop_offset_x = 0,
 310                 .crop_offset_y = 0,
 311                 .crop_width = 0,
 312                 .crop_height = 0,
 313                 .err = OTF_INPUT_ERROR_NO,
 314         },
 315         .otf_output = {
 316                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 317                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 318                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 319                 .format = OTF_OUTPUT_FORMAT_YUV422,
 320                 .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
 321                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 322                 .err = OTF_OUTPUT_ERROR_NO,
 323         },
 324 };
 325
 326 static const struct dis_param init_val_dis_preview_still = {
 327         .control = {
 328                 .cmd = CONTROL_COMMAND_START,
 329                 .bypass = CONTROL_BYPASS_ENABLE,
 330                 .err = CONTROL_ERROR_NO,
 331         },
 332         .otf_input = {
 333                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 334                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 335                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 336                 .format = OTF_INPUT_FORMAT_YUV422,
 337                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 338                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 339                 .crop_offset_x = 0,
 340                 .crop_offset_y = 0,
 341                 .crop_width = 0,
 342                 .crop_height = 0,
 343                 .err = OTF_INPUT_ERROR_NO,
 344         },
 345         .otf_output = {
 346                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 347                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 348                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 349                 .format = OTF_OUTPUT_FORMAT_YUV422,
 350                 .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
 351                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 352                 .err = OTF_OUTPUT_ERROR_NO,
 353         },
 354 };
 355 static const struct tdnr_param init_val_tdnr_preview_still = {
 356         .control = {
 357                 .cmd = CONTROL_COMMAND_START,
 358                 .bypass = CONTROL_BYPASS_ENABLE,
 359                 .err = CONTROL_ERROR_NO,
 360         },
 361         .otf_input = {
 362                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 363                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 364                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 365                 .format = OTF_INPUT_FORMAT_YUV422,
 366                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 367                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 368                 .err = OTF_INPUT_ERROR_NO,
 369         },
 370         .frame = {
 371                 .cmd = 0,
 372                 .err = 0,
 373         },
 374         .otf_output = {
 375                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 376                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 377                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 378                 .format = OTF_OUTPUT_FORMAT_YUV422,
 379                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 380                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 381                 .err = OTF_OUTPUT_ERROR_NO,
 382         },
 383         .dma_output = {
 384                 .cmd = DMA_OUTPUT_COMMAND_DISABLE,
 385                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 386                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 387                 .format = DMA_OUTPUT_FORMAT_YUV420,
 388                 .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
 389                 .plane = DMA_OUTPUT_PLANE_2,
 390                 .order = DMA_OUTPUT_ORDER_CbCr,
 391                 .buffer_number = 0,
 392                 .buffer_address = 0,
 393                 .dma_out_mask = 0xffff,
 394                 .err = DMA_OUTPUT_ERROR_NO,
 395         },
 396 };
 397
 398 static const struct scalerp_param init_val_scalerp_preview_still = {
 399         .control = {
 400                 .cmd = CONTROL_COMMAND_START,
 401                 .bypass = CONTROL_BYPASS_ENABLE,
 402                 .err = CONTROL_ERROR_NO,
 403         },
 404         .otf_input = {
 405                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 406                 .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 407                 .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 408                 .format = OTF_INPUT_FORMAT_YUV444,
 409                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 410                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 411                 .crop_offset_x = 0,
 412                 .crop_offset_y = 0,
 413                 .crop_width = 0,
 414                 .crop_height = 0,
 415                 .err = OTF_INPUT_ERROR_NO,
 416         },
 417         .effect = {
 418                 .cmd = 0,
 419                 .err = 0,
 420         },
 421         .input_crop = {
 422                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 423                 .pos_x = 0,
 424                 .pos_y = 0,
 425                 .crop_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 426                 .crop_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 427                 .in_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
 428                 .in_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
 429                 .out_width = DEFAULT_PREVIEW_STILL_WIDTH,
 430                 .out_height = DEFAULT_PREVIEW_STILL_HEIGHT,
 431                 .err = 0,
 432         },
 433         .output_crop = {
 434                 .cmd = OTF_INPUT_COMMAND_DISABLE,
 435                 .pos_x = 0,
 436                 .pos_y = 0,
 437                 .crop_width = DEFAULT_PREVIEW_STILL_WIDTH,
 438                 .crop_height = DEFAULT_PREVIEW_STILL_HEIGHT,
 439                 .format = OTF_OUTPUT_FORMAT_YUV420,
 440                 .err = 0,
 441         },
 442         .rotation = {
 443                 .cmd = 0,
 444                 .err = 0,
 445         },
 446         .flip = {
 447                 .cmd = 0,
 448                 .err = 0,
 449         },
 450         .otf_output = {
 451                 .cmd = OTF_OUTPUT_COMMAND_ENABLE,
 452                 .width = DEFAULT_PREVIEW_STILL_WIDTH,
 453                 .height = DEFAULT_PREVIEW_STILL_HEIGHT,
 454                 .format = OTF_INPUT_FORMAT_YUV444,
 455                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 456                 .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
 457                 .err = OTF_OUTPUT_ERROR_NO,
 458         },
 459         .dma_output = {
 460                 .cmd = DMA_OUTPUT_COMMAND_DISABLE,
 461                 .width = DEFAULT_PREVIEW_STILL_WIDTH,
 462                 .height = DEFAULT_PREVIEW_STILL_HEIGHT,
 463                 .format = OTF_OUTPUT_FORMAT_YUV420,
 464                 .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
 465                 .plane = DMA_OUTPUT_PLANE_3,
 466                 .order = DMA_OUTPUT_ORDER_NO,
 467                 .buffer_number = 0,
 468                 .buffer_address = 0,
 469                 .dma_out_mask = 0xffff,
 470                 .err = DMA_OUTPUT_ERROR_NO,
 471         },
 472 };
 473
 474 static const struct fd_param init_val_fd_preview_still = {
 475         .control = {
 476                 .cmd = CONTROL_COMMAND_STOP,
 477                 .bypass = CONTROL_BYPASS_DISABLE,
 478                 .err = CONTROL_ERROR_NO,
 479         },
 480         .otf_input = {
 481                 .cmd = OTF_INPUT_COMMAND_ENABLE,
 482                 .width = DEFAULT_PREVIEW_STILL_WIDTH,
 483                 .height = DEFAULT_PREVIEW_STILL_HEIGHT,
 484                 .format = OTF_INPUT_FORMAT_YUV444,
 485                 .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
 486                 .order = OTF_INPUT_ORDER_BAYER_GR_BG,
 487                 .err = OTF_INPUT_ERROR_NO,
 488         },
 489         .dma_input = {
 490                 .cmd = DMA_INPUT_COMMAND_DISABLE,
 491                 .width = 0, .height = 0,
 492                 .format = 0, .bitwidth = 0, .plane = 0,
 493                 .order = 0, .buffer_number = 0, .buffer_address = 0,
 494                 .err = 0,
 495         },
 496         .config = {
 497                 .cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
 498                         FD_CONFIG_COMMAND_ROLL_ANGLE |
 499                         FD_CONFIG_COMMAND_YAW_ANGLE |
 500                         FD_CONFIG_COMMAND_SMILE_MODE |
 501                         FD_CONFIG_COMMAND_BLINK_MODE |
 502                         FD_CONFIG_COMMAND_EYES_DETECT |
 503                         FD_CONFIG_COMMAND_MOUTH_DETECT |
 504                         FD_CONFIG_COMMAND_ORIENTATION |
 505                         FD_CONFIG_COMMAND_ORIENTATION_VALUE,
 506                 .max_number = 5,
 507                 .roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
 508                 .yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
 509                 .smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
 510                 .blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
 511                 .eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
 512                 .mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
 513                 .orientation = FD_CONFIG_ORIENTATION_DISABLE,
 514                 .orientation_value = 0,
 515                 .err = ERROR_FD_NO,
 516         },
 517 };
 518
 519 /*
 520  Group 1. Interrupt
 521 */
 522 void fimc_is_hw_set_intgr0_gd0(struct fimc_is_dev *dev)
 523 {
 524         writel(INTGR0_INTGD0, dev->regs + INTGR0);
 525 }
 526
 527 int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is_dev *dev)
 528 {
 529         u32 cfg = readl(dev->regs + INTSR0);
 530         u32 status = INTSR0_GET_INTSD0(cfg);
 531         while (status) {
 532                 cfg = readl(dev->regs + INTSR0);
 533                 status = INTSR0_GET_INTSD0(cfg);
 534         }
 535         return 0;
 536 }
 537
 538 int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is_dev *dev)
 539 {
 540         u32 cfg = readl(dev->regs + INTMSR0);
 541         u32 status = INTMSR0_GET_INTMSD0(cfg);
 542         while (status) {
 543                 cfg = readl(dev->regs + INTMSR0);
 544                 status = INTMSR0_GET_INTMSD0(cfg);
 545         }
 546         return 0;
 547 }
 548
 549 int fimc_is_fw_clear_irq1(struct fimc_is_dev *dev, unsigned int intr_pos)
 550 {
 551         writel((1<<intr_pos), dev->regs + INTCR1);
 552         return 0;
 553 }
 554
 555 int fimc_is_fw_clear_irq1_all(struct fimc_is_dev *dev)
 556 {
 557         writel(0xFF, dev->regs + INTCR1);
 558         return 0;
 559 }
 560 int fimc_is_fw_clear_irq2(struct fimc_is_dev *dev)
 561 {
 562         u32 cfg = readl(dev->regs + INTSR2);
 563
 564         writel(cfg, dev->regs + INTCR2);
 565         return 0;
 566 }
 567
 568 int fimc_is_fw_clear_insr1(struct fimc_is_dev *dev)
 569 {
 570
 571         writel(0, dev->regs + INTGR1);
 572         return 0;
 573 }
 574
 575 /*
 576  Group 2. Common
 577 */
 578 int fimc_is_hw_get_sensor_type(enum exynos5_sensor_id sensor_id,
 579                                 enum exynos5_flite_id flite_id)
 580 {
 581         int id = sensor_id;
 582
 583         if (flite_id == FLITE_ID_A)
 584                 id = sensor_id;
 585         else if (flite_id == FLITE_ID_B)
 586                 id = sensor_id + 100;
 587
 588         return id;
 589 }
 590
 591 int fimc_is_hw_get_sensor_max_framerate(struct fimc_is_dev *dev)
 592 {
 593         int max_framerate = 0;
 594         switch (dev->sensor.sensor_type) {
 595         case SENSOR_S5K3H2_CSI_A:
 596         case SENSOR_S5K3H2_CSI_B:
 597                 max_framerate = 15;
 598                 break;
 599         case SENSOR_S5K3H7_CSI_A:
 600         case SENSOR_S5K3H7_CSI_B:
 601                 max_framerate = 30;
 602                 break;
 603         case SENSOR_S5K6A3_CSI_A:
 604         case SENSOR_S5K6A3_CSI_B:
 605                 max_framerate = 30;
 606                 break;
 607         case SENSOR_S5K4E5_CSI_A:
 608         case SENSOR_S5K4E5_CSI_B:
 609                 max_framerate = 30;
 610                 break;
 611         default:
 612                 max_framerate = 15;
 613         }
 614         return max_framerate;
 615 }
 616
 617 void fimc_is_hw_open_sensor(struct fimc_is_dev *dev, u32 id, u32 sensor_index)
 618 {
 619         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 620         writel(HIC_OPEN_SENSOR, dev->regs + ISSR0);
 621         writel(id, dev->regs + ISSR1);
 622         switch (sensor_index) {
 623         case SENSOR_S5K3H2_CSI_A:
 624                 dev->af.use_af = 1;
 625                 dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_A;
 626                 writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
 627                 writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
 628                 break;
 629         case SENSOR_S5K3H2_CSI_B:
 630                 dev->af.use_af = 1;
 631                 dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_B;
 632                 writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
 633                 writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
 634                 break;
 635         case SENSOR_S5K6A3_CSI_A:
 636                 dev->af.use_af = 0;
 637                 dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_A;
 638                 writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
 639                 writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
 640                 break;
 641         case SENSOR_S5K6A3_CSI_B:
 642                 dev->af.use_af = 0;
 643                 dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_B;
 644                 writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
 645                 writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
 646                 break;
 647         case SENSOR_S5K4E5_CSI_A:
 648                 dev->af.use_af = 1;
 649                 dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_A;
 650                 writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
 651                 writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
 652                 break;
 653         case SENSOR_S5K4E5_CSI_B:
 654                 dev->af.use_af = 1;
 655                 dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_B;
 656                 writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
 657                 writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
 658                 break;
 659         }
 660         /* Parameter3 : Scenario ID(Initial Scenario) */
 661         writel(ISS_PREVIEW_STILL, dev->regs + ISSR4);
 662         fimc_is_hw_set_intgr0_gd0(dev);
 663
 664 }
 665
 666 void fimc_is_hw_close_sensor(struct fimc_is_dev *dev, u32 id)
 667 {
 668         if (dev->sensor.id_dual == id) {
 669                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
 670                 writel(HIC_CLOSE_SENSOR, dev->regs + ISSR0);
 671                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
 672                 writel(dev->sensor.id_dual, dev->regs + ISSR2);
 673                 fimc_is_hw_set_intgr0_gd0(dev);
 674         }
 675 }
 676
 677 void fimc_is_hw_diable_wdt(struct fimc_is_dev *dev)
 678 {
 679         writel(0x0, dev->regs + WDT);
 680 }
 681
 682 void fimc_is_hw_set_low_poweroff(struct fimc_is_dev *dev, int on)
 683 {
 684         if (on) {
 685                 printk(KERN_INFO "Set low poweroff mode\n");
 686                 __raw_writel(0x0, PMUREG_ISP_ARM_OPTION);
 687                 __raw_writel(0x1CF82000, PMUREG_ISP_LOW_POWER_OFF);
 688                 dev->low_power_mode = true;
 689         } else {
 690                 if (dev->low_power_mode) {
 691                         printk(KERN_INFO "Clear low poweroff mode\n");
 692                         __raw_writel(0xFFFFFFFF, PMUREG_ISP_ARM_OPTION);
 693                         __raw_writel(0x8, PMUREG_ISP_LOW_POWER_OFF);
 694                 }
 695                 dev->low_power_mode = false;
 696         }
 697 }
 698
 699 void fimc_is_hw_subip_poweroff(struct fimc_is_dev *dev)
 700 {
 701         /* 1. Make FIMC-IS power-off state */
 702         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 703         writel(HIC_POWER_DOWN, dev->regs + ISSR0);
 704         writel(dev->sensor.id_dual, dev->regs + ISSR1);
 705         fimc_is_hw_set_intgr0_gd0(dev);
 706 }
 707
 708 int fimc_is_hw_a5_power_on(struct fimc_is_dev *isp)
 709 {
 710         u32 cfg;
 711         u32 timeout;
 712
 713         mutex_lock(&isp->lock);
 714
 715         if (isp->low_power_mode)
 716                 fimc_is_hw_set_low_poweroff(isp, false);
 717
 718         dbg("%s\n", __func__);
 719
 720         writel(0x7, PMUREG_ISP_CONFIGURATION);
 721         timeout = 1000;
 722         while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7) != 0x7) {
 723                 if (timeout == 0)
 724                         err("A5 power on failed1\n");
 725                 timeout--;
 726                 udelay(1);
 727         }
 728
 729         enable_mipi();
 730
 731         /* init Clock */
 732         if (isp->pdata->clk_cfg) {
 733                 isp->pdata->clk_cfg(isp->pdev);
 734         } else {
 735                 dev_err(&isp->pdev->dev, "failed to config clock\n");
 736                 goto done;
 737         }
 738
 739         if (isp->pdata->clk_on) {
 740                 isp->pdata->clk_on(isp->pdev);
 741         } else {
 742                 dev_err(&isp->pdev->dev, "failed to clock on\n");
 743                 goto done;
 744         }
 745
 746         /* 1. A5 start address setting */
 747 #if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
 748         cfg = isp->mem.base;
 749 #elif defined(CONFIG_VIDEOBUF2_ION)
 750         cfg = isp->mem.dvaddr;
 751         if (isp->alloc_ctx)
 752                 fimc_is_mem_resume(isp->alloc_ctx);
 753 #endif
 754
 755         dbg("mem.base(dvaddr) : 0x%08x\n", cfg);
 756         dbg("mem.base(kvaddr) : 0x%08x\n", (unsigned int)isp->mem.kvaddr);
 757         writel(cfg, isp->regs + BBOAR);
 758
 759         /* 2. A5 power on*/
 760         writel(0x1, PMUREG_ISP_ARM_CONFIGURATION);
 761
 762         /* 3. enable A5 */
 763         writel(0x00018000, PMUREG_ISP_ARM_OPTION);
 764         timeout = 1000;
 765         while ((__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) != 0x1) {
 766                 if (timeout == 0)
 767                         err("A5 power on failed2\n");
 768                 timeout--;
 769                 udelay(1);
 770         }
 771
 772         /* HACK : fimc_is_irq_handler() cannot
 773          * set 1 on FIMC_IS_PWR_ST_POWER_ON_OFF */
 774         set_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power);
 775
 776 done:
 777         mutex_unlock(&isp->lock);
 778         return 0;
 779 }
 780
 781 int fimc_is_hw_a5_power_off(struct fimc_is_dev *isp)
 782 {
 783         u32 timeout;
 784
 785         dbg("%s\n", __func__);
 786
 787         mutex_lock(&isp->lock);
 788
 789 #if defined(CONFIG_VIDEOBUF2_ION)
 790         if (isp->alloc_ctx)
 791                 fimc_is_mem_suspend(isp->alloc_ctx);
 792 #endif
 793
 794         if (isp->pdata->clk_off) {
 795                 isp->pdata->clk_off(isp->pdev);
 796         } else {
 797                 dev_err(&isp->pdev->dev, "failed to clock on\n");
 798                 goto done;
 799         }
 800         /* 1. disable A5 */
 801         writel(0x0, PMUREG_ISP_ARM_OPTION);
 802
 803         /* 2. A5 power off*/
 804         writel(0x0, PMUREG_ISP_ARM_CONFIGURATION);
 805
 806         /* 3. Check A5 power off status register */
 807         timeout = 1000;
 808         while (__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) {
 809                 if (timeout == 0)
 810                         err("A5 power off failed\n");
 811                 timeout--;
 812                 udelay(1);
 813         }
 814
 815         /* 4. ISP Power down mode (LOWPWR) */
 816         writel(0x0, PMUREG_CMU_RESET_ISP_SYS_PWR_REG);
 817
 818         writel(0x0, PMUREG_ISP_CONFIGURATION);
 819
 820         timeout = 1000;
 821         while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7)) {
 822                 if (timeout == 0) {
 823                         err("ISP power off failed --> Retry\n");
 824                         /* Retry */
 825                         __raw_writel(0x1CF82000, PMUREG_ISP_LOW_POWER_OFF);
 826                         timeout = 1000;
 827                         while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7)) {
 828                                 if (timeout == 0)
 829                                         err("ISP power off failed\n");
 830                                 timeout--;
 831                                 udelay(1);
 832                         }
 833                 }
 834                 timeout--;
 835                 udelay(1);
 836         }
 837
 838 done:
 839         mutex_unlock(&isp->lock);
 840         return 0;
 841 }
 842
 843 void fimc_is_hw_a5_power(struct fimc_is_dev *isp, int on)
 844 {
 845 #if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
 846         struct device *dev = &isp->pdev->dev;
 847 #endif
 848
 849         printk(KERN_INFO "%s(%d)\n", __func__, on);
 850
 851 #if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
 852         if (on)
 853                 pm_runtime_get_sync(dev);
 854         else
 855                 pm_runtime_put_sync(dev);
 856 #else
 857         if (on)
 858                 fimc_is_hw_a5_power_on(isp);
 859         else
 860                 fimc_is_hw_a5_power_off(isp);
 861 #endif
 862 }
 863
 864 void fimc_is_hw_set_sensor_num(struct fimc_is_dev *dev)
 865 {
 866         u32 cfg;
 867         writel(ISR_DONE, dev->regs + ISSR0);
 868         cfg = dev->sensor.id_dual;
 869         writel(cfg, dev->regs + ISSR1);
 870         /* param 1 */
 871         writel(IHC_GET_SENSOR_NUMBER, dev->regs + ISSR2);
 872         /* param 2 */
 873         cfg = dev->sensor_num;
 874         writel(cfg, dev->regs + ISSR3);
 875 }
 876
 877 void fimc_is_hw_get_setfile_addr(struct fimc_is_dev *dev)
 878 {
 879         /* 1. Get FIMC-IS setfile address */
 880         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 881         writel(HIC_GET_SET_FILE_ADDR, dev->regs + ISSR0);
 882         writel(dev->sensor.id_dual, dev->regs + ISSR1);
 883         fimc_is_hw_set_intgr0_gd0(dev);
 884 }
 885
 886 void fimc_is_hw_load_setfile(struct fimc_is_dev *dev)
 887 {
 888         /* 1. Make FIMC-IS power-off state */
 889         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 890         writel(HIC_LOAD_SET_FILE, dev->regs + ISSR0);
 891         writel(dev->sensor.id_dual, dev->regs + ISSR1);
 892         fimc_is_hw_set_intgr0_gd0(dev);
 893 }
 894
 895 int fimc_is_hw_get_sensor_num(struct fimc_is_dev *dev)
 896 {
 897         u32 cfg = readl(dev->regs + ISSR11);
 898         if (dev->sensor_num == cfg)
 899                 return 0;
 900         else
 901                 return cfg;
 902 }
 903
 904 void fimc_is_hw_set_debug_level(struct fimc_is_dev *dev,
 905                                 int target,
 906                                 int module,
 907                                 int level)
 908 {
 909         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 910         writel(HIC_MSG_CONFIG, dev->regs + ISSR0);
 911         writel(dev->sensor.id_dual, dev->regs + ISSR1);
 912
 913         writel(target, dev->regs + ISSR2);
 914         writel(module, dev->regs + ISSR3);
 915         writel(level, dev->regs + ISSR4);
 916         fimc_is_hw_set_intgr0_gd0(dev);
 917 }
 918
 919 int fimc_is_hw_set_param(struct fimc_is_dev *dev)
 920 {
 921         fimc_is_hw_wait_intmsr0_intmsd0(dev);
 922         writel(HIC_SET_PARAMETER, dev->regs + ISSR0);
 923         writel(dev->sensor.id_dual, dev->regs + ISSR1);
 924
 925         writel(dev->scenario_id, dev->regs + ISSR2);
 926
 927         writel(atomic_read(&dev->p_region_num), dev->regs + ISSR3);
 928         writel(dev->p_region_index1, dev->regs + ISSR4);
 929         writel(dev->p_region_index2, dev->regs + ISSR5);
 930         dbg("### set param\n");
 931         dbg("cmd :0x%08x\n", HIC_SET_PARAMETER);
 932         dbg("senorID :0x%08x\n", dev->sensor.id_dual);
 933         dbg("parma1 :0x%08x\n", dev->scenario_id);
 934         dbg("parma2 :0x%08x\n", atomic_read(&dev->p_region_num));
 935         dbg("parma3 :0x%08x\n", (unsigned int)dev->p_region_index1);
 936         dbg("parma4 :0x%08x\n", (unsigned int)dev->p_region_index2);
 937
 938         fimc_is_hw_set_intgr0_gd0(dev);
 939         return 0;
 940 }
 941
 942 int fimc_is_hw_update_bufmask(struct fimc_is_dev *dev, unsigned int dev_num)
 943 {
 944         int buf_mask;
 945         int i = 0;
 946         int cnt = 0;
 947
 948         buf_mask = dev->video[dev_num].buf_mask;
 949
 950         for (i = 0; i < 16; i++) {
 951                 if (((buf_mask & (1 << i)) >> i) == 1)
 952                         cnt++;
 953         }
 954         dbg("dev_num: %u, buf_mask: %#x, cnt: %d\n", dev_num, buf_mask, cnt);
 955
 956         if (cnt == 1) {
 957                 err("ERR: Not enough buffers[dev_num: %u, buf_mask: %#x]\n",
 958                                                         dev_num, buf_mask);
 959                 goto done;
 960         }
 961
 962         switch (dev_num) {
 963         case 0: /* Bayer */
 964                 if (readl(dev->regs + ISSR23) != 0x0)
 965                         dbg("WARN: Bayer buffer mask is unchecked\n");
 966
 967                 writel(buf_mask, dev->regs + ISSR23);
 968                 break;
 969         case 1:  /* Scaler-C */
 970                 if (readl(dev->regs + ISSR31) != 0x0)
 971                         dbg("WARN: Scaler-C buffer mask is unchecked\n");
 972
 973                 writel(buf_mask, dev->regs + ISSR31);
 974                 break;
 975         case 2: /* 3DNR */
 976                 if (readl(dev->regs + ISSR39) != 0x0)
 977                         dbg("WARN: 3DNR buffer mask is unchecked\n");
 978
 979                 writel(buf_mask, dev->regs + ISSR39);
 980                 break;
 981         case 3: /* Scaler-P */
 982                 if (readl(dev->regs + ISSR47) != 0x0)
 983                         dbg("WARN: Scaler-P buffer mask is unchecked\n");
 984
 985                 writel(buf_mask, dev->regs + ISSR47);
 986                 break;
 987         default:
 988                 return -EINVAL;
 989         }
 990
 991 done:
 992         return 0;
 993 }
 994
 995 int fimc_is_hw_get_param(struct fimc_is_dev *dev, u16 offset)
 996 {
 997         dev->i2h_cmd.num_valid_args = offset;
 998         switch (offset) {
 999         case 1:
1000                 dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
1001                 dev->i2h_cmd.arg[1] = 0;
1002                 dev->i2h_cmd.arg[2] = 0;
1003                 dev->i2h_cmd.arg[3] = 0;
1004                 break;
1005         case 2:
1006                 dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
1007                 dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
1008                 dev->i2h_cmd.arg[2] = 0;
1009                 dev->i2h_cmd.arg[3] = 0;
1010                 break;
1011         case 3:
1012                 dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
1013                 dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
1014                 dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
1015                 dev->i2h_cmd.arg[3] = 0;
1016                 break;
1017         case 4:
1018                 dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
1019                 dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
1020                 dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
1021                 dev->i2h_cmd.arg[3] = readl(dev->regs + ISSR15);
1022                 break;
1023         default:
1024                 return -EINVAL;
1025         }
1026
1027         return 0;
1028 }
1029
1030 void fimc_is_hw_set_stream(struct fimc_is_dev *dev, int on)
1031 {
1032         if (on) {
1033                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1034                 writel(HIC_STREAM_ON, dev->regs + ISSR0);
1035                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1036                 fimc_is_hw_set_intgr0_gd0(dev);
1037         } else {
1038                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1039                 writel(HIC_STREAM_OFF, dev->regs + ISSR0);
1040                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1041                 fimc_is_hw_set_intgr0_gd0(dev);
1042         }
1043 }
1044
1045 void fimc_is_hw_change_mode(struct fimc_is_dev *dev, int val)
1046 {
1047         switch (val) {
1048         case IS_MODE_PREVIEW_STILL:
1049                 dev->scenario_id = ISS_PREVIEW_STILL;
1050                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1051                 clear_bit(IS_ST_RUN, &dev->state);
1052                 set_bit(IS_ST_CHANGE_MODE, &dev->state);
1053                 writel(HIC_PREVIEW_STILL, dev->regs + ISSR0);
1054                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1055                 fimc_is_hw_set_intgr0_gd0(dev);
1056                 break;
1057         case IS_MODE_PREVIEW_VIDEO:
1058                 dev->scenario_id = ISS_PREVIEW_VIDEO;
1059                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1060                 clear_bit(IS_ST_RUN, &dev->state);
1061                 set_bit(IS_ST_CHANGE_MODE, &dev->state);
1062                 writel(HIC_PREVIEW_VIDEO, dev->regs + ISSR0);
1063                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1064                 fimc_is_hw_set_intgr0_gd0(dev);
1065                 break;
1066         case IS_MODE_CAPTURE_STILL:
1067                 dev->scenario_id = ISS_CAPTURE_STILL;
1068                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1069                 clear_bit(IS_ST_RUN, &dev->state);
1070                 set_bit(IS_ST_CHANGE_MODE, &dev->state);
1071                 writel(HIC_CAPTURE_STILL, dev->regs + ISSR0);
1072                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1073                 fimc_is_hw_set_intgr0_gd0(dev);
1074                 break;
1075         case IS_MODE_CAPTURE_VIDEO:
1076                 dev->scenario_id = ISS_CAPTURE_VIDEO;
1077                 fimc_is_hw_wait_intmsr0_intmsd0(dev);
1078                 clear_bit(IS_ST_RUN, &dev->state);
1079                 set_bit(IS_ST_CHANGE_MODE, &dev->state);
1080                 writel(HIC_CAPTURE_VIDEO, dev->regs + ISSR0);
1081                 writel(dev->sensor.id_dual, dev->regs + ISSR1);
1082                 fimc_is_hw_set_intgr0_gd0(dev);
1083                 break;
1084         }
1085 }
1086 /*
1087  Group 3. Initial setting
1088 */
1089 void fimc_is_hw_set_init(struct fimc_is_dev *dev)
1090 {
1091         u32 length;
1092
1093
1094         IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 0);
1095         IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
1096         IS_INC_PARAM_NUM(dev);
1097
1098         IS_SENSOR_SET_FRAME_RATE(dev, DEFAULT_PREVIEW_STILL_FRAMERATE);
1099         IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
1100         IS_INC_PARAM_NUM(dev);
1101         /* ISP */
1102         IS_ISP_SET_PARAM_CONTROL_CMD(dev,
1103                 init_val_isp_preview_still.control.cmd);
1104         IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
1105                 init_val_isp_preview_still.control.bypass);
1106         IS_ISP_SET_PARAM_CONTROL_ERR(dev,
1107                 init_val_isp_preview_still.control.err);
1108         IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
1109         IS_INC_PARAM_NUM(dev);
1110         IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
1111                 init_val_isp_preview_still.otf_input.cmd);
1112         IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
1113                 init_val_isp_preview_still.otf_input.width);
1114         IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1115                 init_val_isp_preview_still.otf_input.height);
1116         dev->sensor.width =
1117                 init_val_isp_preview_still.otf_input.width;
1118         dev->sensor.width =
1119                 init_val_isp_preview_still.otf_input.height;
1120         IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
1121                 init_val_isp_preview_still.otf_input.format);
1122         IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1123                 init_val_isp_preview_still.otf_input.bitwidth);
1124         IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
1125                 init_val_isp_preview_still.otf_input.order);
1126         IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
1127                 init_val_isp_preview_still.otf_input.crop_offset_x);
1128         IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
1129                 init_val_isp_preview_still.otf_input.crop_offset_y);
1130         IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
1131                 init_val_isp_preview_still.otf_input.crop_width);
1132         IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
1133                 init_val_isp_preview_still.otf_input.crop_height);
1134         IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
1135                 init_val_isp_preview_still.otf_input.frametime_min);
1136         IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
1137                 init_val_isp_preview_still.otf_input.frametime_max);
1138         IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
1139                 init_val_isp_preview_still.otf_input.err);
1140         IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
1141         IS_INC_PARAM_NUM(dev);
1142         IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
1143                 init_val_isp_preview_still.dma1_input.cmd);
1144         IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
1145                 init_val_isp_preview_still.dma1_input.width);
1146         IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
1147                 init_val_isp_preview_still.dma1_input.height);
1148         IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
1149                 init_val_isp_preview_still.dma1_input.format);
1150         IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
1151                 init_val_isp_preview_still.dma1_input.bitwidth);
1152         IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
1153                 init_val_isp_preview_still.dma1_input.plane);
1154         IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
1155                 init_val_isp_preview_still.dma1_input.order);
1156         IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
1157                 init_val_isp_preview_still.dma1_input.buffer_number);
1158         IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
1159                 init_val_isp_preview_still.dma1_input.buffer_address);
1160         IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
1161                 init_val_isp_preview_still.dma1_input.err);
1162         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
1163         IS_INC_PARAM_NUM(dev);
1164         IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
1165                 init_val_isp_preview_still.dma2_input.cmd);
1166         IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
1167                 init_val_isp_preview_still.dma2_input.width);
1168         IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
1169                 init_val_isp_preview_still.dma2_input.height);
1170         IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
1171                 init_val_isp_preview_still.dma2_input.format);
1172         IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
1173                 init_val_isp_preview_still.dma2_input.bitwidth);
1174         IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
1175                 init_val_isp_preview_still.dma2_input.plane);
1176         IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
1177                 init_val_isp_preview_still.dma2_input.order);
1178         IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
1179                 init_val_isp_preview_still.dma2_input.buffer_number);
1180         IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
1181                 init_val_isp_preview_still.dma2_input.buffer_address);
1182         IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
1183                 init_val_isp_preview_still.dma2_input.err);
1184         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
1185         IS_INC_PARAM_NUM(dev);
1186         IS_ISP_SET_PARAM_AA_CMD(dev,
1187                 init_val_isp_preview_still.aa.cmd);
1188         IS_ISP_SET_PARAM_AA_TARGET(dev,
1189                 init_val_isp_preview_still.aa.target);
1190         IS_ISP_SET_PARAM_AA_MODE(dev,
1191                 init_val_isp_preview_still.aa.mode);
1192         IS_ISP_SET_PARAM_AA_FACE(dev,
1193                 init_val_isp_preview_still.aa.face);
1194         IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
1195                 init_val_isp_preview_still.aa.touch_x);
1196         IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
1197                 init_val_isp_preview_still.aa.touch_y);
1198         IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
1199                 init_val_isp_preview_still.aa.manual_af_setting);
1200         IS_ISP_SET_PARAM_AA_ERR(dev,
1201                 init_val_isp_preview_still.aa.err);
1202         IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
1203         IS_INC_PARAM_NUM(dev);
1204         IS_ISP_SET_PARAM_FLASH_CMD(dev,
1205                 init_val_isp_preview_still.flash.cmd);
1206         IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
1207                 init_val_isp_preview_still.flash.redeye);
1208         IS_ISP_SET_PARAM_FLASH_ERR(dev,
1209                 init_val_isp_preview_still.flash.err);
1210         IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
1211         IS_INC_PARAM_NUM(dev);
1212         IS_ISP_SET_PARAM_AWB_CMD(dev,
1213                 init_val_isp_preview_still.awb.cmd);
1214         IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
1215                 init_val_isp_preview_still.awb.illumination);
1216         IS_ISP_SET_PARAM_AWB_ERR(dev,
1217                 init_val_isp_preview_still.awb.err);
1218         IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
1219         IS_INC_PARAM_NUM(dev);
1220         IS_ISP_SET_PARAM_EFFECT_CMD(dev,
1221                 init_val_isp_preview_still.effect.cmd);
1222         IS_ISP_SET_PARAM_EFFECT_ERR(dev,
1223                 init_val_isp_preview_still.effect.err);
1224         IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
1225         IS_INC_PARAM_NUM(dev);
1226         IS_ISP_SET_PARAM_ISO_CMD(dev,
1227                 init_val_isp_preview_still.iso.cmd);
1228         IS_ISP_SET_PARAM_ISO_VALUE(dev,
1229                 init_val_isp_preview_still.iso.value);
1230         IS_ISP_SET_PARAM_ISO_ERR(dev,
1231                 init_val_isp_preview_still.iso.err);
1232         IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
1233         IS_INC_PARAM_NUM(dev);
1234         IS_ISP_SET_PARAM_ADJUST_CMD(dev,
1235                 init_val_isp_preview_still.adjust.cmd);
1236         IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
1237                 init_val_isp_preview_still.adjust.contrast);
1238         IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
1239                 init_val_isp_preview_still.adjust.saturation);
1240         IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
1241                 init_val_isp_preview_still.adjust.sharpness);
1242         IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
1243                 init_val_isp_preview_still.adjust.exposure);
1244         IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
1245                 init_val_isp_preview_still.adjust.brightness);
1246         IS_ISP_SET_PARAM_ADJUST_HUE(dev,
1247                 init_val_isp_preview_still.adjust.hue);
1248         IS_ISP_SET_PARAM_ADJUST_ERR(dev,
1249                 init_val_isp_preview_still.adjust.err);
1250         IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
1251         IS_INC_PARAM_NUM(dev);
1252         IS_ISP_SET_PARAM_METERING_CMD(dev,
1253                 init_val_isp_preview_still.metering.cmd);
1254         IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
1255                 init_val_isp_preview_still.metering.win_pos_x);
1256         IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
1257                 init_val_isp_preview_still.metering.win_pos_y);
1258         IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
1259                 init_val_isp_preview_still.metering.win_width);
1260         IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
1261                 init_val_isp_preview_still.metering.win_height);
1262         IS_ISP_SET_PARAM_METERING_ERR(dev,
1263                 init_val_isp_preview_still.metering.err);
1264         IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
1265         IS_INC_PARAM_NUM(dev);
1266         IS_ISP_SET_PARAM_AFC_CMD(dev,
1267                 init_val_isp_preview_still.afc.cmd);
1268         IS_ISP_SET_PARAM_AFC_MANUAL(dev,
1269                 init_val_isp_preview_still.afc.manual);
1270         IS_ISP_SET_PARAM_AFC_ERR(dev,
1271                 init_val_isp_preview_still.afc.err);
1272         IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
1273         IS_INC_PARAM_NUM(dev);
1274         IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
1275                 init_val_isp_preview_still.otf_output.cmd);
1276         IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1277                 init_val_isp_preview_still.otf_output.width);
1278         IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1279                 init_val_isp_preview_still.otf_output.height);
1280         IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1281                 init_val_isp_preview_still.otf_output.format);
1282         IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1283                 init_val_isp_preview_still.otf_output.bitwidth);
1284         IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1285                 init_val_isp_preview_still.otf_output.order);
1286         IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
1287                 init_val_isp_preview_still.otf_output.err);
1288         IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
1289         IS_INC_PARAM_NUM(dev);
1290         IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
1291                 init_val_isp_preview_still.dma1_output.cmd);
1292         IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
1293                 init_val_isp_preview_still.dma1_output.width);
1294         IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
1295                 init_val_isp_preview_still.dma1_output.height);
1296         IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
1297                 init_val_isp_preview_still.dma1_output.format);
1298         IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
1299                 init_val_isp_preview_still.dma1_output.bitwidth);
1300         IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
1301                 init_val_isp_preview_still.dma1_output.plane);
1302         IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
1303                 init_val_isp_preview_still.dma1_output.order);
1304 #ifdef DZOOM_EVT0
1305         IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
1306                 1);
1307         dev->is_p_region->shared[100] = (u32)dev->mem.dvaddr_isp;
1308         IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
1309                 (u32)dev->mem.dvaddr_shared + 100*sizeof(u32));
1310         dbg("ISP buf daddr : 0x%08x\n", dev->mem.dvaddr_isp);
1311         dbg("ISP buf kaddr : 0x%08x\n", dev->mem.kvaddr_isp);
1312 #else
1313         IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
1314                 init_val_isp_preview_still.dma1_output.buffer_number);
1315         IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
1316                 init_val_isp_preview_still.dma1_output.buffer_address);
1317 #endif
1318         IS_ISP_SET_PARAM_DMA_OUTPUT1_MASK(dev,
1319                 init_val_isp_preview_still.dma1_output.dma_out_mask);
1320         IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
1321                 init_val_isp_preview_still.dma1_output.err);
1322         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
1323         IS_INC_PARAM_NUM(dev);
1324         IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
1325                 init_val_isp_preview_still.dma2_output.cmd);
1326         IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
1327                 init_val_isp_preview_still.dma2_output.width);
1328         IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
1329                 init_val_isp_preview_still.dma2_output.height);
1330         IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
1331                 init_val_isp_preview_still.dma2_output.format);
1332         IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
1333                 init_val_isp_preview_still.dma2_output.bitwidth);
1334         IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
1335                 init_val_isp_preview_still.dma2_output.plane);
1336         IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
1337                 init_val_isp_preview_still.dma2_output.order);
1338         IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
1339                 init_val_isp_preview_still.dma2_output.buffer_number);
1340         IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
1341                 init_val_isp_preview_still.dma2_output.buffer_address);
1342         IS_ISP_SET_PARAM_DMA_OUTPUT2_MASK(dev,
1343                 init_val_isp_preview_still.dma2_output.dma_out_mask);
1344         IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
1345                 init_val_isp_preview_still.dma2_output.err);
1346         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
1347         IS_INC_PARAM_NUM(dev);
1348
1349         /* DRC */
1350         IS_DRC_SET_PARAM_CONTROL_CMD(dev,
1351                 init_val_drc_preview_still.control.cmd);
1352         IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
1353                 init_val_drc_preview_still.control.bypass);
1354         IS_DRC_SET_PARAM_CONTROL_ERR(dev,
1355                 init_val_drc_preview_still.control.err);
1356         IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
1357         IS_INC_PARAM_NUM(dev);
1358         IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
1359                 init_val_drc_preview_still.otf_input.cmd);
1360         IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
1361                 init_val_drc_preview_still.otf_input.width);
1362         IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1363                 init_val_drc_preview_still.otf_input.height);
1364         IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
1365                 init_val_drc_preview_still.otf_input.format);
1366         IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1367                 init_val_drc_preview_still.otf_input.bitwidth);
1368         IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
1369                 init_val_drc_preview_still.otf_input.order);
1370         IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
1371                 init_val_drc_preview_still.otf_input.err);
1372         IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
1373         IS_INC_PARAM_NUM(dev);
1374         IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
1375                 init_val_drc_preview_still.dma_input.cmd);
1376         IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
1377                 init_val_drc_preview_still.dma_input.width);
1378         IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
1379                 init_val_drc_preview_still.dma_input.height);
1380         IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
1381                 init_val_drc_preview_still.dma_input.format);
1382         IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
1383                 init_val_drc_preview_still.dma_input.bitwidth);
1384         IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
1385                 init_val_drc_preview_still.dma_input.plane);
1386         IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
1387                 init_val_drc_preview_still.dma_input.order);
1388         IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
1389                 init_val_drc_preview_still.dma_input.buffer_number);
1390         IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
1391                 init_val_drc_preview_still.dma_input.buffer_address);
1392         IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
1393                 init_val_drc_preview_still.dma_input.err);
1394         IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
1395         IS_INC_PARAM_NUM(dev);
1396
1397         IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
1398                 init_val_drc_preview_still.otf_output.cmd);
1399         IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1400                 init_val_drc_preview_still.otf_output.width);
1401         IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1402                 init_val_drc_preview_still.otf_output.height);
1403         IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1404                 init_val_drc_preview_still.otf_output.format);
1405         IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1406                 init_val_drc_preview_still.otf_output.bitwidth);
1407         IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1408                 init_val_drc_preview_still.otf_output.order);
1409         IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
1410                 init_val_drc_preview_still.otf_output.err);
1411         length = init_val_drc_preview_still.otf_output.width*
1412                         init_val_drc_preview_still.otf_output.height;
1413         IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
1414         IS_INC_PARAM_NUM(dev);
1415
1416         /* SCALER-C Macros */
1417         IS_SCALERC_SET_PARAM_CONTROL_CMD(dev,
1418                 init_val_scalerc_preview_still.control.cmd);
1419         IS_SCALERC_SET_PARAM_CONTROL_BYPASS(dev,
1420                 init_val_scalerc_preview_still.control.bypass);
1421         IS_SCALERC_SET_PARAM_CONTROL_ERR(dev,
1422                 init_val_scalerc_preview_still.control.err);
1423         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_CONTROL);
1424         IS_INC_PARAM_NUM(dev);
1425
1426         IS_SCALERC_SET_PARAM_OTF_INPUT_CMD(dev,
1427                 init_val_scalerc_preview_still.otf_input.cmd);
1428         IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev,
1429                 init_val_scalerc_preview_still.otf_input.width);
1430         IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1431                 init_val_scalerc_preview_still.otf_input.height);
1432         IS_SCALERC_SET_PARAM_OTF_INPUT_FORMAT(dev,
1433                 init_val_scalerc_preview_still.otf_input.format);
1434         IS_SCALERC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1435                 init_val_scalerc_preview_still.otf_input.bitwidth);
1436         IS_SCALERC_SET_PARAM_OTF_INPUT_ORDER(dev,
1437                 init_val_scalerc_preview_still.otf_input.order);
1438         IS_SCALERC_SET_PARAM_OTF_INPUT_ERR(dev,
1439                 init_val_scalerc_preview_still.otf_input.err);
1440         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_INPUT);
1441         IS_INC_PARAM_NUM(dev);
1442
1443         IS_SCALERC_SET_PARAM_EFFECT_CMD(dev,
1444                 init_val_scalerc_preview_still.effect.cmd);
1445         IS_SCALERC_SET_PARAM_EFFECT_ERR(dev,
1446                 init_val_scalerc_preview_still.effect.err);
1447         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_IMAGE_EFFECT);
1448         IS_INC_PARAM_NUM(dev);
1449
1450         IS_SCALERC_SET_PARAM_INPUT_CROP_CMD(dev,
1451                 init_val_scalerc_preview_still.input_crop.cmd);
1452         IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev,
1453                 init_val_scalerc_preview_still.input_crop.pos_x);
1454         IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev,
1455                 init_val_scalerc_preview_still.input_crop.pos_y);
1456         IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev,
1457                 init_val_scalerc_preview_still.input_crop.crop_width);
1458         IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev,
1459                 init_val_scalerc_preview_still.input_crop.crop_height);
1460         IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
1461                 init_val_scalerc_preview_still.input_crop.in_width);
1462         IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
1463                 init_val_scalerc_preview_still.input_crop.in_height);
1464         IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
1465                 init_val_scalerc_preview_still.input_crop.out_width);
1466         IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
1467                 init_val_scalerc_preview_still.input_crop.out_height);
1468         IS_SCALERC_SET_PARAM_INPUT_CROP_ERR(dev,
1469                 init_val_scalerc_preview_still.input_crop.err);
1470         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_INPUT_CROP);
1471         IS_INC_PARAM_NUM(dev);
1472
1473         IS_SCALERC_SET_PARAM_OUTPUT_CROP_CMD(dev,
1474                 init_val_scalerc_preview_still.output_crop.cmd);
1475         IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_X(dev,
1476                 init_val_scalerc_preview_still.output_crop.pos_x);
1477         IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_Y(dev,
1478                 init_val_scalerc_preview_still.output_crop.pos_y);
1479         IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
1480                 init_val_scalerc_preview_still.output_crop.crop_width);
1481         IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
1482                 init_val_scalerc_preview_still.output_crop.crop_height);
1483         IS_SCALERC_SET_PARAM_OUTPUT_CROPG_FORMAT(dev,
1484                 init_val_scalerc_preview_still.output_crop.format);
1485         IS_SCALERC_SET_PARAM_OUTPUT_CROP_ERR(dev,
1486                 init_val_scalerc_preview_still.output_crop.err);
1487         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OUTPUT_CROP);
1488         IS_INC_PARAM_NUM(dev);
1489
1490         IS_SCALERC_SET_PARAM_OTF_OUTPUT_CMD(dev,
1491                 init_val_scalerc_preview_still.otf_output.cmd);
1492         IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1493                 init_val_scalerc_preview_still.otf_output.width);
1494         IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1495                 init_val_scalerc_preview_still.otf_output.height);
1496         IS_SCALERC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1497                 init_val_scalerc_preview_still.otf_output.format);
1498         IS_SCALERC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1499                 init_val_scalerc_preview_still.otf_output.bitwidth);
1500         IS_SCALERC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1501                 init_val_scalerc_preview_still.otf_output.order);
1502         IS_SCALERC_SET_PARAM_OTF_OUTPUT_ERR(dev,
1503                 init_val_scalerc_preview_still.otf_output.err);
1504         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_OUTPUT);
1505         IS_INC_PARAM_NUM(dev);
1506
1507         IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(dev,
1508                 init_val_scalerc_preview_still.dma_output.cmd);
1509         IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
1510                 init_val_scalerc_preview_still.dma_output.width);
1511         IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
1512                 init_val_scalerc_preview_still.dma_output.height);
1513         IS_SCALERC_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
1514                 init_val_scalerc_preview_still.dma_output.format);
1515         IS_SCALERC_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
1516                 init_val_scalerc_preview_still.dma_output.bitwidth);
1517         IS_SCALERC_SET_PARAM_DMA_OUTPUT_PLANE(dev,
1518                 init_val_scalerc_preview_still.dma_output.plane);
1519         IS_SCALERC_SET_PARAM_DMA_OUTPUT_ORDER(dev,
1520                 init_val_scalerc_preview_still.dma_output.order);
1521         IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
1522                 init_val_scalerc_preview_still.dma_output.buffer_number);
1523         IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
1524                 init_val_scalerc_preview_still.dma_output.buffer_address);
1525         IS_SCALERC_SET_PARAM_DMA_OUTPUT_MASK(dev,
1526                 (0xff&0xffffffff));
1527         IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
1528                 init_val_scalerc_preview_still.dma_output.reserved[0]);
1529         IS_SCALERC_SET_PARAM_DMA_OUTPUT_ERR(dev,
1530                 init_val_scalerc_preview_still.dma_output.err);
1531         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_DMA_OUTPUT);
1532         IS_INC_PARAM_NUM(dev);
1533
1534         /* ODC Macros */
1535         IS_ODC_SET_PARAM_CONTROL_CMD(dev,
1536                 init_val_odc_preview_still.control.cmd);
1537         IS_ODC_SET_PARAM_CONTROL_BYPASS(dev,
1538                 init_val_odc_preview_still.control.bypass);
1539         IS_ODC_SET_PARAM_CONTROL_ERR(dev,
1540                 init_val_odc_preview_still.control.err);
1541         IS_SET_PARAM_BIT(dev, PARAM_ODC_CONTROL);
1542         IS_INC_PARAM_NUM(dev);
1543
1544         IS_ODC_SET_PARAM_OTF_INPUT_CMD(dev,
1545                 init_val_odc_preview_still.otf_input.cmd);
1546         IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev,
1547                 init_val_odc_preview_still.otf_input.width);
1548         IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1549                 init_val_odc_preview_still.otf_input.height);
1550         IS_ODC_SET_PARAM_OTF_INPUT_FORMAT(dev,
1551                 init_val_odc_preview_still.otf_input.format);
1552         IS_ODC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1553                 init_val_odc_preview_still.otf_input.bitwidth);
1554         IS_ODC_SET_PARAM_OTF_INPUT_ORDER(dev,
1555                 init_val_odc_preview_still.otf_input.order);
1556         IS_ODC_SET_PARAM_OTF_INPUT_ERR(dev,
1557                 init_val_odc_preview_still.otf_input.err);
1558         IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_INPUT);
1559         IS_INC_PARAM_NUM(dev);
1560
1561         IS_ODC_SET_PARAM_OTF_OUTPUT_CMD(dev,
1562                 init_val_odc_preview_still.otf_output.cmd);
1563         IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1564                 init_val_odc_preview_still.otf_output.width);
1565         IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1566                 init_val_odc_preview_still.otf_output.height);
1567         IS_ODC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1568                 init_val_odc_preview_still.otf_output.format);
1569         IS_ODC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1570                 init_val_odc_preview_still.otf_output.bitwidth);
1571         IS_ODC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1572                 init_val_odc_preview_still.otf_output.order);
1573         IS_ODC_SET_PARAM_OTF_OUTPUT_ERR(dev,
1574                 init_val_odc_preview_still.otf_output.err);
1575         IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_OUTPUT);
1576         IS_INC_PARAM_NUM(dev);
1577
1578         /* DIS Macros */
1579         IS_DIS_SET_PARAM_CONTROL_CMD(dev,
1580                 init_val_dis_preview_still.control.cmd);
1581         IS_DIS_SET_PARAM_CONTROL_BYPASS(dev,
1582                 init_val_dis_preview_still.control.bypass);
1583         IS_DIS_SET_PARAM_CONTROL_ERR(dev,
1584                 init_val_dis_preview_still.control.err);
1585         IS_SET_PARAM_BIT(dev, PARAM_DIS_CONTROL);
1586         IS_INC_PARAM_NUM(dev);
1587
1588         IS_DIS_SET_PARAM_OTF_INPUT_CMD(dev,
1589                 init_val_dis_preview_still.otf_input.cmd);
1590         IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev,
1591                 init_val_dis_preview_still.otf_input.width);
1592         IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1593                 init_val_dis_preview_still.otf_input.height);
1594         IS_DIS_SET_PARAM_OTF_INPUT_FORMAT(dev,
1595                 init_val_dis_preview_still.otf_input.format);
1596         IS_DIS_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1597                 init_val_dis_preview_still.otf_input.bitwidth);
1598         IS_DIS_SET_PARAM_OTF_INPUT_ORDER(dev,
1599                 init_val_dis_preview_still.otf_input.order);
1600         IS_DIS_SET_PARAM_OTF_INPUT_ERR(dev,
1601                 init_val_dis_preview_still.otf_input.err);
1602         IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_INPUT);
1603         IS_INC_PARAM_NUM(dev);
1604
1605         IS_DIS_SET_PARAM_OTF_OUTPUT_CMD(dev,
1606                 init_val_dis_preview_still.otf_output.cmd);
1607         IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1608                 init_val_dis_preview_still.otf_output.width);
1609         IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1610                 init_val_dis_preview_still.otf_output.height);
1611         IS_DIS_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1612                 init_val_dis_preview_still.otf_output.format);
1613         IS_DIS_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1614                 init_val_dis_preview_still.otf_output.bitwidth);
1615         IS_DIS_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1616                 init_val_dis_preview_still.otf_output.order);
1617         IS_DIS_SET_PARAM_OTF_OUTPUT_ERR(dev,
1618                 init_val_dis_preview_still.otf_output.err);
1619         IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_OUTPUT);
1620         IS_INC_PARAM_NUM(dev);
1621
1622         /* TDNR Macros */
1623         IS_TDNR_SET_PARAM_CONTROL_CMD(dev,
1624                 init_val_tdnr_preview_still.control.cmd);
1625         IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev,
1626                 init_val_tdnr_preview_still.control.bypass);
1627         IS_TDNR_SET_PARAM_CONTROL_ERR(dev,
1628                 init_val_tdnr_preview_still.control.err);
1629         IS_SET_PARAM_BIT(dev, PARAM_TDNR_CONTROL);
1630         IS_INC_PARAM_NUM(dev);
1631
1632         IS_TDNR_SET_PARAM_OTF_INPUT_CMD(dev,
1633                 init_val_tdnr_preview_still.otf_input.cmd);
1634         IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev,
1635                 init_val_tdnr_preview_still.otf_input.width);
1636         IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1637                 init_val_tdnr_preview_still.otf_input.height);
1638         IS_TDNR_SET_PARAM_OTF_INPUT_FORMAT(dev,
1639                 init_val_tdnr_preview_still.otf_input.format);
1640         IS_TDNR_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1641                 init_val_tdnr_preview_still.otf_input.bitwidth);
1642         IS_TDNR_SET_PARAM_OTF_INPUT_ORDER(dev,
1643                 init_val_tdnr_preview_still.otf_input.order);
1644         IS_TDNR_SET_PARAM_OTF_INPUT_ERR(dev,
1645                 init_val_tdnr_preview_still.otf_input.err);
1646         IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_INPUT);
1647         IS_INC_PARAM_NUM(dev);
1648
1649         IS_TDNR_SET_PARAM_FRAME_CMD(dev,
1650                 init_val_tdnr_preview_still.frame.cmd);
1651         IS_TDNR_SET_PARAM_FRAME_ERR(dev,
1652                 init_val_tdnr_preview_still.frame.err);
1653         IS_SET_PARAM_BIT(dev, PARAM_TDNR_1ST_FRAME);
1654         IS_INC_PARAM_NUM(dev);
1655
1656         IS_TDNR_SET_PARAM_OTF_OUTPUT_CMD(dev,
1657                 init_val_tdnr_preview_still.otf_output.cmd);
1658         IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1659                 init_val_tdnr_preview_still.otf_output.width);
1660         IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1661                 init_val_tdnr_preview_still.otf_output.height);
1662         IS_TDNR_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1663                 init_val_tdnr_preview_still.otf_output.format);
1664         IS_TDNR_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1665                 init_val_tdnr_preview_still.otf_output.bitwidth);
1666         IS_TDNR_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1667                 init_val_tdnr_preview_still.otf_output.order);
1668         IS_TDNR_SET_PARAM_OTF_OUTPUT_ERR(dev,
1669                 init_val_tdnr_preview_still.otf_output.err);
1670         IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_OUTPUT);
1671         IS_INC_PARAM_NUM(dev);
1672
1673         IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(dev,
1674                 init_val_tdnr_preview_still.dma_output.cmd);
1675         IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
1676                 init_val_tdnr_preview_still.dma_output.width);
1677         IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
1678                 init_val_tdnr_preview_still.dma_output.height);
1679         IS_TDNR_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
1680                 init_val_tdnr_preview_still.dma_output.format);
1681         IS_TDNR_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
1682                 init_val_tdnr_preview_still.dma_output.bitwidth);
1683         IS_TDNR_SET_PARAM_DMA_OUTPUT_PLANE(dev,
1684                 init_val_tdnr_preview_still.dma_output.plane);
1685         IS_TDNR_SET_PARAM_DMA_OUTPUT_ORDER(dev,
1686                 init_val_tdnr_preview_still.dma_output.order);
1687         IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
1688                 init_val_tdnr_preview_still.dma_output.buffer_number);
1689         IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
1690                 init_val_tdnr_preview_still.dma_output.buffer_address);
1691         IS_TDNR_SET_PARAM_DMA_OUTPUT_MASK(dev,
1692                 (0xff&0xffffffff));
1693         IS_TDNR_SET_PARAM_DMA_OUTPUT_ERR(dev,
1694                 init_val_tdnr_preview_still.dma_output.err);
1695         IS_SET_PARAM_BIT(dev, PARAM_TDNR_DMA_OUTPUT);
1696         IS_INC_PARAM_NUM(dev);
1697
1698         /* SCALER-P Macros */
1699         IS_SCALERP_SET_PARAM_CONTROL_CMD(dev,
1700                 init_val_scalerp_preview_still.control.cmd);
1701         IS_SCALERP_SET_PARAM_CONTROL_BYPASS(dev,
1702                 init_val_scalerp_preview_still.control.bypass);
1703         IS_SCALERP_SET_PARAM_CONTROL_ERR(dev,
1704                 init_val_scalerp_preview_still.control.err);
1705         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_CONTROL);
1706         IS_INC_PARAM_NUM(dev);
1707
1708         IS_SCALERP_SET_PARAM_OTF_INPUT_CMD(dev,
1709                 init_val_scalerp_preview_still.otf_input.cmd);
1710         IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev,
1711                 init_val_scalerp_preview_still.otf_input.width);
1712         IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1713                 init_val_scalerp_preview_still.otf_input.height);
1714         IS_SCALERP_SET_PARAM_OTF_INPUT_FORMAT(dev,
1715                 init_val_scalerp_preview_still.otf_input.format);
1716         IS_SCALERP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1717                 init_val_scalerp_preview_still.otf_input.bitwidth);
1718         IS_SCALERP_SET_PARAM_OTF_INPUT_ORDER(dev,
1719                 init_val_scalerp_preview_still.otf_input.order);
1720         IS_SCALERP_SET_PARAM_OTF_INPUT_ERR(dev,
1721                 init_val_scalerp_preview_still.otf_input.err);
1722         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_INPUT);
1723         IS_INC_PARAM_NUM(dev);
1724
1725         IS_SCALERP_SET_PARAM_EFFECT_CMD(dev,
1726                 init_val_scalerp_preview_still.effect.cmd);
1727         IS_SCALERP_SET_PARAM_EFFECT_ERR(dev,
1728                 init_val_scalerp_preview_still.effect.err);
1729         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_IMAGE_EFFECT);
1730         IS_INC_PARAM_NUM(dev);
1731
1732         IS_SCALERP_SET_PARAM_INPUT_CROP_CMD(dev,
1733                 init_val_scalerp_preview_still.input_crop.cmd);
1734         IS_SCALERP_SET_PARAM_INPUT_CROP_POS_X(dev,
1735                 init_val_scalerp_preview_still.input_crop.pos_x);
1736         IS_SCALERP_SET_PARAM_INPUT_CROP_POS_Y(dev,
1737                 init_val_scalerp_preview_still.input_crop.pos_y);
1738         IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev,
1739                 init_val_scalerp_preview_still.input_crop.crop_width);
1740         IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev,
1741                 init_val_scalerp_preview_still.input_crop.crop_height);
1742         IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
1743                 init_val_scalerp_preview_still.input_crop.in_width);
1744         IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
1745                 init_val_scalerp_preview_still.input_crop.in_height);
1746         IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
1747                 init_val_scalerp_preview_still.input_crop.out_width);
1748         IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
1749                 init_val_scalerp_preview_still.input_crop.out_height);
1750         IS_SCALERP_SET_PARAM_INPUT_CROP_ERR(dev,
1751                 init_val_scalerp_preview_still.input_crop.err);
1752         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_INPUT_CROP);
1753         IS_INC_PARAM_NUM(dev);
1754
1755         IS_SCALERP_SET_PARAM_OUTPUT_CROP_CMD(dev,
1756                 init_val_scalerp_preview_still.output_crop.cmd);
1757         IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_X(dev,
1758                 init_val_scalerp_preview_still.output_crop.pos_x);
1759         IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_Y(dev,
1760                 init_val_scalerp_preview_still.output_crop.pos_y);
1761         IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
1762                 init_val_scalerp_preview_still.output_crop.crop_width);
1763         IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
1764                 init_val_scalerp_preview_still.output_crop.crop_height);
1765         IS_SCALERP_SET_PARAM_OUTPUT_CROPG_FORMAT(dev,
1766                 init_val_scalerp_preview_still.output_crop.format);
1767         IS_SCALERP_SET_PARAM_OUTPUT_CROP_ERR(dev,
1768                 init_val_scalerp_preview_still.output_crop.err);
1769         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OUTPUT_CROP);
1770         IS_INC_PARAM_NUM(dev);
1771
1772         IS_SCALERP_SET_PARAM_ROTATION_CMD(dev,
1773                 init_val_scalerp_preview_still.rotation.cmd);
1774         IS_SCALERP_SET_PARAM_ROTATION_ERR(dev,
1775                 init_val_scalerp_preview_still.rotation.err);
1776         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_ROTATION);
1777         IS_INC_PARAM_NUM(dev);
1778
1779         IS_SCALERP_SET_PARAM_FLIP_CMD(dev,
1780                 init_val_scalerp_preview_still.flip.cmd);
1781         IS_SCALERP_SET_PARAM_FLIP_ERR(dev,
1782                 init_val_scalerp_preview_still.flip.err);
1783         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_FLIP);
1784         IS_INC_PARAM_NUM(dev);
1785
1786         IS_SCALERP_SET_PARAM_OTF_OUTPUT_CMD(dev,
1787                 init_val_scalerp_preview_still.otf_output.cmd);
1788         IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1789                 init_val_scalerp_preview_still.otf_output.width);
1790         IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1791                 init_val_scalerp_preview_still.otf_output.height);
1792         IS_SCALERP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
1793                 init_val_scalerp_preview_still.otf_output.format);
1794         IS_SCALERP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
1795                 init_val_scalerp_preview_still.otf_output.bitwidth);
1796         IS_SCALERP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
1797                 init_val_scalerp_preview_still.otf_output.order);
1798         IS_SCALERP_SET_PARAM_OTF_OUTPUT_ERR(dev,
1799                 init_val_scalerp_preview_still.otf_output.err);
1800         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_OUTPUT);
1801         IS_INC_PARAM_NUM(dev);
1802
1803         IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(dev,
1804                 init_val_scalerp_preview_still.dma_output.cmd);
1805         IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
1806                 init_val_scalerp_preview_still.dma_output.width);
1807         IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
1808                 init_val_scalerp_preview_still.dma_output.height);
1809         IS_SCALERP_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
1810                 init_val_scalerp_preview_still.dma_output.format);
1811         IS_SCALERP_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
1812                 init_val_scalerp_preview_still.dma_output.bitwidth);
1813         IS_SCALERP_SET_PARAM_DMA_OUTPUT_PLANE(dev,
1814                 init_val_scalerp_preview_still.dma_output.plane);
1815         IS_SCALERP_SET_PARAM_DMA_OUTPUT_ORDER(dev,
1816                 init_val_scalerp_preview_still.dma_output.order);
1817         IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
1818                 init_val_scalerp_preview_still.dma_output.buffer_number);
1819         IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
1820                 init_val_scalerp_preview_still.dma_output.buffer_address);
1821         IS_SCALERP_SET_PARAM_DMA_OUTPUT_MASK(dev,
1822                 (0xff&0xffffffff));
1823         IS_SCALERP_SET_PARAM_DMA_OUTPUT_ERR(dev,
1824                 init_val_scalerp_preview_still.dma_output.err);
1825         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_DMA_OUTPUT);
1826         IS_INC_PARAM_NUM(dev);
1827
1828         /* FD */
1829         IS_FD_SET_PARAM_CONTROL_CMD(dev,
1830                 init_val_fd_preview_still.control.cmd);
1831         IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
1832                 init_val_fd_preview_still.control.bypass);
1833         IS_FD_SET_PARAM_CONTROL_ERR(dev,
1834                 init_val_fd_preview_still.control.err);
1835         IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
1836         IS_INC_PARAM_NUM(dev);
1837         IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
1838                 init_val_fd_preview_still.otf_input.cmd);
1839         IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
1840                 init_val_fd_preview_still.otf_input.width);
1841         IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1842                 init_val_fd_preview_still.otf_input.height);
1843         IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
1844                 init_val_fd_preview_still.otf_input.format);
1845         IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
1846                 init_val_fd_preview_still.otf_input.bitwidth);
1847         IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
1848                 init_val_fd_preview_still.otf_input.order);
1849         IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
1850                 init_val_fd_preview_still.otf_input.err);
1851         IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
1852         IS_INC_PARAM_NUM(dev);
1853         IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
1854                 init_val_fd_preview_still.dma_input.cmd);
1855         IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
1856                 init_val_fd_preview_still.dma_input.width);
1857         IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
1858                 init_val_fd_preview_still.dma_input.height);
1859         IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
1860                 init_val_fd_preview_still.dma_input.format);
1861         IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
1862                 init_val_fd_preview_still.dma_input.bitwidth);
1863         IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
1864                 init_val_fd_preview_still.dma_input.plane);
1865         IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
1866                 init_val_fd_preview_still.dma_input.order);
1867         IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
1868                 init_val_fd_preview_still.dma_input.buffer_number);
1869         IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
1870                 init_val_fd_preview_still.dma_input.buffer_address);
1871         IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
1872                 init_val_fd_preview_still.dma_input.err);
1873         IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
1874         IS_INC_PARAM_NUM(dev);
1875         IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
1876                 init_val_fd_preview_still.config.cmd);
1877         IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
1878                 init_val_fd_preview_still.config.max_number);
1879         IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
1880                 init_val_fd_preview_still.config.roll_angle);
1881         IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
1882                 init_val_fd_preview_still.config.yaw_angle);
1883         IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
1884                 init_val_fd_preview_still.config.smile_mode);
1885         IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
1886                 init_val_fd_preview_still.config.blink_mode);
1887         IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
1888                 init_val_fd_preview_still.config.eye_detect);
1889         IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
1890                 init_val_fd_preview_still.config.mouth_detect);
1891         IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
1892                 init_val_fd_preview_still.config.orientation);
1893         IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
1894                 init_val_fd_preview_still.config.orientation_value);
1895         IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
1896                 init_val_fd_preview_still.config.err);
1897         IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
1898         IS_INC_PARAM_NUM(dev);
1899 }
1900
1901 int fimc_is_hw_change_size(struct fimc_is_dev *dev)
1902 {
1903         u32 front_width, front_height, back_width, back_height;
1904         u32 dis_width, dis_height;
1905         u32 crop_width = 0, crop_height = 0, crop_x = 0, crop_y = 0;
1906         u32 front_crop_ratio, back_crop_ratio;
1907
1908         /* ISP */
1909         IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
1910                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1911         IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1912                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1913         IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
1914         IS_INC_PARAM_NUM(dev);
1915
1916         IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
1917                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1918         IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
1919                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1920         IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
1921         IS_INC_PARAM_NUM(dev);
1922
1923         IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1924                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1925         IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1926                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1927         IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
1928         IS_INC_PARAM_NUM(dev);
1929
1930         IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
1931                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1932         IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
1933                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1934         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
1935         IS_INC_PARAM_NUM(dev);
1936
1937         IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
1938                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1939         IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
1940                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1941         IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
1942         IS_INC_PARAM_NUM(dev);
1943
1944         /* DRC */
1945         IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
1946                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1947         IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1948                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1949         IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
1950         IS_INC_PARAM_NUM(dev);
1951
1952         IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
1953                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1954         IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
1955                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1956         IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
1957         IS_INC_PARAM_NUM(dev);
1958
1959         IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
1960                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
1961         IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
1962                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
1963         IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
1964         IS_INC_PARAM_NUM(dev);
1965
1966         /* ScalerC */
1967         front_width = dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width;
1968         front_height = dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height;
1969
1970         back_width = dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width;
1971         back_height = dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height;
1972
1973         IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev,
1974                 front_width);
1975         IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
1976                 front_height);
1977         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_INPUT);
1978         IS_INC_PARAM_NUM(dev);
1979
1980         IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
1981                 front_width);
1982         IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
1983                 front_height);
1984
1985         front_crop_ratio = front_width * 1000 / front_height;
1986         back_crop_ratio = back_width * 1000 / back_height;
1987
1988         if (front_crop_ratio == back_crop_ratio) {
1989                 crop_width = front_width;
1990                 crop_height = front_height;
1991
1992         } else if (front_crop_ratio < back_crop_ratio) {
1993                 crop_width = front_width;
1994                 crop_height = (front_width
1995                                 * (1000 * 100 / back_crop_ratio)) / 100;
1996                 crop_width = ALIGN(crop_width, 8);
1997                 crop_height = ALIGN(crop_height, 8);
1998
1999         } else if (front_crop_ratio > back_crop_ratio) {
2000                 crop_height = front_height;
2001                 crop_width = (front_height
2002                                 * (back_crop_ratio * 100 / 1000)) / 100 ;
2003                 crop_width = ALIGN(crop_width, 8);
2004                 crop_height = ALIGN(crop_height, 8);
2005         }
2006
2007         if (dev->back.dis_on) {
2008                 dis_width = back_width * 125 / 100;
2009                 dis_height = back_height * 125 / 100;
2010         } else {
2011                 dis_width = back_width;
2012                 dis_height = back_height;
2013         }
2014
2015         IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
2016                 crop_width);
2017         IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
2018                 crop_height);
2019
2020         dbg("calulate crop size\n");
2021         dbg("front w: %d front h: %d\n", front_width, front_height);
2022         dbg("dis w: %d dis h: %d\n", dis_width, dis_height);
2023         dbg("back w: %d back h: %d\n", back_width, back_height);
2024
2025         dbg("front_crop_ratio: %d back_crop_ratio: %d\n",
2026                         front_crop_ratio, back_crop_ratio);
2027
2028         crop_x = (front_width - crop_width) / 2;
2029         crop_y = (front_height - crop_height) / 2;
2030         crop_x &= 0xffe;
2031         crop_y &= 0xffe;
2032
2033         dev->sensor.width = front_width;
2034         dev->sensor.height = front_height;
2035         dev->front.width = front_width;
2036         dev->front.height = front_height;
2037         dev->back.width = back_width;
2038         dev->back.height = back_height;
2039         dev->back.dis_width = dis_width;
2040         dev->back.dis_height = dis_height;
2041
2042         dbg("crop w: %d crop h: %d\n", crop_width, crop_height);
2043         dbg("crop x: %d crop y: %d\n", crop_x, crop_y);
2044
2045         IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev,
2046                 crop_width);
2047         IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev,
2048                 crop_height);
2049         IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev,
2050                 crop_x);
2051         IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev,
2052                 crop_y);
2053
2054         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_INPUT_CROP);
2055         IS_INC_PARAM_NUM(dev);
2056
2057         IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
2058                 dis_width);
2059         IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
2060                 dis_height);
2061         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OUTPUT_CROP);
2062         IS_INC_PARAM_NUM(dev);
2063
2064         IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
2065                 dis_width);
2066         IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
2067                 dis_height);
2068         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_OUTPUT);
2069         IS_INC_PARAM_NUM(dev);
2070
2071         IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
2072                 front_width);
2073         IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
2074                 front_height);
2075         if((front_width != dis_width) || (front_height != dis_height))
2076                 IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
2077                         2);  /* unscaled image */
2078         else
2079                 IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
2080                         1); /* scaled image */
2081         IS_SET_PARAM_BIT(dev, PARAM_SCALERC_DMA_OUTPUT);
2082         IS_INC_PARAM_NUM(dev);
2083
2084         /* ODC */
2085         IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev,
2086                 dis_width);
2087         IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
2088                 dis_height);
2089         IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_INPUT);
2090         IS_INC_PARAM_NUM(dev);
2091
2092         IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
2093                 dis_width);
2094         IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
2095                 dis_height);
2096         IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_OUTPUT);
2097         IS_INC_PARAM_NUM(dev);
2098
2099         /* DIS */
2100         IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev,
2101                 dis_width);
2102         IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev,
2103                 dis_height);
2104         IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_INPUT);
2105         IS_INC_PARAM_NUM(dev);
2106
2107         IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
2108                 back_width);
2109         IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
2110                 back_height);
2111         IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_OUTPUT);
2112         IS_INC_PARAM_NUM(dev);
2113
2114         /* 3DNR */
2115         IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev,
2116                 back_width);
2117         IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev,
2118                 back_height);
2119         IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_INPUT);
2120         IS_INC_PARAM_NUM(dev);
2121
2122         IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
2123                 back_width);
2124         IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
2125                 back_height);
2126         IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_OUTPUT);
2127         IS_INC_PARAM_NUM(dev);
2128
2129         IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
2130                 back_width);
2131         IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
2132                 back_height);
2133         IS_SET_PARAM_BIT(dev, PARAM_TDNR_DMA_OUTPUT);
2134         IS_INC_PARAM_NUM(dev);
2135
2136         /* ScalerP */
2137         IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev,
2138                 back_width);
2139         IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
2140                 back_height);
2141         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_INPUT);
2142         IS_INC_PARAM_NUM(dev);
2143
2144         IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
2145                 back_width);
2146         IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
2147                 back_height);
2148         IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev,
2149                 back_width);
2150         IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev,
2151                 back_height);
2152         IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
2153                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
2154         IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
2155                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
2156         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_INPUT_CROP);
2157         IS_INC_PARAM_NUM(dev);
2158
2159         IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
2160                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
2161         IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
2162                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
2163         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OUTPUT_CROP);
2164         IS_INC_PARAM_NUM(dev);
2165
2166         IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
2167                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
2168         IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
2169                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
2170         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_OUTPUT);
2171         IS_INC_PARAM_NUM(dev);
2172
2173         IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
2174                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
2175         IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
2176                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
2177         IS_SET_PARAM_BIT(dev, PARAM_SCALERP_DMA_OUTPUT);
2178         IS_INC_PARAM_NUM(dev);
2179
2180         /* FD */
2181         IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
2182                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
2183         IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
2184                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
2185         IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
2186         IS_INC_PARAM_NUM(dev);
2187
2188         return 0;
2189 }
2190
2191 void fimc_is_hw_set_default_size(struct fimc_is_dev *dev, int  sensor_id)
2192 {
2193         switch (sensor_id) {
2194         case SENSOR_NAME_S5K6A3:
2195                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
2196                         DEFAULT_6A3_STILLSHOT_WIDTH;
2197                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
2198                         DEFAULT_6A3_STILLSHOT_HEIGHT;
2199                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
2200                         DEFAULT_6A3_PREVIEW_WIDTH;
2201                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
2202                         DEFAULT_6A3_PREVIEW_HEIGHT;
2203                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
2204                         DEFAULT_6A3_VIDEO_WIDTH;
2205                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
2206                         DEFAULT_6A3_VIDEO_HEIGHT;
2207                 break;
2208         case SENSOR_NAME_S5K4E5:
2209                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
2210                         DEFAULT_4E5_STILLSHOT_WIDTH;
2211                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
2212                         DEFAULT_4E5_STILLSHOT_HEIGHT;
2213                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
2214                         DEFAULT_4E5_PREVIEW_WIDTH;
2215                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
2216                         DEFAULT_4E5_PREVIEW_HEIGHT;
2217                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
2218                         DEFAULT_4E5_VIDEO_WIDTH;
2219                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
2220                         DEFAULT_4E5_VIDEO_HEIGHT;
2221                 break;
2222         default:
2223                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
2224                         DEFAULT_CAPTURE_STILL_WIDTH;
2225                 dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
2226                         DEFAULT_CAPTURE_STILL_HEIGHT;
2227                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
2228                         DEFAULT_PREVIEW_STILL_WIDTH;
2229                 dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
2230                         DEFAULT_PREVIEW_STILL_HEIGHT;
2231                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
2232                         DEFAULT_CAPTURE_VIDEO_WIDTH;
2233                 dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
2234                         DEFAULT_CAPTURE_VIDEO_HEIGHT;
2235                 break;
2236         }
2237 }