drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/init.h>
  28 #include <linux/time.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/errno.h>
  32 #include <linux/err.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/clk.h>
  35 #include <linux/cpufreq.h>
  36 #include <linux/slab.h>
  37 #include <linux/io.h>
  38
  39 #include <asm/irq.h>
  40
  41 #include <plat/regs-iic.h>
  42 #include <plat/iic.h>
  43
  44 /* i2c controller state */
  45
  46 enum s3c24xx_i2c_state {
  47         STATE_IDLE,
  48         STATE_START,
  49         STATE_READ,
  50         STATE_WRITE,
  51         STATE_STOP
  52 };
  53
  54 enum s3c24xx_i2c_type {
  55         TYPE_S3C2410,
  56         TYPE_S3C2440,
  57         TYPE_S3C2440_HDMIPHY,
  58 };
  59
  60 struct s3c24xx_i2c {
  61         spinlock_t              lock;
  62         wait_queue_head_t       wait;
  63         unsigned int            suspended:1;
  64
  65         struct i2c_msg          *msg;
  66         unsigned int            msg_num;
  67         unsigned int            msg_idx;
  68         unsigned int            msg_ptr;
  69
  70         unsigned int            tx_setup;
  71         unsigned int            irq;
  72
  73         enum s3c24xx_i2c_state  state;
  74         unsigned long           clkrate;
  75
  76         void __iomem            *regs;
  77         struct clk              *clk;
  78         struct device           *dev;
  79         struct resource         *ioarea;
  80         struct i2c_adapter      adap;
  81
  82 #ifdef CONFIG_CPU_FREQ
  83         struct notifier_block   freq_transition;
  84 #endif
  85 };
  86
  87 /* default platform data removed, dev should always carry data. */
  88
  89 static inline void dump_i2c_register(struct s3c24xx_i2c *i2c)
  90 {
  91         dev_dbg(i2c->dev, "Register dump(%d) : %x %x %x %x %x\n"
  92                 , i2c->suspended
  93                 , readl(i2c->regs + S3C2410_IICCON)
  94                 , readl(i2c->regs + S3C2410_IICSTAT)
  95                 , readl(i2c->regs + S3C2410_IICADD)
  96                 , readl(i2c->regs + S3C2410_IICDS)
  97                 , readl(i2c->regs + S3C2440_IICLC) );
  98 }
  99
 100 /* s3c24xx_i2c_is2440()
 101  *
 102  * return true is this is an s3c2440
 103 */
 104
 105 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
 106 {
 107         struct platform_device *pdev = to_platform_device(i2c->dev);
 108         enum s3c24xx_i2c_type type;
 109
 110         type = platform_get_device_id(pdev)->driver_data;
 111         return type == TYPE_S3C2440 || type == TYPE_S3C2440_HDMIPHY;
 112 }
 113
 114 /* s3c24xx_i2c_is2440_hdmiphy()
 115  *
 116  * return true is this is an s3c2440 dedicated for HDMIPHY interface
 117 */
 118 static inline int s3c24xx_i2c_is2440_hdmiphy(struct s3c24xx_i2c *i2c)
 119 {
 120         struct platform_device *pdev = to_platform_device(i2c->dev);
 121         enum s3c24xx_i2c_type type;
 122
 123         type = platform_get_device_id(pdev)->driver_data;
 124         return type == TYPE_S3C2440_HDMIPHY;
 125 }
 126
 127 /* s3c24xx_i2c_master_complete
 128  *
 129  * complete the message and wake up the caller, using the given return code,
 130  * or zero to mean ok.
 131 */
 132
 133 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 134 {
 135         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 136
 137         i2c->msg_ptr = 0;
 138         i2c->msg = NULL;
 139         i2c->msg_idx++;
 140         i2c->msg_num = 0;
 141         if (ret)
 142                 i2c->msg_idx = ret;
 143
 144         wake_up(&i2c->wait);
 145 }
 146
 147 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 148 {
 149         unsigned long tmp;
 150
 151         tmp = readl(i2c->regs + S3C2410_IICCON);
 152         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 153 }
 154
 155 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 156 {
 157         unsigned long tmp;
 158
 159         tmp = readl(i2c->regs + S3C2410_IICCON);
 160         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 161 }
 162
 163 /* irq enable/disable functions */
 164
 165 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 166 {
 167         unsigned long tmp;
 168
 169         tmp = readl(i2c->regs + S3C2410_IICCON);
 170         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 171 }
 172
 173 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 174 {
 175         unsigned long tmp;
 176
 177         tmp = readl(i2c->regs + S3C2410_IICCON);
 178         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 179 }
 180
 181
 182 /* s3c24xx_i2c_message_start
 183  *
 184  * put the start of a message onto the bus
 185 */
 186
 187 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 188                                       struct i2c_msg *msg)
 189 {
 190         unsigned int addr = (msg->addr & 0x7f) << 1;
 191         unsigned long stat;
 192         unsigned long iiccon;
 193
 194         stat = 0;
 195         stat |=  S3C2410_IICSTAT_TXRXEN;
 196
 197         if (msg->flags & I2C_M_RD) {
 198                 stat |= S3C2410_IICSTAT_MASTER_RX;
 199                 addr |= 1;
 200         } else
 201                 stat |= S3C2410_IICSTAT_MASTER_TX;
 202
 203         if (msg->flags & I2C_M_REV_DIR_ADDR)
 204                 addr ^= 1;
 205
 206         /* todo - check for wether ack wanted or not */
 207         s3c24xx_i2c_enable_ack(i2c);
 208
 209         iiccon = readl(i2c->regs + S3C2410_IICCON);
 210         writel(stat, i2c->regs + S3C2410_IICSTAT);
 211
 212         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 213         writeb(addr, i2c->regs + S3C2410_IICDS);
 214
 215         /* delay here to ensure the data byte has gotten onto the bus
 216          * before the transaction is started */
 217
 218         ndelay(i2c->tx_setup);
 219
 220         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 221         writel(iiccon, i2c->regs + S3C2410_IICCON);
 222
 223         stat |= S3C2410_IICSTAT_START;
 224         writel(stat, i2c->regs + S3C2410_IICSTAT);
 225 }
 226
 227 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 228 {
 229         unsigned long iicstat;
 230         unsigned long iiccon;
 231
 232         dev_dbg(i2c->dev, "STOP\n");
 233
 234         /* stop the transfer */
 235
 236         /* Disable irq */
 237         s3c24xx_i2c_disable_irq(i2c);
 238
 239         /* STOP signal generation : MTx(0xD0) */
 240         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 241         iicstat &= ~S3C2410_IICSTAT_START;
 242         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 243
 244         /* Clear pending bit */
 245         iiccon = readl(i2c->regs + S3C2410_IICCON);
 246         iiccon &= ~S3C2410_IICCON_IRQPEND;
 247         writel(iiccon, i2c->regs + S3C2410_IICCON);
 248
 249         s3c24xx_i2c_master_complete(i2c, ret);
 250
 251         i2c->state = STATE_STOP;
 252 }
 253
 254 /* helper functions to determine the current state in the set of
 255  * messages we are sending */
 256
 257 /* is_lastmsg()
 258  *
 259  * returns TRUE if the current message is the last in the set
 260 */
 261
 262 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 263 {
 264         return i2c->msg_idx >= (i2c->msg_num - 1);
 265 }
 266
 267 /* is_msglast
 268  *
 269  * returns TRUE if we this is the last byte in the current message
 270 */
 271
 272 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 273 {
 274         return i2c->msg_ptr == i2c->msg->len-1;
 275 }
 276
 277 /* is_msgend
 278  *
 279  * returns TRUE if we reached the end of the current message
 280 */
 281
 282 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 283 {
 284         return i2c->msg_ptr >= i2c->msg->len;
 285 }
 286
 287 /* i2c_s3c_irq_nextbyte
 288  *
 289  * process an interrupt and work out what to do
 290  */
 291
 292 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 293 {
 294         unsigned long tmp;
 295         unsigned char byte;
 296         int ret = 0;
 297
 298         switch (i2c->state) {
 299
 300         case STATE_IDLE:
 301                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 302                 goto out;
 303
 304         case STATE_STOP:
 305                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 306                 s3c24xx_i2c_disable_irq(i2c);
 307                 goto out_ack;
 308
 309         case STATE_START:
 310                 /* last thing we did was send a start condition on the
 311                  * bus, or started a new i2c message
 312                  */
 313
 314                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 315                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 316                         /* ack was not received... */
 317
 318                         dev_dbg(i2c->dev, "ack was not received\n");
 319                         s3c24xx_i2c_stop(i2c, -ENXIO);
 320                         goto out_ack;
 321                 }
 322
 323                 if (i2c->msg->flags & I2C_M_RD)
 324                         i2c->state = STATE_READ;
 325                 else
 326                         i2c->state = STATE_WRITE;
 327
 328                 /* terminate the transfer if there is nothing to do
 329                  * as this is used by the i2c probe to find devices. */
 330
 331                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 332                         s3c24xx_i2c_stop(i2c, 0);
 333                         goto out_ack;
 334                 }
 335
 336                 if (i2c->state == STATE_READ)
 337                         goto prepare_read;
 338
 339                 /* fall through to the write state, as we will need to
 340                  * send a byte as well */
 341
 342         case STATE_WRITE:
 343                 /* we are writing data to the device... check for the
 344                  * end of the message, and if so, work out what to do
 345                  */
 346
 347                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 348                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 349                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 350
 351                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 352                                 goto out_ack;
 353                         }
 354                 }
 355
 356  retry_write:
 357
 358                 if (!is_msgend(i2c)) {
 359                         byte = i2c->msg->buf[i2c->msg_ptr++];
 360                         writeb(byte, i2c->regs + S3C2410_IICDS);
 361
 362                         /* delay after writing the byte to allow the
 363                          * data setup time on the bus, as writing the
 364                          * data to the register causes the first bit
 365                          * to appear on SDA, and SCL will change as
 366                          * soon as the interrupt is acknowledged */
 367
 368                         ndelay(i2c->tx_setup);
 369
 370                 } else if (!is_lastmsg(i2c)) {
 371                         /* we need to go to the next i2c message */
 372
 373                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 374
 375                         i2c->msg_ptr = 0;
 376                         i2c->msg_idx++;
 377                         i2c->msg++;
 378
 379                         /* check to see if we need to do another message */
 380                         if (i2c->msg->flags & I2C_M_NOSTART) {
 381
 382                                 if (i2c->msg->flags & I2C_M_RD) {
 383                                         /* cannot do this, the controller
 384                                          * forces us to send a new START
 385                                          * when we change direction */
 386
 387                                         dev_dbg(i2c->dev, "Cannot do this\n");
 388                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 389                                 }
 390
 391                                 /* For multiple messages,
 392                                  * ex)
 393                                  * Msg[0]: Slave Addr + Write(Addr)
 394                                  * Msg[1]: Write(Data) */
 395                                 goto retry_write;
 396                         } else {
 397                                 /* send the new start */
 398                                 /* For multiple messages,
 399                                  * ex)
 400                                  * Msg[0]: Slave Addr + Write(Addr)
 401                                  * Msg[1]: Slave Addr + Read/Write(Data) */
 402                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 403                                 i2c->state = STATE_START;
 404                         }
 405
 406                 } else {
 407                         /* send stop */
 408
 409                         s3c24xx_i2c_stop(i2c, 0);
 410                 }
 411                 break;
 412
 413         case STATE_READ:
 414                 /* we have a byte of data in the data register, do
 415                  * something with it, and then work out wether we are
 416                  * going to do any more read/write
 417                  */
 418
 419                 byte = readb(i2c->regs + S3C2410_IICDS);
 420                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 421
 422  prepare_read:
 423                 if (is_msglast(i2c)) {
 424                         /* last byte of buffer */
 425
 426                         if (is_lastmsg(i2c))
 427                                 s3c24xx_i2c_disable_ack(i2c);
 428
 429                 } else if (is_msgend(i2c)) {
 430                         /* ok, we've read the entire buffer, see if there
 431                          * is anything else we need to do */
 432
 433                         if (is_lastmsg(i2c)) {
 434                                 /* last message, send stop and complete */
 435                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 436
 437                                 s3c24xx_i2c_stop(i2c, 0);
 438                         } else {
 439                                 /* go to the next transfer */
 440                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 441
 442                                 i2c->msg_ptr = 0;
 443                                 i2c->msg_idx++;
 444                                 i2c->msg++;
 445                         }
 446                 }
 447
 448                 break;
 449         }
 450
 451         /* acknowlegde the IRQ and get back on with the work */
 452
 453  out_ack:
 454         tmp = readl(i2c->regs + S3C2410_IICCON);
 455         tmp &= ~S3C2410_IICCON_IRQPEND;
 456         writel(tmp, i2c->regs + S3C2410_IICCON);
 457  out:
 458         return ret;
 459 }
 460
 461 /* s3c24xx_i2c_irq
 462  *
 463  * top level IRQ servicing routine
 464 */
 465
 466 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 467 {
 468         struct s3c24xx_i2c *i2c = dev_id;
 469         unsigned long status;
 470         unsigned long tmp;
 471
 472         spin_lock(&i2c->lock);
 473
 474         status = readl(i2c->regs + S3C2410_IICSTAT);
 475
 476         if (status & S3C2410_IICSTAT_ARBITR) {
 477                 /* deal with arbitration loss */
 478                 dev_err(i2c->dev, "deal with arbitration loss\n");
 479         }
 480
 481         if (i2c->state == STATE_IDLE) {
 482                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 483
 484                 tmp = readl(i2c->regs + S3C2410_IICCON);
 485                 tmp &= ~S3C2410_IICCON_IRQPEND;
 486                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 487                 goto out;
 488         }
 489
 490         /* pretty much this leaves us with the fact that we've
 491          * transmitted or received whatever byte we last sent */
 492
 493         i2c_s3c_irq_nextbyte(i2c, status);
 494
 495  out:
 496         spin_unlock(&i2c->lock);
 497
 498         return IRQ_HANDLED;
 499 }
 500
 501
 502 /* s3c24xx_i2c_set_master
 503  *
 504  * get the i2c bus for a master transaction
 505 */
 506
 507 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 508 {
 509         unsigned long iicstat;
 510         int timeout = 400;
 511
 512         while (timeout-- > 0) {
 513                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 514
 515                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 516                         return 0;
 517
 518                 msleep(1);
 519         }
 520
 521         return -ETIMEDOUT;
 522 }
 523
 524 /* s3c24xx_i2c_doxfer
 525  *
 526  * this starts an i2c transfer
 527 */
 528
 529 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 530                               struct i2c_msg *msgs, int num)
 531 {
 532         unsigned long iicstat, timeout;
 533         int spins = 20;
 534         int ret;
 535
 536         if (i2c->suspended)
 537                 return -EIO;
 538
 539         ret = s3c24xx_i2c_set_master(i2c);
 540         if (ret != 0) {
 541                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 542                 dump_i2c_register(i2c);
 543                 ret = -EAGAIN;
 544                 goto out;
 545         }
 546
 547         spin_lock_irq(&i2c->lock);
 548
 549         i2c->msg     = msgs;
 550         i2c->msg_num = num;
 551         i2c->msg_ptr = 0;
 552         i2c->msg_idx = 0;
 553         i2c->state   = STATE_START;
 554
 555         s3c24xx_i2c_enable_irq(i2c);
 556         s3c24xx_i2c_message_start(i2c, msgs);
 557         spin_unlock_irq(&i2c->lock);
 558
 559         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 560
 561         ret = i2c->msg_idx;
 562
 563         /* having these next two as dev_err() makes life very
 564          * noisy when doing an i2cdetect */
 565
 566         if (timeout == 0)
 567         {
 568                 dev_dbg(i2c->dev, "timeout\n");
 569                 dump_i2c_register(i2c);
 570         }
 571         else if (ret != num)
 572         {
 573                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 574                 dump_i2c_register(i2c);
 575         }
 576
 577         /* ensure the stop has been through the bus */
 578
 579         dev_dbg(i2c->dev, "waiting for bus idle\n");
 580
 581         /* first, try busy waiting briefly */
 582         do {
 583                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 584         } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
 585
 586         /* if that timed out sleep */
 587         if (!spins) {
 588                 usleep_range(1000, 1000);
 589                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 590         }
 591
 592         /* if still not finished, clean it up */
 593         spin_lock_irq(&i2c->lock);
 594
 595         if (iicstat & S3C2410_IICSTAT_BUSBUSY) {
 596                 dev_dbg(i2c->dev, "timeout waiting for bus idle\n");
 597                 dump_i2c_register(i2c);
 598
 599                 if (i2c->state != STATE_STOP) {
 600                         dev_dbg(i2c->dev, "timeout : i2c interrupt hasn't occurred\n");
 601                         s3c24xx_i2c_stop(i2c, 0);
 602                 }
 603
 604                 /* Disable Serial Out : To forcely terminate the connection */
 605                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 606                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 607                 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 608         }
 609         spin_unlock_irq(&i2c->lock);
 610
 611  out:
 612         return ret;
 613 }
 614
 615 /* s3c24xx_i2c_xfer
 616  *
 617  * first port of call from the i2c bus code when an message needs
 618  * transferring across the i2c bus.
 619 */
 620
 621 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 622                         struct i2c_msg *msgs, int num)
 623 {
 624         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 625         int retry;
 626         int ret;
 627
 628         if (i2c->suspended)
 629         {
 630                 dev_err(i2c->dev, "I2C is not initialzed.\n");
 631                 dump_i2c_register(i2c);
 632                 return -EIO;
 633         }
 634
 635         clk_enable(i2c->clk);
 636
 637         for (retry = 0; retry < adap->retries; retry++) {
 638
 639                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 640
 641                 if (ret != -EAGAIN) {
 642                         clk_disable(i2c->clk);
 643                         return ret;
 644                 }
 645
 646                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 647
 648                 udelay(100);
 649         }
 650
 651         clk_disable(i2c->clk);
 652         return -EREMOTEIO;
 653 }
 654
 655 /* declare our i2c functionality */
 656 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 657 {
 658         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 659 }
 660
 661 /* i2c bus registration info */
 662
 663 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 664         .master_xfer            = s3c24xx_i2c_xfer,
 665         .functionality          = s3c24xx_i2c_func,
 666 };
 667
 668 /* s3c24xx_i2c_calcdivisor
 669  *
 670  * return the divisor settings for a given frequency
 671 */
 672
 673 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 674                                    unsigned int *div1, unsigned int *divs)
 675 {
 676         unsigned int calc_divs = clkin / wanted;
 677         unsigned int calc_div1;
 678
 679         if (calc_divs > (16*16))
 680                 calc_div1 = 512;
 681         else
 682                 calc_div1 = 16;
 683
 684         calc_divs += calc_div1-1;
 685         calc_divs /= calc_div1;
 686
 687         if (calc_divs == 0)
 688                 calc_divs = 1;
 689         if (calc_divs > 17)
 690                 calc_divs = 17;
 691
 692         *divs = calc_divs;
 693         *div1 = calc_div1;
 694
 695         return clkin / (calc_divs * calc_div1);
 696 }
 697
 698 /* s3c24xx_i2c_clockrate
 699  *
 700  * work out a divisor for the user requested frequency setting,
 701  * either by the requested frequency, or scanning the acceptable
 702  * range of frequencies until something is found
 703 */
 704
 705 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 706 {
 707         struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
 708         unsigned long clkin = clk_get_rate(i2c->clk);
 709         unsigned int divs, div1;
 710         unsigned long target_frequency;
 711         u32 iiccon;
 712         int freq;
 713
 714         i2c->clkrate = clkin;
 715         clkin /= 1000;          /* clkin now in KHz */
 716
 717         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 718
 719         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 720
 721         target_frequency /= 1000; /* Target frequency now in KHz */
 722
 723         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 724
 725         if (freq > target_frequency) {
 726                 dev_err(i2c->dev,
 727                         "Unable to achieve desired frequency %luKHz."   \
 728                         " Lowest achievable %dKHz\n", target_frequency, freq);
 729                 return -EINVAL;
 730         }
 731
 732         *got = freq;
 733
 734         iiccon = readl(i2c->regs + S3C2410_IICCON);
 735         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 736         iiccon |= (divs-1);
 737
 738         if (div1 == 512)
 739                 iiccon |= S3C2410_IICCON_TXDIV_512;
 740
 741         writel(iiccon, i2c->regs + S3C2410_IICCON);
 742
 743         if (s3c24xx_i2c_is2440(i2c)) {
 744                 unsigned long sda_delay;
 745
 746                 if (pdata->sda_delay) {
 747                         sda_delay = clkin * pdata->sda_delay;
 748                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 749                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 750                         if (sda_delay > 3)
 751                                 sda_delay = 3;
 752                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 753                 } else
 754                         sda_delay = 0;
 755
 756                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 757                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 758         }
 759
 760         return 0;
 761 }
 762
 763 #ifdef CONFIG_CPU_FREQ
 764
 765 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 766
 767 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 768                                           unsigned long val, void *data)
 769 {
 770         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 771         unsigned long flags;
 772         unsigned int got;
 773         int delta_f;
 774         int ret;
 775
 776         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 777
 778         /* if we're post-change and the input clock has slowed down
 779          * or at pre-change and the clock is about to speed up, then
 780          * adjust our clock rate. <0 is slow, >0 speedup.
 781          */
 782
 783         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 784             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 785                 spin_lock_irqsave(&i2c->lock, flags);
 786                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 787                 spin_unlock_irqrestore(&i2c->lock, flags);
 788
 789                 if (ret < 0)
 790                         dev_err(i2c->dev, "cannot find frequency\n");
 791                 else
 792                         dev_dbg(i2c->dev, "setting freq %d\n", got);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 799 {
 800         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 801
 802         return cpufreq_register_notifier(&i2c->freq_transition,
 803                                          CPUFREQ_TRANSITION_NOTIFIER);
 804 }
 805
 806 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 807 {
 808         cpufreq_unregister_notifier(&i2c->freq_transition,
 809                                     CPUFREQ_TRANSITION_NOTIFIER);
 810 }
 811
 812 #else
 813 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 814 {
 815         return 0;
 816 }
 817
 818 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 819 {
 820 }
 821 #endif
 822
 823 /* s3c24xx_i2c_init
 824  *
 825  * initialise the controller, set the IO lines and frequency
 826 */
 827
 828 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 829 {
 830         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 831         struct s3c2410_platform_i2c *pdata;
 832         unsigned int freq;
 833
 834         /* get the plafrom data */
 835
 836         pdata = i2c->dev->platform_data;
 837
 838         /* inititalise the gpio */
 839
 840         if (pdata->cfg_gpio)
 841                 pdata->cfg_gpio(to_platform_device(i2c->dev));
 842
 843         /* write slave address */
 844
 845         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 846
 847         dev_dbg(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 848
 849         writel(iicon, i2c->regs + S3C2410_IICCON);
 850
 851         /* we need to work out the divisors for the clock... */
 852
 853         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 854                 writel(0, i2c->regs + S3C2410_IICCON);
 855                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 856                 return -EINVAL;
 857         }
 858
 859         /* todo - check that the i2c lines aren't being dragged anywhere */
 860
 861         dev_dbg(i2c->dev, "bus frequency set to %d KHz\n", freq);
 862         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 863
 864         return 0;
 865 }
 866
 867 /* s3c24xx_i2c_probe
 868  *
 869  * called by the bus driver when a suitable device is found
 870 */
 871
 872 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 873 {
 874         struct s3c24xx_i2c *i2c;
 875         struct s3c2410_platform_i2c *pdata;
 876         struct resource *res;
 877         int ret;
 878
 879         pdata = pdev->dev.platform_data;
 880         if (!pdata) {
 881                 dev_err(&pdev->dev, "no platform data\n");
 882                 return -EINVAL;
 883         }
 884
 885         i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
 886         if (!i2c) {
 887                 dev_err(&pdev->dev, "no memory for state\n");
 888                 return -ENOMEM;
 889         }
 890
 891         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
 892         i2c->adap.owner   = THIS_MODULE;
 893         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
 894         i2c->adap.retries = 2;
 895         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 896         i2c->tx_setup     = 50;
 897
 898         spin_lock_init(&i2c->lock);
 899         init_waitqueue_head(&i2c->wait);
 900
 901         /* find the clock and enable it */
 902
 903         i2c->dev = &pdev->dev;
 904         i2c->clk = clk_get(&pdev->dev, "i2c");
 905         if (IS_ERR(i2c->clk)) {
 906                 dev_err(&pdev->dev, "cannot get clock\n");
 907                 ret = -ENOENT;
 908                 goto err_noclk;
 909         }
 910
 911         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 912
 913         clk_enable(i2c->clk);
 914
 915         /* map the registers */
 916
 917         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 918         if (res == NULL) {
 919                 dev_err(&pdev->dev, "cannot find IO resource\n");
 920                 ret = -ENOENT;
 921                 goto err_clk;
 922         }
 923
 924         i2c->ioarea = request_mem_region(res->start, resource_size(res),
 925                                          pdev->name);
 926
 927         if (i2c->ioarea == NULL) {
 928                 dev_err(&pdev->dev, "cannot request IO\n");
 929                 ret = -ENXIO;
 930                 goto err_clk;
 931         }
 932
 933         i2c->regs = ioremap(res->start, resource_size(res));
 934
 935         if (i2c->regs == NULL) {
 936                 dev_err(&pdev->dev, "cannot map IO\n");
 937                 ret = -ENXIO;
 938                 goto err_ioarea;
 939         }
 940
 941         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 942                 i2c->regs, i2c->ioarea, res);
 943
 944         /* setup info block for the i2c core */
 945
 946         i2c->adap.algo_data = i2c;
 947         i2c->adap.dev.parent = &pdev->dev;
 948
 949         /* initialise the i2c controller */
 950
 951         ret = s3c24xx_i2c_init(i2c);
 952         if (ret != 0)
 953                 goto err_iomap;
 954
 955         /* find the IRQ for this unit (note, this relies on the init call to
 956          * ensure no current IRQs pending
 957          */
 958
 959         i2c->irq = ret = platform_get_irq(pdev, 0);
 960         if (ret <= 0) {
 961                 dev_err(&pdev->dev, "cannot find IRQ\n");
 962                 goto err_iomap;
 963         }
 964
 965         ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
 966                           dev_name(&pdev->dev), i2c);
 967
 968         if (ret != 0) {
 969                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
 970                 goto err_iomap;
 971         }
 972
 973         ret = s3c24xx_i2c_register_cpufreq(i2c);
 974         if (ret < 0) {
 975                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
 976                 goto err_irq;
 977         }
 978
 979         /* Note, previous versions of the driver used i2c_add_adapter()
 980          * to add the bus at any number. We now pass the bus number via
 981          * the platform data, so if unset it will now default to always
 982          * being bus 0.
 983          */
 984
 985         i2c->adap.nr = pdata->bus_num;
 986
 987         ret = i2c_add_numbered_adapter(&i2c->adap);
 988         if (ret < 0) {
 989                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 990                 goto err_cpufreq;
 991         }
 992
 993         platform_set_drvdata(pdev, i2c);
 994
 995         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
 996         clk_disable(i2c->clk);
 997         return 0;
 998
 999  err_cpufreq:
1000         s3c24xx_i2c_deregister_cpufreq(i2c);
1001
1002  err_irq:
1003         free_irq(i2c->irq, i2c);
1004
1005  err_iomap:
1006         iounmap(i2c->regs);
1007
1008  err_ioarea:
1009         release_resource(i2c->ioarea);
1010         kfree(i2c->ioarea);
1011
1012  err_clk:
1013         clk_disable(i2c->clk);
1014         clk_put(i2c->clk);
1015
1016  err_noclk:
1017         kfree(i2c);
1018         return ret;
1019 }
1020
1021 /* s3c24xx_i2c_remove
1022  *
1023  * called when device is removed from the bus
1024 */
1025
1026 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1027 {
1028         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1029
1030         s3c24xx_i2c_deregister_cpufreq(i2c);
1031
1032         i2c_del_adapter(&i2c->adap);
1033         free_irq(i2c->irq, i2c);
1034
1035         clk_disable(i2c->clk);
1036         clk_put(i2c->clk);
1037
1038         iounmap(i2c->regs);
1039
1040         release_resource(i2c->ioarea);
1041         kfree(i2c->ioarea);
1042         kfree(i2c);
1043
1044         return 0;
1045 }
1046
1047 #ifdef CONFIG_PM
1048 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1049 {
1050         struct platform_device *pdev = to_platform_device(dev);
1051         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1052
1053         i2c->suspended = 1;
1054
1055         return 0;
1056 }
1057
1058 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1059 {
1060         struct platform_device *pdev = to_platform_device(dev);
1061         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1062
1063         clk_enable(i2c->clk);
1064         s3c24xx_i2c_init(i2c);
1065         clk_disable(i2c->clk);
1066         i2c->suspended = 0;
1067
1068         return 0;
1069 }
1070
1071 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1072         .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1073         .resume_noirq = s3c24xx_i2c_resume_noirq,
1074 #ifdef CONFIG_HIBERNATION
1075         .freeze_noirq = s3c24xx_i2c_suspend_noirq,
1076         .thaw_noirq = s3c24xx_i2c_resume_noirq,
1077         .restore_noirq = s3c24xx_i2c_resume_noirq,
1078 #endif
1079 };
1080
1081 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1082 #else
1083 #define S3C24XX_DEV_PM_OPS NULL
1084 #endif
1085
1086 /* device driver for platform bus bits */
1087
1088 static struct platform_device_id s3c24xx_driver_ids[] = {
1089         {
1090                 .name           = "s3c2410-i2c",
1091                 .driver_data    = TYPE_S3C2410,
1092         }, {
1093                 .name           = "s3c2440-i2c",
1094                 .driver_data    = TYPE_S3C2440,
1095         }, {
1096                 .name           = "s3c2440-hdmiphy-i2c",
1097                 .driver_data    = TYPE_S3C2440_HDMIPHY,
1098         }, { },
1099 };
1100 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1101
1102 static struct platform_driver s3c24xx_i2c_driver = {
1103         .probe          = s3c24xx_i2c_probe,
1104         .remove         = s3c24xx_i2c_remove,
1105         .id_table       = s3c24xx_driver_ids,
1106         .driver         = {
1107                 .owner  = THIS_MODULE,
1108                 .name   = "s3c-i2c",
1109                 .pm     = S3C24XX_DEV_PM_OPS,
1110         },
1111 };
1112
1113 static int __init i2c_adap_s3c_init(void)
1114 {
1115         return platform_driver_register(&s3c24xx_i2c_driver);
1116 }
1117 #ifdef CONFIG_FAST_RESUME
1118 beforeresume_initcall(i2c_adap_s3c_init);
1119 #else
1120 subsys_initcall(i2c_adap_s3c_init);
1121 #endif
1122
1123 static void __exit i2c_adap_s3c_exit(void)
1124 {
1125         platform_driver_unregister(&s3c24xx_i2c_driver);
1126 }
1127 module_exit(i2c_adap_s3c_exit);
1128
1129 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1130 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1131 MODULE_LICENSE("GPL");