sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/soc-dapm.h>
  40 #include <sound/initval.h>
  41 #include <sound/tlv.h>
  42
  43 #include <sound/tlv320dac33-plat.h>
  44 #include "tlv320dac33.h"
  45
  46 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  47                                                  * 6144 stereo */
  48 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  49
  50 #define NSAMPLE_MAX             5700
  51
  52 #define MODE7_LTHR              10
  53 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / us))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 static struct snd_soc_codec *tlv320dac33_codec;
  70
  71 enum dac33_state {
  72         DAC33_IDLE = 0,
  73         DAC33_PREFILL,
  74         DAC33_PLAYBACK,
  75         DAC33_FLUSH,
  76 };
  77
  78 enum dac33_fifo_modes {
  79         DAC33_FIFO_BYPASS = 0,
  80         DAC33_FIFO_MODE1,
  81         DAC33_FIFO_MODE7,
  82         DAC33_FIFO_LAST_MODE,
  83 };
  84
  85 #define DAC33_NUM_SUPPLIES 3
  86 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  87         "AVDD",
  88         "DVDD",
  89         "IOVDD",
  90 };
  91
  92 struct tlv320dac33_priv {
  93         struct mutex mutex;
  94         struct workqueue_struct *dac33_wq;
  95         struct work_struct work;
  96         struct snd_soc_codec codec;
  97         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  98         struct snd_pcm_substream *substream;
  99         int power_gpio;
 100         int chip_power;
 101         int irq;
 102         unsigned int refclk;
 103
 104         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 105         unsigned int nsample_min;       /* nsample should not be lower than
 106                                          * this */
 107         unsigned int nsample_max;       /* nsample should not be higher than
 108                                          * this */
 109         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 110         unsigned int nsample;           /* burst read amount from host */
 111         int mode1_latency;              /* latency caused by the i2c writes in
 112                                          * us */
 113         int auto_fifo_config;           /* Configure the FIFO based on the
 114                                          * period size */
 115         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 116         unsigned int burst_rate;        /* Interface speed in Burst modes */
 117
 118         int keep_bclk;                  /* Keep the BCLK continuously running
 119                                          * in FIFO modes */
 120         spinlock_t lock;
 121         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 122         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 123
 124         unsigned int mode1_us_burst;    /* Time to burst read n number of
 125                                          * samples */
 126         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 127
 128         unsigned int uthr;
 129
 130         enum dac33_state state;
 131 };
 132
 133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 148 0x00, 0x00,             /* 0x38 - 0x39 */
 149 /* Registers 0x3a - 0x3f are reserved  */
 150             0x00, 0x00, /* 0x3a - 0x3b */
 151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 152
 153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 154 0x00, 0x80,             /* 0x44 - 0x45 */
 155 /* Registers 0x46 - 0x47 are reserved  */
 156             0x80, 0x80, /* 0x46 - 0x47 */
 157
 158 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 159 /* Registers 0x4b - 0x7c are reserved  */
 160                   0x00, /* 0x4b        */
 161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 173 0x00,                   /* 0x7c        */
 174
 175       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 176 };
 177
 178 /* Register read and write */
 179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 180                                                 unsigned reg)
 181 {
 182         u8 *cache = codec->reg_cache;
 183         if (reg >= DAC33_CACHEREGNUM)
 184                 return 0;
 185
 186         return cache[reg];
 187 }
 188
 189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 190                                          u8 reg, u8 value)
 191 {
 192         u8 *cache = codec->reg_cache;
 193         if (reg >= DAC33_CACHEREGNUM)
 194                 return;
 195
 196         cache[reg] = value;
 197 }
 198
 199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 200                       u8 *value)
 201 {
 202         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 203         int val;
 204
 205         *value = reg & 0xff;
 206
 207         /* If powered off, return the cached value */
 208         if (dac33->chip_power) {
 209                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 210                 if (val < 0) {
 211                         dev_err(codec->dev, "Read failed (%d)\n", val);
 212                         value[0] = dac33_read_reg_cache(codec, reg);
 213                 } else {
 214                         value[0] = val;
 215                         dac33_write_reg_cache(codec, reg, val);
 216                 }
 217         } else {
 218                 value[0] = dac33_read_reg_cache(codec, reg);
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 225                        unsigned int value)
 226 {
 227         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 228         u8 data[2];
 229         int ret = 0;
 230
 231         /*
 232          * data is
 233          *   D15..D8 dac33 register offset
 234          *   D7...D0 register data
 235          */
 236         data[0] = reg & 0xff;
 237         data[1] = value & 0xff;
 238
 239         dac33_write_reg_cache(codec, data[0], data[1]);
 240         if (dac33->chip_power) {
 241                 ret = codec->hw_write(codec->control_data, data, 2);
 242                 if (ret != 2)
 243                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 244                 else
 245                         ret = 0;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 252                        unsigned int value)
 253 {
 254         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 255         int ret;
 256
 257         mutex_lock(&dac33->mutex);
 258         ret = dac33_write(codec, reg, value);
 259         mutex_unlock(&dac33->mutex);
 260
 261         return ret;
 262 }
 263
 264 #define DAC33_I2C_ADDR_AUTOINC  0x80
 265 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 266                        unsigned int value)
 267 {
 268         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 269         u8 data[3];
 270         int ret = 0;
 271
 272         /*
 273          * data is
 274          *   D23..D16 dac33 register offset
 275          *   D15..D8  register data MSB
 276          *   D7...D0  register data LSB
 277          */
 278         data[0] = reg & 0xff;
 279         data[1] = (value >> 8) & 0xff;
 280         data[2] = value & 0xff;
 281
 282         dac33_write_reg_cache(codec, data[0], data[1]);
 283         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 284
 285         if (dac33->chip_power) {
 286                 /* We need to set autoincrement mode for 16 bit writes */
 287                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 288                 ret = codec->hw_write(codec->control_data, data, 3);
 289                 if (ret != 3)
 290                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 291                 else
 292                         ret = 0;
 293         }
 294
 295         return ret;
 296 }
 297
 298 static void dac33_init_chip(struct snd_soc_codec *codec)
 299 {
 300         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 301
 302         if (unlikely(!dac33->chip_power))
 303                 return;
 304
 305         /* 44-46: DAC Control Registers */
 306         /* A : DAC sample rate Fsref/1.5 */
 307         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 308         /* B : DAC src=normal, not muted */
 309         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 310                                              DAC33_DACSRCL_LEFT);
 311         /* C : (defaults) */
 312         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 313
 314         /* 73 : volume soft stepping control,
 315          clock source = internal osc (?) */
 316         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 317
 318         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
 319
 320         /* Restore only selected registers (gains mostly) */
 321         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 322                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 323         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 324                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 325
 326         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 327                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 328         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 329                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 330 }
 331
 332 static inline void dac33_read_id(struct snd_soc_codec *codec)
 333 {
 334         u8 reg;
 335
 336         dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
 337         dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
 338         dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
 339 }
 340
 341 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 342 {
 343         u8 reg;
 344
 345         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 346         if (power)
 347                 reg |= DAC33_PDNALLB;
 348         else
 349                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 350                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 351         dac33_write(codec, DAC33_PWR_CTRL, reg);
 352 }
 353
 354 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 355 {
 356         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 357         int ret = 0;
 358
 359         mutex_lock(&dac33->mutex);
 360
 361         /* Safety check */
 362         if (unlikely(power == dac33->chip_power)) {
 363                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 364                         power ? "ON" : "OFF");
 365                 goto exit;
 366         }
 367
 368         if (power) {
 369                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 370                                           dac33->supplies);
 371                 if (ret != 0) {
 372                         dev_err(codec->dev,
 373                                 "Failed to enable supplies: %d\n", ret);
 374                                 goto exit;
 375                 }
 376
 377                 if (dac33->power_gpio >= 0)
 378                         gpio_set_value(dac33->power_gpio, 1);
 379
 380                 dac33->chip_power = 1;
 381         } else {
 382                 dac33_soft_power(codec, 0);
 383                 if (dac33->power_gpio >= 0)
 384                         gpio_set_value(dac33->power_gpio, 0);
 385
 386                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 387                                              dac33->supplies);
 388                 if (ret != 0) {
 389                         dev_err(codec->dev,
 390                                 "Failed to disable supplies: %d\n", ret);
 391                         goto exit;
 392                 }
 393
 394                 dac33->chip_power = 0;
 395         }
 396
 397 exit:
 398         mutex_unlock(&dac33->mutex);
 399         return ret;
 400 }
 401
 402 static int playback_event(struct snd_soc_dapm_widget *w,
 403                 struct snd_kcontrol *kcontrol, int event)
 404 {
 405         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 406
 407         switch (event) {
 408         case SND_SOC_DAPM_PRE_PMU:
 409                 if (likely(dac33->substream)) {
 410                         dac33_calculate_times(dac33->substream);
 411                         dac33_prepare_chip(dac33->substream);
 412                 }
 413                 break;
 414         }
 415         return 0;
 416 }
 417
 418 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 419                          struct snd_ctl_elem_value *ucontrol)
 420 {
 421         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 422         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 423
 424         ucontrol->value.integer.value[0] = dac33->nsample;
 425
 426         return 0;
 427 }
 428
 429 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 430                          struct snd_ctl_elem_value *ucontrol)
 431 {
 432         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 433         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 434         int ret = 0;
 435
 436         if (dac33->nsample == ucontrol->value.integer.value[0])
 437                 return 0;
 438
 439         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 440             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 441                 ret = -EINVAL;
 442         } else {
 443                 dac33->nsample = ucontrol->value.integer.value[0];
 444                 /* Re calculate the burst time */
 445                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 446                                                       dac33->nsample);
 447         }
 448
 449         return ret;
 450 }
 451
 452 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
 453                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 457
 458         ucontrol->value.integer.value[0] = dac33->uthr;
 459
 460         return 0;
 461 }
 462
 463 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
 464                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 468         int ret = 0;
 469
 470         if (dac33->substream)
 471                 return -EBUSY;
 472
 473         if (dac33->uthr == ucontrol->value.integer.value[0])
 474                 return 0;
 475
 476         if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
 477             ucontrol->value.integer.value[0] > MODE7_UTHR)
 478                 ret = -EINVAL;
 479         else
 480                 dac33->uthr = ucontrol->value.integer.value[0];
 481
 482         return ret;
 483 }
 484
 485 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 486                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 490
 491         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 492
 493         return 0;
 494 }
 495
 496 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 497                          struct snd_ctl_elem_value *ucontrol)
 498 {
 499         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 500         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 501         int ret = 0;
 502
 503         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 504                 return 0;
 505         /* Do not allow changes while stream is running*/
 506         if (codec->active)
 507                 return -EPERM;
 508
 509         if (ucontrol->value.integer.value[0] < 0 ||
 510             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 511                 ret = -EINVAL;
 512         else
 513                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 514
 515         return ret;
 516 }
 517
 518 /* Codec operation modes */
 519 static const char *dac33_fifo_mode_texts[] = {
 520         "Bypass", "Mode 1", "Mode 7"
 521 };
 522
 523 static const struct soc_enum dac33_fifo_mode_enum =
 524         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 525                             dac33_fifo_mode_texts);
 526
 527 /*
 528  * DACL/R digital volume control:
 529  * from 0 dB to -63.5 in 0.5 dB steps
 530  * Need to be inverted later on:
 531  * 0x00 == 0 dB
 532  * 0x7f == -63.5 dB
 533  */
 534 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 535
 536 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 537         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 538                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 539                 0, 0x7f, 1, dac_digivol_tlv),
 540         SOC_DOUBLE_R("DAC Digital Playback Switch",
 541                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 542         SOC_DOUBLE_R("Line to Line Out Volume",
 543                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 544 };
 545
 546 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 547         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 548                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 549 };
 550
 551 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
 552         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 553                 dac33_get_nsample, dac33_set_nsample),
 554         SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
 555                  dac33_get_uthr, dac33_set_uthr),
 556 };
 557
 558 /* Analog bypass */
 559 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 560         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 561
 562 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 563         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 564
 565 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 566         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 567         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 568
 569         SND_SOC_DAPM_INPUT("LINEL"),
 570         SND_SOC_DAPM_INPUT("LINER"),
 571
 572         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 573         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 574
 575         /* Analog bypass */
 576         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 577                                 &dac33_dapm_abypassl_control),
 578         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 579                                 &dac33_dapm_abypassr_control),
 580
 581         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 582                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 583         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 584                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 585
 586         SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
 587 };
 588
 589 static const struct snd_soc_dapm_route audio_map[] = {
 590         /* Analog bypass */
 591         {"Analog Left Bypass", "Switch", "LINEL"},
 592         {"Analog Right Bypass", "Switch", "LINER"},
 593
 594         {"Output Left Amp Power", NULL, "DACL"},
 595         {"Output Right Amp Power", NULL, "DACR"},
 596
 597         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 598         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 599
 600         /* output */
 601         {"LEFT_LO", NULL, "Output Left Amp Power"},
 602         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 603 };
 604
 605 static int dac33_add_widgets(struct snd_soc_codec *codec)
 606 {
 607         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
 608                                   ARRAY_SIZE(dac33_dapm_widgets));
 609
 610         /* set up audio path interconnects */
 611         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 612
 613         return 0;
 614 }
 615
 616 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 617                                 enum snd_soc_bias_level level)
 618 {
 619         int ret;
 620
 621         switch (level) {
 622         case SND_SOC_BIAS_ON:
 623                 dac33_soft_power(codec, 1);
 624                 break;
 625         case SND_SOC_BIAS_PREPARE:
 626                 break;
 627         case SND_SOC_BIAS_STANDBY:
 628                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 629                         /* Coming from OFF, switch on the codec */
 630                         ret = dac33_hard_power(codec, 1);
 631                         if (ret != 0)
 632                                 return ret;
 633
 634                         dac33_init_chip(codec);
 635                 }
 636                 break;
 637         case SND_SOC_BIAS_OFF:
 638                 /* Do not power off, when the codec is already off */
 639                 if (codec->bias_level == SND_SOC_BIAS_OFF)
 640                         return 0;
 641                 ret = dac33_hard_power(codec, 0);
 642                 if (ret != 0)
 643                         return ret;
 644                 break;
 645         }
 646         codec->bias_level = level;
 647
 648         return 0;
 649 }
 650
 651 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 652 {
 653         struct snd_soc_codec *codec;
 654
 655         codec = &dac33->codec;
 656
 657         switch (dac33->fifo_mode) {
 658         case DAC33_FIFO_MODE1:
 659                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 660                         DAC33_THRREG(dac33->nsample));
 661
 662                 /* Take the timestamps */
 663                 spin_lock_irq(&dac33->lock);
 664                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 665                 dac33->t_stamp1 = dac33->t_stamp2;
 666                 spin_unlock_irq(&dac33->lock);
 667
 668                 dac33_write16(codec, DAC33_PREFILL_MSB,
 669                                 DAC33_THRREG(dac33->alarm_threshold));
 670                 /* Enable Alarm Threshold IRQ with a delay */
 671                 udelay(SAMPLES_TO_US(dac33->burst_rate,
 672                                      dac33->alarm_threshold));
 673                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 674                 break;
 675         case DAC33_FIFO_MODE7:
 676                 /* Take the timestamp */
 677                 spin_lock_irq(&dac33->lock);
 678                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 679                 /* Move back the timestamp with drain time */
 680                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 681                 spin_unlock_irq(&dac33->lock);
 682
 683                 dac33_write16(codec, DAC33_PREFILL_MSB,
 684                                 DAC33_THRREG(MODE7_LTHR));
 685
 686                 /* Enable Upper Threshold IRQ */
 687                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 688                 break;
 689         default:
 690                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 691                                                         dac33->fifo_mode);
 692                 break;
 693         }
 694 }
 695
 696 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 697 {
 698         struct snd_soc_codec *codec;
 699
 700         codec = &dac33->codec;
 701
 702         switch (dac33->fifo_mode) {
 703         case DAC33_FIFO_MODE1:
 704                 /* Take the timestamp */
 705                 spin_lock_irq(&dac33->lock);
 706                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 707                 spin_unlock_irq(&dac33->lock);
 708
 709                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 710                                 DAC33_THRREG(dac33->nsample));
 711                 break;
 712         case DAC33_FIFO_MODE7:
 713                 /* At the moment we are not using interrupts in mode7 */
 714                 break;
 715         default:
 716                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 717                                                         dac33->fifo_mode);
 718                 break;
 719         }
 720 }
 721
 722 static void dac33_work(struct work_struct *work)
 723 {
 724         struct snd_soc_codec *codec;
 725         struct tlv320dac33_priv *dac33;
 726         u8 reg;
 727
 728         dac33 = container_of(work, struct tlv320dac33_priv, work);
 729         codec = &dac33->codec;
 730
 731         mutex_lock(&dac33->mutex);
 732         switch (dac33->state) {
 733         case DAC33_PREFILL:
 734                 dac33->state = DAC33_PLAYBACK;
 735                 dac33_prefill_handler(dac33);
 736                 break;
 737         case DAC33_PLAYBACK:
 738                 dac33_playback_handler(dac33);
 739                 break;
 740         case DAC33_IDLE:
 741                 break;
 742         case DAC33_FLUSH:
 743                 dac33->state = DAC33_IDLE;
 744                 /* Mask all interrupts from dac33 */
 745                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 746
 747                 /* flush fifo */
 748                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 749                 reg |= DAC33_FIFOFLUSH;
 750                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 751                 break;
 752         }
 753         mutex_unlock(&dac33->mutex);
 754 }
 755
 756 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 757 {
 758         struct snd_soc_codec *codec = dev;
 759         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 760
 761         spin_lock(&dac33->lock);
 762         dac33->t_stamp1 = ktime_to_us(ktime_get());
 763         spin_unlock(&dac33->lock);
 764
 765         /* Do not schedule the workqueue in Mode7 */
 766         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 767                 queue_work(dac33->dac33_wq, &dac33->work);
 768
 769         return IRQ_HANDLED;
 770 }
 771
 772 static void dac33_oscwait(struct snd_soc_codec *codec)
 773 {
 774         int timeout = 20;
 775         u8 reg;
 776
 777         do {
 778                 msleep(1);
 779                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 780         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 781         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 782                 dev_err(codec->dev,
 783                         "internal oscillator calibration failed\n");
 784 }
 785
 786 static int dac33_startup(struct snd_pcm_substream *substream,
 787                            struct snd_soc_dai *dai)
 788 {
 789         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 790         struct snd_soc_device *socdev = rtd->socdev;
 791         struct snd_soc_codec *codec = socdev->card->codec;
 792         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 793
 794         /* Stream started, save the substream pointer */
 795         dac33->substream = substream;
 796
 797         return 0;
 798 }
 799
 800 static void dac33_shutdown(struct snd_pcm_substream *substream,
 801                              struct snd_soc_dai *dai)
 802 {
 803         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 804         struct snd_soc_device *socdev = rtd->socdev;
 805         struct snd_soc_codec *codec = socdev->card->codec;
 806         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 807
 808         dac33->substream = NULL;
 809
 810         /* Reset the nSample restrictions */
 811         dac33->nsample_min = 0;
 812         dac33->nsample_max = NSAMPLE_MAX;
 813 }
 814
 815 static int dac33_hw_params(struct snd_pcm_substream *substream,
 816                            struct snd_pcm_hw_params *params,
 817                            struct snd_soc_dai *dai)
 818 {
 819         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 820         struct snd_soc_device *socdev = rtd->socdev;
 821         struct snd_soc_codec *codec = socdev->card->codec;
 822
 823         /* Check parameters for validity */
 824         switch (params_rate(params)) {
 825         case 44100:
 826         case 48000:
 827                 break;
 828         default:
 829                 dev_err(codec->dev, "unsupported rate %d\n",
 830                         params_rate(params));
 831                 return -EINVAL;
 832         }
 833
 834         switch (params_format(params)) {
 835         case SNDRV_PCM_FORMAT_S16_LE:
 836                 break;
 837         default:
 838                 dev_err(codec->dev, "unsupported format %d\n",
 839                         params_format(params));
 840                 return -EINVAL;
 841         }
 842
 843         return 0;
 844 }
 845
 846 #define CALC_OSCSET(rate, refclk) ( \
 847         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 848 #define CALC_RATIOSET(rate, refclk) ( \
 849         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 850
 851 /*
 852  * tlv320dac33 is strict on the sequence of the register writes, if the register
 853  * writes happens in different order, than dac33 might end up in unknown state.
 854  * Use the known, working sequence of register writes to initialize the dac33.
 855  */
 856 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 857 {
 858         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 859         struct snd_soc_device *socdev = rtd->socdev;
 860         struct snd_soc_codec *codec = socdev->card->codec;
 861         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 862         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 863         u8 aictrl_a, aictrl_b, fifoctrl_a;
 864
 865         switch (substream->runtime->rate) {
 866         case 44100:
 867         case 48000:
 868                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 869                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 870                                          dac33->refclk);
 871                 break;
 872         default:
 873                 dev_err(codec->dev, "unsupported rate %d\n",
 874                         substream->runtime->rate);
 875                 return -EINVAL;
 876         }
 877
 878
 879         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 880         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 881         /* Read FIFO control A, and clear FIFO flush bit */
 882         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 883         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 884
 885         fifoctrl_a &= ~DAC33_WIDTH;
 886         switch (substream->runtime->format) {
 887         case SNDRV_PCM_FORMAT_S16_LE:
 888                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 889                 fifoctrl_a |= DAC33_WIDTH;
 890                 break;
 891         default:
 892                 dev_err(codec->dev, "unsupported format %d\n",
 893                         substream->runtime->format);
 894                 return -EINVAL;
 895         }
 896
 897         mutex_lock(&dac33->mutex);
 898
 899         if (!dac33->chip_power) {
 900                 /*
 901                  * Chip is not powered yet.
 902                  * Do the init in the dac33_set_bias_level later.
 903                  */
 904                 mutex_unlock(&dac33->mutex);
 905                 return 0;
 906         }
 907
 908         dac33_soft_power(codec, 0);
 909         dac33_soft_power(codec, 1);
 910
 911         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 912         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 913
 914         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 915         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 916
 917         /* calib time: 128 is a nice number ;) */
 918         dac33_write(codec, DAC33_CALIB_TIME, 128);
 919
 920         /* adjustment treshold & step */
 921         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 922                                                  DAC33_ADJSTEP(1));
 923
 924         /* div=4 / gain=1 / div */
 925         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 926
 927         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 928         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 929         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 930
 931         dac33_oscwait(codec);
 932
 933         if (dac33->fifo_mode) {
 934                 /* Generic for all FIFO modes */
 935                 /* 50-51 : ASRC Control registers */
 936                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 937                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 938
 939                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 940                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 941
 942                 /* Set interrupts to high active */
 943                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 944         } else {
 945                 /* FIFO bypass mode */
 946                 /* 50-51 : ASRC Control registers */
 947                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 948                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 949         }
 950
 951         /* Interrupt behaviour configuration */
 952         switch (dac33->fifo_mode) {
 953         case DAC33_FIFO_MODE1:
 954                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 955                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 956                 break;
 957         case DAC33_FIFO_MODE7:
 958                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 959                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 960                 break;
 961         default:
 962                 /* in FIFO bypass mode, the interrupts are not used */
 963                 break;
 964         }
 965
 966         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 967
 968         switch (dac33->fifo_mode) {
 969         case DAC33_FIFO_MODE1:
 970                 /*
 971                  * For mode1:
 972                  * Disable the FIFO bypass (Enable the use of FIFO)
 973                  * Select nSample mode
 974                  * BCLK is only running when data is needed by DAC33
 975                  */
 976                 fifoctrl_a &= ~DAC33_FBYPAS;
 977                 fifoctrl_a &= ~DAC33_FAUTO;
 978                 if (dac33->keep_bclk)
 979                         aictrl_b |= DAC33_BCLKON;
 980                 else
 981                         aictrl_b &= ~DAC33_BCLKON;
 982                 break;
 983         case DAC33_FIFO_MODE7:
 984                 /*
 985                  * For mode1:
 986                  * Disable the FIFO bypass (Enable the use of FIFO)
 987                  * Select Threshold mode
 988                  * BCLK is only running when data is needed by DAC33
 989                  */
 990                 fifoctrl_a &= ~DAC33_FBYPAS;
 991                 fifoctrl_a |= DAC33_FAUTO;
 992                 if (dac33->keep_bclk)
 993                         aictrl_b |= DAC33_BCLKON;
 994                 else
 995                         aictrl_b &= ~DAC33_BCLKON;
 996                 break;
 997         default:
 998                 /*
 999                  * For FIFO bypass mode:
1000                  * Enable the FIFO bypass (Disable the FIFO use)
1001                  * Set the BCLK as continous
1002                  */
1003                 fifoctrl_a |= DAC33_FBYPAS;
1004                 aictrl_b |= DAC33_BCLKON;
1005                 break;
1006         }
1007
1008         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1009         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1010         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1011
1012         /*
1013          * BCLK divide ratio
1014          * 0: 1.5
1015          * 1: 1
1016          * 2: 2
1017          * ...
1018          * 254: 254
1019          * 255: 255
1020          */
1021         if (dac33->fifo_mode)
1022                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1023                                                         dac33->burst_bclkdiv);
1024         else
1025                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1026
1027         switch (dac33->fifo_mode) {
1028         case DAC33_FIFO_MODE1:
1029                 dac33_write16(codec, DAC33_ATHR_MSB,
1030                               DAC33_THRREG(dac33->alarm_threshold));
1031                 break;
1032         case DAC33_FIFO_MODE7:
1033                 /*
1034                  * Configure the threshold levels, and leave 10 sample space
1035                  * at the bottom, and also at the top of the FIFO
1036                  */
1037                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1038                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1039                 break;
1040         default:
1041                 break;
1042         }
1043
1044         mutex_unlock(&dac33->mutex);
1045
1046         return 0;
1047 }
1048
1049 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1050 {
1051         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1052         struct snd_soc_device *socdev = rtd->socdev;
1053         struct snd_soc_codec *codec = socdev->card->codec;
1054         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1055         unsigned int period_size = substream->runtime->period_size;
1056         unsigned int rate = substream->runtime->rate;
1057         unsigned int nsample_limit;
1058
1059         /* In bypass mode we don't need to calculate */
1060         if (!dac33->fifo_mode)
1061                 return;
1062
1063         switch (dac33->fifo_mode) {
1064         case DAC33_FIFO_MODE1:
1065                 /* Number of samples under i2c latency */
1066                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1067                                                 dac33->mode1_latency);
1068                 if (dac33->auto_fifo_config) {
1069                         if (period_size <= dac33->alarm_threshold)
1070                                 /*
1071                                  * Configure nSamaple to number of periods,
1072                                  * which covers the latency requironment.
1073                                  */
1074                                 dac33->nsample = period_size *
1075                                        ((dac33->alarm_threshold / period_size) +
1076                                        (dac33->alarm_threshold % period_size ?
1077                                        1 : 0));
1078                         else
1079                                 dac33->nsample = period_size;
1080                 } else {
1081                         /* nSample time shall not be shorter than i2c latency */
1082                         dac33->nsample_min = dac33->alarm_threshold;
1083                         /*
1084                          * nSample should not be bigger than alsa buffer minus
1085                          * size of one period to avoid overruns
1086                          */
1087                         dac33->nsample_max = substream->runtime->buffer_size -
1088                                                 period_size;
1089                         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1090                                         dac33->alarm_threshold;
1091                         if (dac33->nsample_max > nsample_limit)
1092                                 dac33->nsample_max = nsample_limit;
1093
1094                         /* Correct the nSample if it is outside of the ranges */
1095                         if (dac33->nsample < dac33->nsample_min)
1096                                 dac33->nsample = dac33->nsample_min;
1097                         if (dac33->nsample > dac33->nsample_max)
1098                                 dac33->nsample = dac33->nsample_max;
1099                 }
1100
1101                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1102                                                       dac33->nsample);
1103                 dac33->t_stamp1 = 0;
1104                 dac33->t_stamp2 = 0;
1105                 break;
1106         case DAC33_FIFO_MODE7:
1107                 if (dac33->auto_fifo_config) {
1108                         dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1109                                         period_size,
1110                                         rate,
1111                                         dac33->burst_rate) + 9;
1112                         if (dac33->uthr > MODE7_UTHR)
1113                                 dac33->uthr = MODE7_UTHR;
1114                         if (dac33->uthr < (MODE7_LTHR + 10))
1115                                 dac33->uthr = (MODE7_LTHR + 10);
1116                 }
1117                 dac33->mode7_us_to_lthr =
1118                                 SAMPLES_TO_US(substream->runtime->rate,
1119                                         dac33->uthr - MODE7_LTHR + 1);
1120                 dac33->t_stamp1 = 0;
1121                 break;
1122         default:
1123                 break;
1124         }
1125
1126 }
1127
1128 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1129                              struct snd_soc_dai *dai)
1130 {
1131         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1132         struct snd_soc_device *socdev = rtd->socdev;
1133         struct snd_soc_codec *codec = socdev->card->codec;
1134         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1135         int ret = 0;
1136
1137         switch (cmd) {
1138         case SNDRV_PCM_TRIGGER_START:
1139         case SNDRV_PCM_TRIGGER_RESUME:
1140         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1141                 if (dac33->fifo_mode) {
1142                         dac33->state = DAC33_PREFILL;
1143                         queue_work(dac33->dac33_wq, &dac33->work);
1144                 }
1145                 break;
1146         case SNDRV_PCM_TRIGGER_STOP:
1147         case SNDRV_PCM_TRIGGER_SUSPEND:
1148         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1149                 if (dac33->fifo_mode) {
1150                         dac33->state = DAC33_FLUSH;
1151                         queue_work(dac33->dac33_wq, &dac33->work);
1152                 }
1153                 break;
1154         default:
1155                 ret = -EINVAL;
1156         }
1157
1158         return ret;
1159 }
1160
1161 static snd_pcm_sframes_t dac33_dai_delay(
1162                         struct snd_pcm_substream *substream,
1163                         struct snd_soc_dai *dai)
1164 {
1165         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1166         struct snd_soc_device *socdev = rtd->socdev;
1167         struct snd_soc_codec *codec = socdev->card->codec;
1168         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1169         unsigned long long t0, t1, t_now;
1170         unsigned int time_delta, uthr;
1171         int samples_out, samples_in, samples;
1172         snd_pcm_sframes_t delay = 0;
1173
1174         switch (dac33->fifo_mode) {
1175         case DAC33_FIFO_BYPASS:
1176                 break;
1177         case DAC33_FIFO_MODE1:
1178                 spin_lock(&dac33->lock);
1179                 t0 = dac33->t_stamp1;
1180                 t1 = dac33->t_stamp2;
1181                 spin_unlock(&dac33->lock);
1182                 t_now = ktime_to_us(ktime_get());
1183
1184                 /* We have not started to fill the FIFO yet, delay is 0 */
1185                 if (!t1)
1186                         goto out;
1187
1188                 if (t0 > t1) {
1189                         /*
1190                          * Phase 1:
1191                          * After Alarm threshold, and before nSample write
1192                          */
1193                         time_delta = t_now - t0;
1194                         samples_out = time_delta ? US_TO_SAMPLES(
1195                                                 substream->runtime->rate,
1196                                                 time_delta) : 0;
1197
1198                         if (likely(dac33->alarm_threshold > samples_out))
1199                                 delay = dac33->alarm_threshold - samples_out;
1200                         else
1201                                 delay = 0;
1202                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1203                         /*
1204                          * Phase 2:
1205                          * After nSample write (during burst operation)
1206                          */
1207                         time_delta = t_now - t0;
1208                         samples_out = time_delta ? US_TO_SAMPLES(
1209                                                 substream->runtime->rate,
1210                                                 time_delta) : 0;
1211
1212                         time_delta = t_now - t1;
1213                         samples_in = time_delta ? US_TO_SAMPLES(
1214                                                 dac33->burst_rate,
1215                                                 time_delta) : 0;
1216
1217                         samples = dac33->alarm_threshold;
1218                         samples += (samples_in - samples_out);
1219
1220                         if (likely(samples > 0))
1221                                 delay = samples;
1222                         else
1223                                 delay = 0;
1224                 } else {
1225                         /*
1226                          * Phase 3:
1227                          * After burst operation, before next alarm threshold
1228                          */
1229                         time_delta = t_now - t0;
1230                         samples_out = time_delta ? US_TO_SAMPLES(
1231                                                 substream->runtime->rate,
1232                                                 time_delta) : 0;
1233
1234                         samples_in = dac33->nsample;
1235                         samples = dac33->alarm_threshold;
1236                         samples += (samples_in - samples_out);
1237
1238                         if (likely(samples > 0))
1239                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1240                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1241                         else
1242                                 delay = 0;
1243                 }
1244                 break;
1245         case DAC33_FIFO_MODE7:
1246                 spin_lock(&dac33->lock);
1247                 t0 = dac33->t_stamp1;
1248                 uthr = dac33->uthr;
1249                 spin_unlock(&dac33->lock);
1250                 t_now = ktime_to_us(ktime_get());
1251
1252                 /* We have not started to fill the FIFO yet, delay is 0 */
1253                 if (!t0)
1254                         goto out;
1255
1256                 if (t_now <= t0) {
1257                         /*
1258                          * Either the timestamps are messed or equal. Report
1259                          * maximum delay
1260                          */
1261                         delay = uthr;
1262                         goto out;
1263                 }
1264
1265                 time_delta = t_now - t0;
1266                 if (time_delta <= dac33->mode7_us_to_lthr) {
1267                         /*
1268                         * Phase 1:
1269                         * After burst (draining phase)
1270                         */
1271                         samples_out = US_TO_SAMPLES(
1272                                         substream->runtime->rate,
1273                                         time_delta);
1274
1275                         if (likely(uthr > samples_out))
1276                                 delay = uthr - samples_out;
1277                         else
1278                                 delay = 0;
1279                 } else {
1280                         /*
1281                         * Phase 2:
1282                         * During burst operation
1283                         */
1284                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1285
1286                         samples_out = US_TO_SAMPLES(
1287                                         substream->runtime->rate,
1288                                         time_delta);
1289                         samples_in = US_TO_SAMPLES(
1290                                         dac33->burst_rate,
1291                                         time_delta);
1292                         delay = MODE7_LTHR + samples_in - samples_out;
1293
1294                         if (unlikely(delay > uthr))
1295                                 delay = uthr;
1296                 }
1297                 break;
1298         default:
1299                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1300                                                         dac33->fifo_mode);
1301                 break;
1302         }
1303 out:
1304         return delay;
1305 }
1306
1307 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1308                 int clk_id, unsigned int freq, int dir)
1309 {
1310         struct snd_soc_codec *codec = codec_dai->codec;
1311         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1312         u8 ioc_reg, asrcb_reg;
1313
1314         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1315         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1316         switch (clk_id) {
1317         case TLV320DAC33_MCLK:
1318                 ioc_reg |= DAC33_REFSEL;
1319                 asrcb_reg |= DAC33_SRCREFSEL;
1320                 break;
1321         case TLV320DAC33_SLEEPCLK:
1322                 ioc_reg &= ~DAC33_REFSEL;
1323                 asrcb_reg &= ~DAC33_SRCREFSEL;
1324                 break;
1325         default:
1326                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1327                 break;
1328         }
1329         dac33->refclk = freq;
1330
1331         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1332         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1333
1334         return 0;
1335 }
1336
1337 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1338                              unsigned int fmt)
1339 {
1340         struct snd_soc_codec *codec = codec_dai->codec;
1341         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1342         u8 aictrl_a, aictrl_b;
1343
1344         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1345         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1346         /* set master/slave audio interface */
1347         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1348         case SND_SOC_DAIFMT_CBM_CFM:
1349                 /* Codec Master */
1350                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1351                 break;
1352         case SND_SOC_DAIFMT_CBS_CFS:
1353                 /* Codec Slave */
1354                 if (dac33->fifo_mode) {
1355                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1356                         return -EINVAL;
1357                 } else
1358                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1359                 break;
1360         default:
1361                 return -EINVAL;
1362         }
1363
1364         aictrl_a &= ~DAC33_AFMT_MASK;
1365         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1366         case SND_SOC_DAIFMT_I2S:
1367                 aictrl_a |= DAC33_AFMT_I2S;
1368                 break;
1369         case SND_SOC_DAIFMT_DSP_A:
1370                 aictrl_a |= DAC33_AFMT_DSP;
1371                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1372                 aictrl_b |= DAC33_DATA_DELAY(0);
1373                 break;
1374         case SND_SOC_DAIFMT_RIGHT_J:
1375                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1376                 break;
1377         case SND_SOC_DAIFMT_LEFT_J:
1378                 aictrl_a |= DAC33_AFMT_LEFT_J;
1379                 break;
1380         default:
1381                 dev_err(codec->dev, "Unsupported format (%u)\n",
1382                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1383                 return -EINVAL;
1384         }
1385
1386         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1387         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1388
1389         return 0;
1390 }
1391
1392 static int dac33_soc_probe(struct platform_device *pdev)
1393 {
1394         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1395         struct snd_soc_codec *codec;
1396         struct tlv320dac33_priv *dac33;
1397         int ret = 0;
1398
1399         BUG_ON(!tlv320dac33_codec);
1400
1401         codec = tlv320dac33_codec;
1402         socdev->card->codec = codec;
1403         dac33 = snd_soc_codec_get_drvdata(codec);
1404
1405         /* register pcms */
1406         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1407         if (ret < 0) {
1408                 dev_err(codec->dev, "failed to create pcms\n");
1409                 goto pcm_err;
1410         }
1411
1412         snd_soc_add_controls(codec, dac33_snd_controls,
1413                              ARRAY_SIZE(dac33_snd_controls));
1414         /* Only add the FIFO controls, if we have valid IRQ number */
1415         if (dac33->irq >= 0) {
1416                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1417                                      ARRAY_SIZE(dac33_mode_snd_controls));
1418                 /* FIFO usage controls only, if autoio config is not selected */
1419                 if (!dac33->auto_fifo_config)
1420                         snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1421                                         ARRAY_SIZE(dac33_fifo_snd_controls));
1422         }
1423
1424         dac33_add_widgets(codec);
1425
1426         return 0;
1427
1428 pcm_err:
1429         dac33_hard_power(codec, 0);
1430         return ret;
1431 }
1432
1433 static int dac33_soc_remove(struct platform_device *pdev)
1434 {
1435         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1436         struct snd_soc_codec *codec = socdev->card->codec;
1437
1438         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1439
1440         snd_soc_free_pcms(socdev);
1441         snd_soc_dapm_free(socdev);
1442
1443         return 0;
1444 }
1445
1446 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1447 {
1448         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1449         struct snd_soc_codec *codec = socdev->card->codec;
1450
1451         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1452
1453         return 0;
1454 }
1455
1456 static int dac33_soc_resume(struct platform_device *pdev)
1457 {
1458         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1459         struct snd_soc_codec *codec = socdev->card->codec;
1460
1461         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1462
1463         return 0;
1464 }
1465
1466 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1467         .probe = dac33_soc_probe,
1468         .remove = dac33_soc_remove,
1469         .suspend = dac33_soc_suspend,
1470         .resume = dac33_soc_resume,
1471 };
1472 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1473
1474 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1475                          SNDRV_PCM_RATE_48000)
1476 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1477
1478 static struct snd_soc_dai_ops dac33_dai_ops = {
1479         .startup        = dac33_startup,
1480         .shutdown       = dac33_shutdown,
1481         .hw_params      = dac33_hw_params,
1482         .trigger        = dac33_pcm_trigger,
1483         .delay          = dac33_dai_delay,
1484         .set_sysclk     = dac33_set_dai_sysclk,
1485         .set_fmt        = dac33_set_dai_fmt,
1486 };
1487
1488 struct snd_soc_dai dac33_dai = {
1489         .name = "tlv320dac33",
1490         .playback = {
1491                 .stream_name = "Playback",
1492                 .channels_min = 2,
1493                 .channels_max = 2,
1494                 .rates = DAC33_RATES,
1495                 .formats = DAC33_FORMATS,},
1496         .ops = &dac33_dai_ops,
1497 };
1498 EXPORT_SYMBOL_GPL(dac33_dai);
1499
1500 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1501                                      const struct i2c_device_id *id)
1502 {
1503         struct tlv320dac33_platform_data *pdata;
1504         struct tlv320dac33_priv *dac33;
1505         struct snd_soc_codec *codec;
1506         int ret, i;
1507
1508         if (client->dev.platform_data == NULL) {
1509                 dev_err(&client->dev, "Platform data not set\n");
1510                 return -ENODEV;
1511         }
1512         pdata = client->dev.platform_data;
1513
1514         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1515         if (dac33 == NULL)
1516                 return -ENOMEM;
1517
1518         codec = &dac33->codec;
1519         snd_soc_codec_set_drvdata(codec, dac33);
1520         codec->control_data = client;
1521
1522         mutex_init(&codec->mutex);
1523         mutex_init(&dac33->mutex);
1524         spin_lock_init(&dac33->lock);
1525         INIT_LIST_HEAD(&codec->dapm_widgets);
1526         INIT_LIST_HEAD(&codec->dapm_paths);
1527
1528         codec->name = "tlv320dac33";
1529         codec->owner = THIS_MODULE;
1530         codec->read = dac33_read_reg_cache;
1531         codec->write = dac33_write_locked;
1532         codec->hw_write = (hw_write_t) i2c_master_send;
1533         codec->bias_level = SND_SOC_BIAS_OFF;
1534         codec->set_bias_level = dac33_set_bias_level;
1535         codec->idle_bias_off = 1;
1536         codec->dai = &dac33_dai;
1537         codec->num_dai = 1;
1538         codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1539         codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1540                                    GFP_KERNEL);
1541         if (codec->reg_cache == NULL) {
1542                 ret = -ENOMEM;
1543                 goto error_reg;
1544         }
1545
1546         i2c_set_clientdata(client, dac33);
1547
1548         dac33->power_gpio = pdata->power_gpio;
1549         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1550         /* Pre calculate the burst rate */
1551         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1552         dac33->keep_bclk = pdata->keep_bclk;
1553         dac33->auto_fifo_config = pdata->auto_fifo_config;
1554         dac33->mode1_latency = pdata->mode1_latency;
1555         if (!dac33->mode1_latency)
1556                 dac33->mode1_latency = 10000; /* 10ms */
1557         dac33->irq = client->irq;
1558         dac33->nsample = NSAMPLE_MAX;
1559         dac33->nsample_max = NSAMPLE_MAX;
1560         dac33->uthr = MODE7_UTHR;
1561         /* Disable FIFO use by default */
1562         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1563
1564         tlv320dac33_codec = codec;
1565
1566         codec->dev = &client->dev;
1567         dac33_dai.dev = codec->dev;
1568
1569         /* Check if the reset GPIO number is valid and request it */
1570         if (dac33->power_gpio >= 0) {
1571                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1572                 if (ret < 0) {
1573                         dev_err(codec->dev,
1574                                 "Failed to request reset GPIO (%d)\n",
1575                                 dac33->power_gpio);
1576                         snd_soc_unregister_dai(&dac33_dai);
1577                         snd_soc_unregister_codec(codec);
1578                         goto error_gpio;
1579                 }
1580                 gpio_direction_output(dac33->power_gpio, 0);
1581         }
1582
1583         /* Check if the IRQ number is valid and request it */
1584         if (dac33->irq >= 0) {
1585                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1586                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1587                                   codec->name, codec);
1588                 if (ret < 0) {
1589                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1590                                                 dac33->irq, ret);
1591                         dac33->irq = -1;
1592                 }
1593                 if (dac33->irq != -1) {
1594                         /* Setup work queue */
1595                         dac33->dac33_wq =
1596                                 create_singlethread_workqueue("tlv320dac33");
1597                         if (dac33->dac33_wq == NULL) {
1598                                 free_irq(dac33->irq, &dac33->codec);
1599                                 ret = -ENOMEM;
1600                                 goto error_wq;
1601                         }
1602
1603                         INIT_WORK(&dac33->work, dac33_work);
1604                 }
1605         }
1606
1607         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1608                 dac33->supplies[i].supply = dac33_supply_names[i];
1609
1610         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1611                                  dac33->supplies);
1612
1613         if (ret != 0) {
1614                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1615                 goto err_get;
1616         }
1617
1618         /* Read the tlv320dac33 ID registers */
1619         ret = dac33_hard_power(codec, 1);
1620         if (ret != 0) {
1621                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1622                 goto error_codec;
1623         }
1624         dac33_read_id(codec);
1625         dac33_hard_power(codec, 0);
1626
1627         ret = snd_soc_register_codec(codec);
1628         if (ret != 0) {
1629                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1630                 goto error_codec;
1631         }
1632
1633         ret = snd_soc_register_dai(&dac33_dai);
1634         if (ret != 0) {
1635                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1636                 snd_soc_unregister_codec(codec);
1637                 goto error_codec;
1638         }
1639
1640         return ret;
1641
1642 error_codec:
1643         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1644 err_get:
1645         if (dac33->irq >= 0) {
1646                 free_irq(dac33->irq, &dac33->codec);
1647                 destroy_workqueue(dac33->dac33_wq);
1648         }
1649 error_wq:
1650         if (dac33->power_gpio >= 0)
1651                 gpio_free(dac33->power_gpio);
1652 error_gpio:
1653         kfree(codec->reg_cache);
1654 error_reg:
1655         tlv320dac33_codec = NULL;
1656         kfree(dac33);
1657
1658         return ret;
1659 }
1660
1661 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1662 {
1663         struct tlv320dac33_priv *dac33;
1664
1665         dac33 = i2c_get_clientdata(client);
1666
1667         if (unlikely(dac33->chip_power))
1668                 dac33_hard_power(&dac33->codec, 0);
1669
1670         if (dac33->power_gpio >= 0)
1671                 gpio_free(dac33->power_gpio);
1672         if (dac33->irq >= 0)
1673                 free_irq(dac33->irq, &dac33->codec);
1674
1675         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1676
1677         destroy_workqueue(dac33->dac33_wq);
1678         snd_soc_unregister_dai(&dac33_dai);
1679         snd_soc_unregister_codec(&dac33->codec);
1680         kfree(dac33->codec.reg_cache);
1681         kfree(dac33);
1682         tlv320dac33_codec = NULL;
1683
1684         return 0;
1685 }
1686
1687 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1688         {
1689                 .name = "tlv320dac33",
1690                 .driver_data = 0,
1691         },
1692         { },
1693 };
1694
1695 static struct i2c_driver tlv320dac33_i2c_driver = {
1696         .driver = {
1697                 .name = "tlv320dac33",
1698                 .owner = THIS_MODULE,
1699         },
1700         .probe          = dac33_i2c_probe,
1701         .remove         = __devexit_p(dac33_i2c_remove),
1702         .id_table       = tlv320dac33_i2c_id,
1703 };
1704
1705 static int __init dac33_module_init(void)
1706 {
1707         int r;
1708         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1709         if (r < 0) {
1710                 printk(KERN_ERR "DAC33: driver registration failed\n");
1711                 return r;
1712         }
1713         return 0;
1714 }
1715 module_init(dac33_module_init);
1716
1717 static void __exit dac33_module_exit(void)
1718 {
1719         i2c_del_driver(&tlv320dac33_i2c_driver);
1720 }
1721 module_exit(dac33_module_exit);
1722
1723
1724 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1725 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1726 MODULE_LICENSE("GPL");