sound/soc/codecs/mc1n2/mcresctrl.h

   1 /****************************************************************************
   2  *
   3  *              Copyright(c) 2010 Yamaha Corporation. All rights reserved.
   4  *
   5  *              Module          : mcresctrl.h
   6  *
   7  *              Description     : MC Driver resource control header
   8  *
   9  *              Version         : 1.0.0         2010.09.01
  10  *
  11  ****************************************************************************/
  12
  13 #ifndef _MCRESCTRL_H_
  14 #define _MCRESCTRL_H_
  15
  16 #include "mcdevif.h"
  17 #include "mcpacking.h"
  18
  19 /* HW_ID */
  20 #define MCDRV_HWID_AA   (0x78)
  21 #define MCDRV_HWID_AB   (0x79)
  22
  23 #define MCDRV_BURST_WRITE_ENABLE        (0x01)
  24
  25 /*      eState setting  */
  26 typedef enum _MCDRV_STATE
  27 {
  28         eMCDRV_STATE_NOTINIT,
  29         eMCDRV_STATE_READY
  30 } MCDRV_STATE;
  31
  32 /*      volume setting  */
  33 #define MCDRV_LOGICAL_VOL_MUTE          (-24576)        /*      -96dB   */
  34 #define MCDRV_LOGICAL_MICGAIN_DEF       (3840)          /*      15dB    */
  35 #define MCDRV_LOGICAL_HPGAIN_DEF        (0)                     /*      0dB             */
  36
  37 #define MCDRV_VOLUPDATE_ALL                     (0xFFFFFFFFUL)
  38 #define MCDRV_VOLUPDATE_ANAOUT_ALL      (0x00000001UL)
  39
  40 #define MCDRV_REG_MUTE  (0x00)
  41
  42 /*      DAC source setting      */
  43 typedef enum _MCDRV_DAC_CH
  44 {
  45         eMCDRV_DAC_MASTER       = 0,
  46         eMCDRV_DAC_VOICE
  47 } MCDRV_DAC_CH;
  48
  49 /*      DIO port setting        */
  50 typedef enum _MCDRV_DIO_PORT_NO
  51 {
  52         eMCDRV_DIO_0    = 0,
  53         eMCDRV_DIO_1,
  54         eMCDRV_DIO_2
  55 } MCDRV_DIO_PORT_NO;
  56
  57 /*      Path source setting     */
  58 typedef enum _MCDRV_SRC_TYPE
  59 {
  60         eMCDRV_SRC_NONE                 = (0),
  61         eMCDRV_SRC_MIC1                 = (1<<0),
  62         eMCDRV_SRC_MIC2                 = (1<<1),
  63         eMCDRV_SRC_MIC3                 = (1<<2),
  64         eMCDRV_SRC_LINE1_L              = (1<<3),
  65         eMCDRV_SRC_LINE1_R              = (1<<4),
  66         eMCDRV_SRC_LINE1_M              = (1<<5),
  67         eMCDRV_SRC_LINE2_L              = (1<<6),
  68         eMCDRV_SRC_LINE2_R              = (1<<7),
  69         eMCDRV_SRC_LINE2_M              = (1<<8),
  70         eMCDRV_SRC_DIR0                 = (1<<9),
  71         eMCDRV_SRC_DIR1                 = (1<<10),
  72         eMCDRV_SRC_DIR2                 = (1<<11),
  73         eMCDRV_SRC_DTMF                 = (1<<12),
  74         eMCDRV_SRC_PDM                  = (1<<13),
  75         eMCDRV_SRC_ADC0                 = (1<<14),
  76         eMCDRV_SRC_ADC1                 = (1<<15),
  77         eMCDRV_SRC_DAC_L                = (1<<16),
  78         eMCDRV_SRC_DAC_R                = (1<<17),
  79         eMCDRV_SRC_DAC_M                = (1<<18),
  80         eMCDRV_SRC_AE                   = (1<<19),
  81         eMCDRV_SRC_CDSP                 = (1<<20),
  82         eMCDRV_SRC_MIX                  = (1<<21),
  83         eMCDRV_SRC_DIR2_DIRECT  = (1<<22),
  84         eMCDRV_SRC_CDSP_DIRECT  = (1<<23)
  85 } MCDRV_SRC_TYPE;
  86
  87 /*      Path destination setting        */
  88 typedef enum _MCDRV_DST_CH
  89 {
  90         eMCDRV_DST_CH0  = 0,
  91         eMCDRV_DST_CH1
  92 } MCDRV_DST_CH;
  93 typedef enum _MCDRV_DST_TYPE
  94 {
  95         eMCDRV_DST_HP   = 0,
  96         eMCDRV_DST_SP,
  97         eMCDRV_DST_RCV,
  98         eMCDRV_DST_LOUT1,
  99         eMCDRV_DST_LOUT2,
 100         eMCDRV_DST_PEAK,
 101         eMCDRV_DST_DIT0,
 102         eMCDRV_DST_DIT1,
 103         eMCDRV_DST_DIT2,
 104         eMCDRV_DST_DAC,
 105         eMCDRV_DST_AE,
 106         eMCDRV_DST_CDSP,
 107         eMCDRV_DST_ADC0,
 108         eMCDRV_DST_ADC1,
 109         eMCDRV_DST_MIX,
 110         eMCDRV_DST_BIAS
 111 } MCDRV_DST_TYPE;
 112
 113 /*      Register accsess availability   */
 114 typedef enum _MCDRV_REG_ACCSESS
 115 {
 116         eMCDRV_ACCESS_DENY      = 0,
 117         eMCDRV_READ_ONLY        = 0x01,
 118         eMCDRV_WRITE_ONLY       = 0x02,
 119         eMCDRV_READ_WRITE       = eMCDRV_READ_ONLY | eMCDRV_WRITE_ONLY
 120 } MCDRV_REG_ACCSESS;
 121
 122
 123 /*      UpdateReg parameter     */
 124 typedef enum _MCDRV_UPDATE_MODE
 125 {
 126         eMCDRV_UPDATE_NORMAL,
 127         eMCDRV_UPDATE_FORCE,
 128         eMCDRV_UPDATE_DUMMY
 129 } MCDRV_UPDATE_MODE;
 130
 131 /*      ePacketBufAlloc setting */
 132 typedef enum _MCDRV_PACKETBUF_ALLOC
 133 {
 134         eMCDRV_PACKETBUF_FREE,
 135         eMCDRV_PACKETBUF_ALLOCATED
 136 } MCDRV_PACKETBUF_ALLOC;
 137
 138 /* power management sequence mode */
 139 typedef enum _MCDRV_PMODE
 140 {
 141         eMCDRV_APM_ON,
 142         eMCDRV_APM_OFF
 143 } MCDRV_PMODE;
 144
 145 #define MCDRV_A_REG_NUM                 (64)
 146 #define MCDRV_B_BASE_REG_NUM    (32)
 147 #define MCDRV_B_MIXER_REG_NUM   (218)
 148 #define MCDRV_B_AE_REG_NUM              (255)
 149 #define MCDRV_B_CDSP_REG_NUM    (130)
 150 #define MCDRV_B_CODEC_REG_NUM   (128)
 151 #define MCDRV_B_ANA_REG_NUM             (128)
 152
 153 /* control packet for serial host interface */
 154 #define MCDRV_MAX_CTRL_DATA_NUM (1024)
 155 typedef struct
 156 {
 157         UINT8   abData[MCDRV_MAX_CTRL_DATA_NUM];
 158         UINT16  wDataNum;
 159 } MCDRV_SERIAL_CTRL_PACKET;
 160
 161 /*      global information      */
 162 typedef struct
 163 {
 164         UINT8                                           bHwId;
 165         MCDRV_PACKETBUF_ALLOC           ePacketBufAlloc;
 166         UINT8                                           abRegValA[MCDRV_A_REG_NUM];
 167         UINT8                                           abRegValB_BASE[MCDRV_B_BASE_REG_NUM];
 168         UINT8                                           abRegValB_MIXER[MCDRV_B_MIXER_REG_NUM];
 169         UINT8                                           abRegValB_AE[MCDRV_B_AE_REG_NUM];
 170         UINT8                                           abRegValB_CDSP[MCDRV_B_CDSP_REG_NUM];
 171         UINT8                                           abRegValB_CODEC[MCDRV_B_CODEC_REG_NUM];
 172         UINT8                                           abRegValB_ANA[MCDRV_B_ANA_REG_NUM];
 173
 174         MCDRV_INIT_INFO                         sInitInfo;
 175         MCDRV_PATH_INFO                         sPathInfo;
 176         MCDRV_PATH_INFO                         sPathInfoVirtual;
 177         MCDRV_VOL_INFO                          sVolInfo;
 178         MCDRV_DIO_INFO                          sDioInfo;
 179         MCDRV_DAC_INFO                          sDacInfo;
 180         MCDRV_ADC_INFO                          sAdcInfo;
 181         MCDRV_SP_INFO                           sSpInfo;
 182         MCDRV_DNG_INFO                          sDngInfo;
 183         MCDRV_AE_INFO                           sAeInfo;
 184         MCDRV_PDM_INFO                          sPdmInfo;
 185         MCDRV_GP_MODE                           sGpMode;
 186         UINT8                                           abGpMask[GPIO_PAD_NUM];
 187         MCDRV_SYSEQ_INFO                        sSysEq;
 188         MCDRV_CLKSW_INFO                        sClockSwitch;
 189
 190         MCDRV_SERIAL_CTRL_PACKET        sCtrlPacket;
 191         UINT16                                          wCurSlaveAddress;
 192         UINT16                                          wCurRegType;
 193         UINT16                                          wCurRegAddress;
 194         UINT16                                          wDataContinueCount;
 195         UINT16                                          wPrevAddressIndex;
 196
 197         MCDRV_PMODE                                     eAPMode;
 198 } MCDRV_GLOBAL_INFO;
 199
 200
 201
 202 SINT32                  McResCtrl_SetHwId                               (UINT8 bHwId);
 203 UINT8                   McResCtrl_GetHwId                               (void);
 204 void                    McResCtrl_Init                                  (const MCDRV_INIT_INFO* psInitInfo);
 205 void                    McResCtrl_UpdateState                   (MCDRV_STATE eState);
 206 MCDRV_STATE             McResCtrl_GetState                              (void);
 207 UINT8                   McResCtrl_GetRegVal                             (UINT16 wRegType, UINT16 wRegAddr);
 208 void                    McResCtrl_SetRegVal                             (UINT16 wRegType, UINT16 wRegAddr, UINT8 bRegVal);
 209
 210 void                    McResCtrl_GetInitInfo                   (MCDRV_INIT_INFO* psInitInfo);
 211 void                    McResCtrl_SetClockInfo                  (const MCDRV_CLOCK_INFO* psClockInfo);
 212 void                    McResCtrl_SetPathInfo                   (const MCDRV_PATH_INFO* psPathInfo);
 213 void                    McResCtrl_GetPathInfo                   (MCDRV_PATH_INFO* psPathInfo);
 214 void                    McResCtrl_GetPathInfoVirtual    (MCDRV_PATH_INFO* psPathInfo);
 215 void                    McResCtrl_SetDioInfo                    (const MCDRV_DIO_INFO* psDioInfo, UINT32 dUpdateInfo);
 216 void                    McResCtrl_GetDioInfo                    (MCDRV_DIO_INFO* psDioInfo);
 217 void                    McResCtrl_SetVolInfo                    (const MCDRV_VOL_INFO* psVolInfo);
 218 void                    McResCtrl_GetVolInfo                    (MCDRV_VOL_INFO* psVolInfo);
 219 void                    McResCtrl_SetDacInfo                    (const MCDRV_DAC_INFO* psDacInfo, UINT32 dUpdateInfo);
 220 void                    McResCtrl_GetDacInfo                    (MCDRV_DAC_INFO* psDacInfo);
 221 void                    McResCtrl_SetAdcInfo                    (const MCDRV_ADC_INFO* psAdcInfo, UINT32 dUpdateInfo);
 222 void                    McResCtrl_GetAdcInfo                    (MCDRV_ADC_INFO* psAdcInfo);
 223 void                    McResCtrl_SetSpInfo                             (const MCDRV_SP_INFO* psSpInfo);
 224 void                    McResCtrl_GetSpInfo                             (MCDRV_SP_INFO* psSpInfo);
 225 void                    McResCtrl_SetDngInfo                    (const MCDRV_DNG_INFO* psDngInfo, UINT32 dUpdateInfo);
 226 void                    McResCtrl_GetDngInfo                    (MCDRV_DNG_INFO* psDngInfo);
 227 void                    McResCtrl_SetAeInfo                             (const MCDRV_AE_INFO* psAeInfo, UINT32 dUpdateInfo);
 228 void                    McResCtrl_GetAeInfo                             (MCDRV_AE_INFO* psAeInfo);
 229 void                    McResCtrl_SetPdmInfo                    (const MCDRV_PDM_INFO* psPdmInfo, UINT32 dUpdateInfo);
 230 void                    McResCtrl_GetPdmInfo                    (MCDRV_PDM_INFO* psPdmInfo);
 231 void                    McResCtrl_SetGPMode                             (const MCDRV_GP_MODE* psGpMode);
 232 void                    McResCtrl_GetGPMode                             (MCDRV_GP_MODE* psGpMode);
 233 void                    McResCtrl_SetGPMask                             (UINT8 bMask, UINT32 dPadNo);
 234 void                    McResCtrl_GetGPMask                             (UINT8* pabMask);
 235 void                    McResCtrl_GetSysEq                              (MCDRV_SYSEQ_INFO* psSysEq);
 236 void                    McResCtrl_SetSysEq                              (const MCDRV_SYSEQ_INFO* psSysEq, UINT32 dUpdateInfo);
 237 void                    McResCtrl_GetClockSwitch                (MCDRV_CLKSW_INFO* psClockInfo);
 238 void                    McResCtrl_SetClockSwitch                (const MCDRV_CLKSW_INFO* psClockInfo);
 239
 240 void                    McResCtrl_GetVolReg                             (MCDRV_VOL_INFO* psVolInfo);
 241 void                    McResCtrl_GetPowerInfo                  (MCDRV_POWER_INFO* psPowerInfo);
 242 void                    McResCtrl_GetPowerInfoRegAccess (const MCDRV_REG_INFO* psRegInfo, MCDRV_POWER_INFO* psPowerInfo);
 243 void                    McResCtrl_GetCurPowerInfo               (MCDRV_POWER_INFO* psPowerInfo);
 244 MCDRV_SRC_TYPE  McResCtrl_GetDACSource                  (MCDRV_DAC_CH eCh);
 245 MCDRV_SRC_TYPE  McResCtrl_GetDITSource                  (MCDRV_DIO_PORT_NO ePort);
 246 MCDRV_SRC_TYPE  McResCtrl_GetAESource                   (void);
 247 UINT8                   McResCtrl_IsSrcUsed                             (MCDRV_SRC_TYPE ePathSrc);
 248 UINT8                   McResCtrl_IsDstUsed                             (MCDRV_DST_TYPE eType, MCDRV_DST_CH eCh);
 249 MCDRV_REG_ACCSESS       McResCtrl_GetRegAccess          (const MCDRV_REG_INFO* psRegInfo);
 250
 251 MCDRV_PMODE             McResCtrl_GetAPMode                             (void);
 252
 253 MCDRV_PACKET*   McResCtrl_AllocPacketBuf                (void);
 254 void                    McResCtrl_ReleasePacketBuf              (void);
 255
 256 void                    McResCtrl_InitRegUpdate                 (void);
 257 void                    McResCtrl_AddRegUpdate                  (UINT16 wRegType, UINT16 wAddress, UINT8 bData, MCDRV_UPDATE_MODE eUpdateMode);
 258 void                    McResCtrl_ExecuteRegUpdate              (void);
 259 SINT32                  McResCtrl_WaitEvent                             (UINT32 dEvent, UINT32 dParam);
 260
 261
 262
 263 #endif /* _MCRESCTRL_H_ */