1 /****************************************************************************
3 * Copyright(c) 2010 Yamaha Corporation. All rights reserved.
7 * Description : MC Device Definitions
9 * Version : 1.0.0 2010.07.05
11 ****************************************************************************/
16 /* Register Definition
21 MCI_xxx_DEF : Default setting of registers
22 MCB_xxx : Miscelleneous bit definition
28 #define MCB_RST (0x01)
29 #define MCI_RST_DEF (MCB_RST)
31 #define MCI_BASE_ADR (1)
32 #define MCI_BASE_WINDOW (2)
35 #define MCI_HW_ID_DEF (0x79)
37 #define MCI_ANA_ADR (12)
38 #define MCI_ANA_WINDOW (13)
40 #define MCI_CD_ADR (14)
41 #define MCI_CD_WINDOW (15)
43 #define MCI_MIX_ADR (16)
44 #define MCI_MIX_WINDOW (17)
46 #define MCI_AE_ADR (18)
47 #define MCI_AE_WINDOW (19)
49 #define MCI_BDSP_ST (20)
50 #define MCB_EQ5ON (0x80)
51 #define MCB_DRCON (0x40)
52 #define MCB_EQ3ON (0x20)
53 #define MCB_DBEXON (0x08)
54 #define MCB_BDSP_ST (0x01)
56 #define MCI_BDSP_RST (21)
57 #define MCB_TRAM_RST (0x02)
58 #define MCB_BDSP_RST (0x01)
60 #define MCI_BDSP_ADR (22)
61 #define MCI_BDSP_WINDOW (23)
63 #define MCI_CDSP_ADR (24)
64 #define MCI_CDSP_WINDOW (25)
68 #define MCB_RSTB (0x10)
69 #define MCI_RSTB_DEF (MCB_RSTB)
71 #define MCI_PWM_DIGITAL (1)
72 #define MCB_PWM_DP2 (0x04)
73 #define MCB_PWM_DP1 (0x02)
74 #define MCI_PWM_DIGITAL_DEF (MCB_PWM_DP2 | MCB_PWM_DP1)
76 #define MCI_PWM_DIGITAL_1 (3)
77 #define MCB_PWM_DPPDM (0x10)
78 #define MCB_PWM_DPDI2 (0x08)
79 #define MCB_PWM_DPDI1 (0x04)
80 #define MCB_PWM_DPDI0 (0x02)
81 #define MCB_PWM_DPB (0x01)
82 #define MCI_PWM_DIGITAL_1_DEF (MCB_PWM_DPPDM | MCB_PWM_DPDI2 | MCB_PWM_DPDI1 | MCB_PWM_DPDI0 | MCB_PWM_DPB)
84 #define MCI_PWM_DIGITAL_CDSP (4)
85 #define MCB_PWM_DPCDSP (0x00)
86 #define MCI_PWM_DIGITAL_CDSP_DEF (MCB_PWM_DPCDSP)
88 #define MCI_PWM_DIGITAL_BDSP (6)
89 #define MCI_PWM_DIGITAL_BDSP_DEF (MCB_PWM_DPBDSP)
90 #define MCB_PWM_DPBDSP (0x01)
92 #define MCI_SD_MSK (9)
93 #define MCB_SDIN_MSK2 (0x80)
94 #define MCB_SDO_DDR2 (0x10)
95 #define MCB_SDIN_MSK1 (0x08)
96 #define MCB_SDO_DDR1 (0x01)
97 #define MCI_SD_MSK_DEF (MCB_SDIN_MSK2 | MCB_SDIN_MSK1)
99 #define MCI_SD_MSK_1 (10)
100 #define MCB_SDIN_MSK0 (0x80)
101 #define MCB_SDO_DDR0 (0x10)
102 #define MCI_SD_MSK_1_DEF (MCB_SDIN_MSK0)
104 #define MCI_BCLK_MSK (11)
105 #define MCB_BCLK_MSK2 (0x80)
106 #define MCB_BCLK_DDR2 (0x40)
107 #define MCB_LRCK_MSK2 (0x20)
108 #define MCB_LRCK_DDR2 (0x10)
109 #define MCB_BCLK_MSK1 (0x08)
110 #define MCB_BCLK_DDR1 (0x04)
111 #define MCB_LRCK_MSK1 (0x02)
112 #define MCB_LRCK_DDR1 (0x01)
113 #define MCI_BCLK_MSK_DEF (MCB_BCLK_MSK2 | MCB_LRCK_MSK2 | MCB_BCLK_MSK1 | MCB_LRCK_MSK1)
115 #define MCI_BCLK_MSK_1 (12)
116 #define MCB_BCLK_MSK0 (0x80)
117 #define MCB_BCLK_DDR0 (0x40)
118 #define MCB_LRCK_MSK0 (0x20)
119 #define MCB_LRCK_DDR0 (0x10)
120 #define MCB_PCMOUT_HIZ2 (0x08)
121 #define MCB_PCMOUT_HIZ1 (0x04)
122 #define MCB_PCMOUT_HIZ0 (0x02)
123 #define MCB_ROUTER_MS (0x01)
124 #define MCI_BCLK_MSK_1_DEF (MCB_BCLK_MSK0 | MCB_LRCK_MSK0)
126 #define MCI_BCKP (13)
127 #define MCB_DI2_BCKP (0x04)
128 #define MCB_DI1_BCKP (0x02)
129 #define MCB_DI0_BCKP (0x01)
130 #define MCI_BCKP_DEF (0)
132 #define MCI_BYPASS (21)
133 #define MCB_LOCK1 (0x80)
134 #define MCB_LOCK0 (0x40)
135 #define MCB_BYPASS1 (0x02)
136 #define MCB_BYPASS0 (0x01)
138 #define MCI_EPA_IRQ (22)
139 #define MCB_EPA2_IRQ (0x04)
140 #define MCB_EPA1_IRQ (0x02)
141 #define MCB_EPA0_IRQ (0x01)
143 #define MCI_PA_FLG (23)
144 #define MCB_PA2_FLAG (0x04)
145 #define MCB_PA1_FLAG (0x02)
146 #define MCB_PA0_FLAG (0x01)
148 #define MCI_PA_MSK (26)
149 #define MCB_PA1_MSK (0x80)
150 #define MCB_PA1_DDR (0x40)
151 #define MCB_PA0_MSK (0x08)
152 #define MCB_PA0_DDR (0x04)
153 #define MCI_PA_MSK_DEF (MCB_PA1_MSK | MCB_PA0_MSK)
155 #define MCI_PA_HOST (28)
156 #define MCI_PA_HOST_1 (29)
158 #define MCI_PA_OUT (30)
159 #define MCB_PA_OUT (0x01)
161 #define MCI_PA_SCU_PA (31)
162 #define MCB_PA_SCU_PA0 (0x01)
163 #define MCB_PA_SCU_PA1 (0x02)
166 #define MCI_DIT_INVFLAGL (0)
167 #define MCB_DIT0_INVFLAGL (0x20)
168 #define MCB_DIT1_INVFLAGL (0x10)
169 #define MCB_DIT2_INVFLAGL (0x08)
171 #define MCI_DIT_INVFLAGR (1)
172 #define MCB_DIT0_INVFLAGR (0x20)
173 #define MCB_DIT1_INVFLAGR (0x10)
174 #define MCB_DIT2_INVFLAGR (0x08)
176 #define MCI_DIR_VFLAGL (2)
177 #define MCB_PDM0_VFLAGL (0x80)
178 #define MCB_DIR0_VFLAGL (0x20)
179 #define MCB_DIR1_VFLAGL (0x10)
180 #define MCB_DIR2_VFLAGL (0x08)
182 #define MCI_DIR_VFLAGR (3)
183 #define MCB_PDM0_VFLAGR (0x80)
184 #define MCB_DIR0_VFLAGR (0x20)
185 #define MCB_DIR1_VFLAGR (0x10)
186 #define MCB_DIR2_VFLAGR (0x08)
188 #define MCI_AD_VFLAGL (4)
189 #define MCB_ADC_VFLAGL (0x80)
190 #define MCB_AENG6_VFLAGL (0x20)
192 #define MCI_AD_VFLAGR (5)
193 #define MCB_ADC_VFLAGR (0x80)
194 #define MCB_AENG6_VFLAGR (0x20)
196 #define MCI_AFLAGL (6)
197 #define MCB_ADC_AFLAGL (0x40)
198 #define MCB_DIR0_AFLAGL (0x20)
199 #define MCB_DIR1_AFLAGL (0x10)
200 #define MCB_DIR2_AFLAGL (0x04)
202 #define MCI_AFLAGR (7)
203 #define MCB_ADC_AFLAGR (0x40)
204 #define MCB_DIR0_AFLAGR (0x20)
205 #define MCB_DIR1_AFLAGR (0x10)
206 #define MCB_DIR2_AFLAGR (0x04)
208 #define MCI_DAC_INS_FLAG (8)
209 #define MCB_DAC_INS_FLAG (0x80)
211 #define MCI_INS_FLAG (9)
212 #define MCB_ADC_INS_FLAG (0x40)
213 #define MCB_DIR0_INS_FLAG (0x20)
214 #define MCB_DIR1_INS_FLAG (0x10)
215 #define MCB_DIR2_INS_FLAG (0x04)
217 #define MCI_DAC_FLAGL (10)
218 #define MCB_ST_FLAGL (0x80)
219 #define MCB_MASTER_OFLAGL (0x40)
220 #define MCB_VOICE_FLAGL (0x10)
221 #define MCB_DAC_FLAGL (0x02)
223 #define MCI_DAC_FLAGR (11)
224 #define MCB_ST_FLAGR (0x80)
225 #define MCB_MASTER_OFLAGR (0x40)
226 #define MCB_VOICE_FLAGR (0x10)
227 #define MCB_DAC_FLAGR (0x02)
229 #define MCI_DIT0_INVOLL (12)
230 #define MCB_DIT0_INLAT (0x80)
231 #define MCB_DIT0_INVOLL (0x7F)
233 #define MCI_DIT0_INVOLR (13)
234 #define MCB_DIT0_INVOLR (0x7F)
236 #define MCI_DIT1_INVOLL (14)
237 #define MCB_DIT1_INLAT (0x80)
238 #define MCB_DIT1_INVOLL (0x7F)
240 #define MCI_DIT1_INVOLR (15)
241 #define MCB_DIT1_INVOLR (0x7F)
243 #define MCI_DIT2_INVOLL (16)
244 #define MCB_DIT2_INLAT (0x80)
245 #define MCB_DIT2_INVOLL (0x7F)
247 #define MCI_DIT2_INVOLR (17)
248 #define MCB_DIT2_INVOLR (0x7F)
250 #define MCI_ESRC0_INVOLL (16)
251 #define MCI_ESRC0_INVOLR (17)
253 #define MCI_PDM0_VOLL (24)
254 #define MCB_PDM0_LAT (0x80)
255 #define MCB_PDM0_VOLL (0x7F)
257 #define MCI_PDM0_VOLR (25)
258 #define MCB_PDM0_VOLR (0x7F)
260 #define MCI_DIR0_VOLL (28)
261 #define MCB_DIR0_LAT (0x80)
262 #define MCB_DIR0_VOLL (0x7F)
264 #define MCI_DIR0_VOLR (29)
265 #define MCB_DIR0_VOLR (0x7F)
267 #define MCI_DIR1_VOLL (30)
268 #define MCB_DIR1_LAT (0x80)
269 #define MCB_DIR1_VOLL (0x7F)
271 #define MCI_DIR1_VOLR (31)
272 #define MCB_DIR1_VOLR (0x7F)
274 #define MCI_DIR2_VOLL (32)
275 #define MCB_DIR2_LAT (0x80)
276 #define MCB_DIR2_VOLL (0x7F)
278 #define MCI_DIR2_VOLR (33)
279 #define MCB_DIR2_VOLR (0x7F)
281 #define MCI_ADC1_VOLL (38?)
282 #define MCB_ADC1_LAT (0x80)
283 #define MCB_ADC1_VOLL (0x7F)
285 #define MCI_ADC1_VOLR (39?)
286 #define MCB_ADC1_VOLR (0x7F)
288 #define MCI_ADC_VOLL (40)
289 #define MCB_ADC_LAT (0x80)
290 #define MCB_ADC_VOLL (0x7F)
292 #define MCI_ADC_VOLR (41)
293 #define MCB_ADC_VOLR (0x7F)
295 #define MCI_DTMFB_VOLL (42)
296 #define MCI_DTMFB_VOLR (43)
298 #define MCI_AENG6_VOLL (44)
299 #define MCB_AENG6_LAT (0x80)
300 #define MCB_AENG6_VOLL (0x7F)
302 #define MCI_AENG6_VOLR (45)
303 #define MCB_AENG6_VOLR (0x7F)
305 #define MCI_DIT_ININTP (50)
306 #define MCB_DIT0_ININTP (0x20)
307 #define MCB_DIT1_ININTP (0x10)
308 #define MCB_DIT2_ININTP (0x08)
309 #define MCI_DIT_ININTP_DEF (MCB_DIT0_ININTP | MCB_DIT1_ININTP | MCB_DIT2_ININTP)
311 #define MCI_DIR_INTP (51)
312 #define MCB_PDM0_INTP (0x80)
313 #define MCB_DIR0_INTP (0x20)
314 #define MCB_DIR1_INTP (0x10)
315 #define MCB_DIR2_INTP (0x08)
316 #define MCB_ADC2_INTP (0x01)
317 #define MCI_DIR_INTP_DEF (MCB_PDM0_INTP | MCB_DIR0_INTP | MCB_DIR1_INTP | MCB_DIR2_INTP)
319 #define MCI_ADC_INTP (52)
320 #define MCB_ADC_INTP (0x80)
321 #define MCB_AENG6_INTP (0x20)
322 #define MCI_ADC_INTP_DEF (MCB_ADC_INTP | MCB_AENG6_INTP)
324 #define MCI_ADC_ATTL (54)
325 #define MCB_ADC_ALAT (0x80)
326 #define MCB_ADC_ATTL (0x7F)
328 #define MCI_ADC_ATTR (55)
329 #define MCB_ADC_ATTR (0x7F)
331 #define MCI_DIR0_ATTL (56)
332 #define MCB_DIR0_ALAT (0x80)
333 #define MCB_DIR0_ATTL (0x7F)
335 #define MCI_DIR0_ATTR (57)
336 #define MCB_DIR0_ATTR (0x7F)
338 #define MCI_DIR1_ATTL (58)
339 #define MCB_DIR1_ALAT (0x80)
340 #define MCB_DIR1_ATTL (0x7F)
342 #define MCI_DIR1_ATTR (59)
343 #define MCB_DIR1_ATTR (0x7F)
345 #define MCI_ADC2_ATTL (60)
346 #define MCI_ADC2_ATTR (61)
348 #define MCI_DIR2_ATTL (62)
349 #define MCB_DIR2_ALAT (0x80)
350 #define MCB_DIR2_ATTL (0x7F)
352 #define MCI_DIR2_ATTR (63)
353 #define MCB_DIR2_ATTR (0x7F)
355 #define MCI_AINTP (72)
356 #define MCB_ADC_AINTP (0x40)
357 #define MCB_DIR0_AINTP (0x20)
358 #define MCB_DIR1_AINTP (0x10)
359 #define MCB_DIR2_AINTP (0x04)
360 #define MCI_AINTP_DEF (MCB_ADC_AINTP | MCB_DIR0_AINTP | MCB_DIR1_AINTP | MCB_DIR2_AINTP)
362 #define MCI_DAC_INS (74)
363 #define MCB_DAC_INS (0x80)
366 #define MCB_ADC_INS (0x40)
367 #define MCB_DIR0_INS (0x20)
368 #define MCB_DIR1_INS (0x10)
369 #define MCB_DIR2_INS (0x04)
371 #define MCI_IINTP (76)
372 #define MCB_DAC_IINTP (0x80)
373 #define MCB_ADC_IINTP (0x40)
374 #define MCB_DIR0_IINTP (0x20)
375 #define MCB_DIR1_IINTP (0x10)
376 #define MCB_DIR2_IINTP (0x04)
377 #define MCI_IINTP_DEF (MCB_DAC_IINTP | MCB_ADC_IINTP | MCB_DIR0_IINTP | MCB_DIR1_IINTP | MCB_DIR2_IINTP)
379 #define MCI_ST_VOLL (77)
380 #define MCB_ST_LAT (0x80)
381 #define MCB_ST_VOLL (0x7F)
383 #define MCI_ST_VOLR (78)
384 #define MCB_ST_VOLR (0x7F)
386 #define MCI_MASTER_OUTL (79)
387 #define MCB_MASTER_OLAT (0x80)
388 #define MCB_MASTER_OUTL (0x7F)
390 #define MCI_MASTER_OUTR (80)
391 #define MCB_MASTER_OUTR (0x7F)
393 #define MCI_VOICE_ATTL (83)
394 #define MCB_VOICE_LAT (0x80)
395 #define MCB_VOICE_ATTL (0x7F)
397 #define MCI_VOICE_ATTR (84)
398 #define MCB_VOICE_ATTR (0x7F)
400 #define MCI_DTMF_ATTL (85)
401 #define MCI_DTMF_ATTR (86)
403 #define MCI_DAC_ATTL (89)
404 #define MCB_DAC_LAT (0x80)
405 #define MCB_DAC_ATTL (0x7F)
407 #define MCI_DAC_ATTR (90)
408 #define MCB_DAC_ATTR (0x7F)
410 #define MCI_DAC_INTP (93)
411 #define MCB_ST_INTP (0x80)
412 #define MCB_MASTER_OINTP (0x40)
413 #define MCB_VOICE_INTP (0x10)
414 /*#define MCB_DTMF_INTP (0x08)*/
415 #define MCB_DAC_INTP (0x02)
416 #define MCI_DAC_INTP_DEF (MCB_ST_INTP | MCB_MASTER_OINTP | MCB_VOICE_INTP | MCB_DAC_INTP)
418 #define MCI_SOURCE (110)
419 #define MCB_DAC_SOURCE_AD (0x10)
420 #define MCB_DAC_SOURCE_DIR2 (0x20)
421 #define MCB_DAC_SOURCE_DIR0 (0x30)
422 #define MCB_DAC_SOURCE_DIR1 (0x40)
423 #define MCB_DAC_SOURCE_MIX (0x70)
424 #define MCB_VOICE_SOURCE_AD (0x01)
425 #define MCB_VOICE_SOURCE_DIR2 (0x02)
426 #define MCB_VOICE_SOURCE_DIR0 (0x03)
427 #define MCB_VOICE_SOURCE_DIR1 (0x04)
428 #define MCB_VOICE_SOURCE_MIX (0x07)
430 #define MCI_SWP (111)
432 #define MCI_SRC_SOURCE (112)
433 #define MCB_DIT0_SOURCE_AD (0x10)
434 #define MCB_DIT0_SOURCE_DIR2 (0x20)
435 #define MCB_DIT0_SOURCE_DIR0 (0x30)
436 #define MCB_DIT0_SOURCE_DIR1 (0x40)
437 #define MCB_DIT0_SOURCE_MIX (0x70)
438 #define MCB_DIT1_SOURCE_AD (0x01)
439 #define MCB_DIT1_SOURCE_DIR2 (0x02)
440 #define MCB_DIT1_SOURCE_DIR0 (0x03)
441 #define MCB_DIT1_SOURCE_DIR1 (0x04)
442 #define MCB_DIT1_SOURCE_MIX (0x07)
444 #define MCI_SRC_SOURCE_1 (113)
445 #define MCB_AE_SOURCE_AD (0x10)
446 #define MCB_AE_SOURCE_DIR2 (0x20)
447 #define MCB_AE_SOURCE_DIR0 (0x30)
448 #define MCB_AE_SOURCE_DIR1 (0x40)
449 #define MCB_AE_SOURCE_MIX (0x70)
450 #define MCB_DIT2_SOURCE_AD (0x01)
451 #define MCB_DIT2_SOURCE_DIR2 (0x02)
452 #define MCB_DIT2_SOURCE_DIR0 (0x03)
453 #define MCB_DIT2_SOURCE_DIR1 (0x04)
454 #define MCB_DIT2_SOURCE_MIX (0x07)
456 #define MCI_ESRC_SOURCE (114)
458 #define MCI_AENG6_SOURCE (115)
459 #define MCB_AENG6_ADC0 (0x00)
460 #define MCB_AENG6_PDM (0x01)
462 #define MCI_EFIFO_SOURCE (116)
464 #define MCI_SRC_SOURCE_2 (117)
466 #define MCI_PEAK_METER (121)
468 #define MCI_OVFL (122)
469 #define MCI_OVFR (123)
471 #define MCI_DIMODE0 (130)
473 #define MCI_DIRSRC_RATE0_MSB (131)
475 #define MCI_DIRSRC_RATE0_LSB (132)
477 #define MCI_DITSRC_RATE0_MSB (133)
479 #define MCI_DITSRC_RATE0_LSB (134)
481 #define MCI_DI_FS0 (135)
483 /* DI Common Parameter */
484 #define MCB_DICOMMON_SRC_RATE_SET (0x01)
486 #define MCI_DI0_SRC (136)
488 #define MCI_DIX0_START (137)
489 #define MCB_DITIM0_START (0x40)
490 #define MCB_DIR0_SRC_START (0x08)
491 #define MCB_DIR0_START (0x04)
492 #define MCB_DIT0_SRC_START (0x02)
493 #define MCB_DIT0_START (0x01)
495 #define MCI_DIX0_FMT (142)
497 #define MCI_DIR0_CH (143)
498 #define MCI_DIR0_CH_DEF (0x10)
500 #define MCI_DIT0_SLOT (144)
501 #define MCI_DIT0_SLOT_DEF (0x10)
503 #define MCI_HIZ_REDGE0 (145)
505 #define MCI_PCM_RX0 (146)
506 #define MCB_PCM_MONO_RX0 (0x80)
507 #define MCI_PCM_RX0_DEF (MCB_PCM_MONO_RX0)
509 #define MCI_PCM_SLOT_RX0 (147)
511 #define MCI_PCM_TX0 (148)
512 #define MCB_PCM_MONO_TX0 (0x80)
513 #define MCI_PCM_TX0_DEF (MCB_PCM_MONO_TX0)
515 #define MCI_PCM_SLOT_TX0 (149)
516 #define MCI_PCM_SLOT_TX0_DEF (0x10)
518 #define MCI_DIMODE1 (150)
520 #define MCI_DIRSRC_RATE1_MSB (151)
521 #define MCI_DIRSRC_RATE1_LSB (152)
523 #define MCI_DITSRC_RATE1_MSB (153)
524 #define MCI_DITSRC_RATE1_LSB (154)
526 #define MCI_DI_FS1 (155)
528 #define MCI_DI1_SRC (156)
530 #define MCI_DIX1_START (157)
531 #define MCB_DITIM1_START (0x40)
532 #define MCB_DIR1_SRC_START (0x08)
533 #define MCB_DIR1_START (0x04)
534 #define MCB_DIT1_SRC_START (0x02)
535 #define MCB_DIT1_START (0x01)
537 #define MCI_DIX1_FMT (162)
539 #define MCI_DIR1_CH (163)
540 #define MCB_DIR1_CH1 (0x10)
541 #define MCI_DIR1_CH_DEF (MCB_DIR1_CH1)
543 #define MCI_DIT1_SLOT (164)
544 #define MCB_DIT1_SLOT1 (0x10)
545 #define MCI_DIT1_SLOT_DEF (MCB_DIT1_SLOT1)
547 #define MCI_HIZ_REDGE1 (165)
549 #define MCI_PCM_RX1 (166)
550 #define MCB_PCM_MONO_RX1 (0x80)
551 #define MCI_PCM_RX1_DEF (MCB_PCM_MONO_RX1)
553 #define MCI_PCM_SLOT_RX1 (167)
555 #define MCI_PCM_TX1 (168)
556 #define MCB_PCM_MONO_TX1 (0x80)
557 #define MCI_PCM_TX1_DEF (MCB_PCM_MONO_TX1)
559 #define MCI_PCM_SLOT_TX1 (169)
560 #define MCI_PCM_SLOT_TX1_DEF (0x10)
562 #define MCI_DIMODE2 (170)
564 #define MCI_DIRSRC_RATE2_MSB (171)
565 #define MCI_DIRSRC_RATE2_LSB (172)
567 #define MCI_DITSRC_RATE2_MSB (173)
568 #define MCI_DITSRC_RATE2_LSB (174)
570 #define MCI_DI_FS2 (175)
572 #define MCI_DI2_SRC (176)
574 #define MCI_DIX2_START (177)
575 #define MCB_DITIM2_START (0x40)
576 #define MCB_DIR2_SRC_START (0x08)
577 #define MCB_DIR2_START (0x04)
578 #define MCB_DIT2_SRC_START (0x02)
579 #define MCB_DIT2_START (0x01)
581 #define MCI_DIX2_FMT (182)
583 #define MCI_DIR2_CH (183)
584 #define MCB_DIR2_CH1 (0x10)
585 #define MCB_DIR2_CH0 (0x01)
586 #define MCI_DIR2_CH_DEF (MCB_DIR2_CH1)
588 #define MCI_DIT2_SLOT (184)
589 #define MCB_DIT2_SLOT1 (0x10)
590 #define MCB_DIT2_SLOT0 (0x01)
591 #define MCI_DIT2_SLOT_DEF (MCB_DIT2_SLOT1)
593 #define MCI_HIZ_REDGE2 (185)
595 #define MCI_PCM_RX2 (186)
596 #define MCB_PCM_MONO_RX2 (0x80)
597 #define MCI_PCM_RX2_DEF (MCB_PCM_MONO_RX2)
599 #define MCI_PCM_SLOT_RX2 (187)
601 #define MCI_PCM_TX2 (188)
602 #define MCB_PCM_MONO_TX2 (0x80)
603 #define MCI_PCM_TX2_DEF (MCB_PCM_MONO_TX2)
605 #define MCI_PCM_SLOT_TX2 (189)
606 #define MCI_PCM_SLOT_TX2_DEF (0x10)
608 #define MCI_CD_START (192)
610 #define MCI_CDI_CH (193)
611 #define MCI_CDI_CH_DEF (0xE4)
613 #define MCI_CDO_SLOT (194)
614 #define MCI_CDO_SLOT_DEF (0xE4)
616 #define MCI_PDM_AGC (200)
617 #define MCI_PDM_AGC_DEF (0x03)
619 #define MCI_PDM_START (202)
620 #define MCB_PDM_MN (0x02)
621 #define MCB_PDM_START (0x01)
623 #define MCI_PDM_STWAIT (205)
624 #define MCI_PDM_STWAIT_DEF (0x40)
626 #define MCI_HP_ID (206)
628 #define MCI_CHP_H (207)
629 #define MCI_CHP_H_DEF (0x3F)
631 #define MCI_CHP_M (208)
632 #define MCI_CHP_M_DEF (0xEA)
634 #define MCI_CHP_L (209)
635 #define MCI_CHP_L_DEF (0x94)
637 #define MCI_SINGEN0_VOL (210)
638 #define MCI_SINGEN1_VOL (211)
640 #define MCI_SINGEN_FREQ0_MSB (212)
641 #define MCI_SINGEN_FREQ0_LSB (213)
643 #define MCI_SINGEN_FREQ1_MSB (214)
644 #define MCI_SINGEN_FREQ1_LSB (215)
646 #define MCI_SINGEN_GATETIME (216)
648 #define MCI_SINGEN_FLAG (217)
651 #define MCI_BAND0_CEQ0 (0)
652 #define MCI_BAND0_CEQ0_H_DEF (0x10)
654 #define MCI_BAND1_CEQ0 (15)
655 #define MCI_BAND1_CEQ0_H_DEF (0x10)
657 #define MCI_BAND2_CEQ0 (30)
658 #define MCI_BAND2_CEQ0_H_DEF (0x10)
660 #define MCI_BAND3H_CEQ0 (45)
661 #define MCI_BAND3H_CEQ0_H_DEF (0x10)
663 #define MCI_BAND4H_CEQ0 (75)
664 #define MCI_BAND4H_CEQ0_H_DEF (0x10)
666 #define MCI_BAND5_CEQ0 (105)
667 #define MCI_BAND5_CEQ0_H_DEF (0x10)
669 #define MCI_BAND6H_CEQ0 (120)
670 #define MCI_BAND6H_CEQ0_H_DEF (0x10)
672 #define MCI_BAND7H_CEQ0 (150)
673 #define MCI_BAND7H_CEQ0_H_DEF (0x10)
675 #define MCI_PDM_CHP0_H (240)
676 #define MCI_PDM_CHP0_H_DEF (0x3F)
677 #define MCI_PDM_CHP0_M (241)
678 #define MCI_PDM_CHP0_M_DEF (0xEA)
679 #define MCI_PDM_CHP0_L (242)
680 #define MCI_PDM_CHP0_L_DEF (0x94)
682 #define MCI_PDM_CHP1_H (243)
683 #define MCI_PDM_CHP1_H_DEF (0xC0)
684 #define MCI_PDM_CHP1_M (244)
685 #define MCI_PDM_CHP1_M_DEF (0x15)
686 #define MCI_PDM_CHP1_L (245)
687 #define MCI_PDM_CHP1_L_DEF (0x6C)
689 #define MCI_PDM_CHP2_H (246)
690 #define MCI_PDM_CHP2_H_DEF (0x00)
691 #define MCI_PDM_CHP2_M (247)
692 #define MCI_PDM_CHP2_M_DEF (0x00)
693 #define MCI_PDM_CHP2_L (248)
694 #define MCI_PDM_CHP2_L_DEF (0x00)
696 #define MCI_PDM_CHP3_H (249)
697 #define MCI_PDM_CHP3_H_DEF (0x3F)
698 #define MCI_PDM_CHP3_M (250)
699 #define MCI_PDM_CHP3_M_DEF (0xD5)
700 #define MCI_PDM_CHP3_L (251)
701 #define MCI_PDM_CHP3_L_DEF (0x29)
703 #define MCI_PDM_CHP4_H (252)
704 #define MCI_PDM_CHP4_H_DEF (0x00)
705 #define MCI_PDM_CHP4_M (253)
706 #define MCI_PDM_CHP4_M_DEF (0x00)
707 #define MCI_PDM_CHP4_L (254)
708 #define MCI_PDM_CHP4_L_DEF (0x00)
711 #define MCI_CDSP_SAVEOFF (0)
713 #define MCI_OFIFO_LVL (1)
715 #define MCI_EFIFO_LVL (2)
717 #define MCI_DEC_POS_24 (4)
718 #define MCI_DEC_POS_16 (5)
719 #define MCI_DEC_POS_8 (6)
720 #define MCI_DEC_POS_0 (7)
722 #define MCI_ENC_POS_24 (8)
723 #define MCI_ENC_POS_16 (9)
724 #define MCI_ENC_POS_8 (10)
725 #define MCI_ENC_POS_0 (11)
727 #define MCI_DEC_ERR (12)
728 #define MCI_ENC_ERR (13)
730 #define MCI_FIFO_RST (14)
732 #define MCI_DEC_ENC_START (15)
734 #define MCI_FIFO4CH (16)
736 #define MCI_DEC_CTL15 (19)
738 #define MCI_DEC_GPR15 (35)
740 #define MCI_DEC_SFR1 (51)
741 #define MCI_DEC_SFR0 (52)
743 #define MCI_ENC_CTL15 (53)
745 #define MCI_ENC_GPR15 (69)
747 #define MCI_ENC_SFR1 (85)
748 #define MCI_ENC_SFR0 (86)
750 #define MCI_JOEMP (92)
751 #define MCB_JOEMP (0x80)
752 #define MCB_JOPNT (0x40)
753 #define MCB_OOVF_FLG (0x08)
754 #define MCB_OUDF_FLG (0x04)
755 #define MCB_OEMP_FLG (0x02)
756 #define MCB_OPNT_FLG (0x01)
757 #define MCI_JOEMP_DEF (MCB_JOEMP | MCB_OEMP_FLG)
759 #define MCI_JEEMP (93)
760 #define MCB_JEEMP (0x80)
761 #define MCB_JEPNT (0x40)
762 #define MCB_EOVF_FLG (0x08)
763 #define MCB_EUDF_FLG (0x04)
764 #define MCB_EEMP_FLG (0x02)
765 #define MCB_EPNT_FLG (0x01)
766 #define MCI_JEEMP_DEF (MCB_JEEMP | MCB_EEMP_FLG)
768 #define MCI_DEC_FLG (96)
769 #define MCI_ENC_FLG (97)
771 #define MCI_DEC_GPR_FLG (98)
772 #define MCI_ENC_GPR_FLG (99)
774 #define MCI_EOPNT (101)
776 #define MCI_EDEC (105)
777 #define MCI_EENC (106)
779 #define MCI_EDEC_GPR (107)
780 #define MCI_EENC_GPR (108)
782 #define MCI_CDSP_SRST (110)
783 #define MCB_CDSP_FMODE (0x10)
784 #define MCB_CDSP_MSAVE (0x08)
785 #define MCB_CDSP_SRST (0x01)
786 #define MCI_CDSP_SRST_DEF (MCB_CDSP_SRST)
788 #define MCI_CDSP_SLEEP (112)
790 #define MCI_CDSP_ERR (113)
792 #define MCI_CDSP_MAR_MSB (114)
793 #define MCI_CDSP_MAR_LSB (115)
795 #define MCI_OFIFO_IRQ_PNT (116)
797 #define MCI_EFIFO_IRQ_PNT (122)
799 #define MCI_CDSP_FLG (128)
801 #define MCI_ECDSP_ERR (129)
804 #define MCI_DPADIF (1)
805 #define MCB_CLKSRC (0x80)
806 #define MCB_CLKBUSY (0x40)
807 #define MCB_CLKINPUT (0x20)
808 #define MCB_DPADIF (0x10)
809 #define MCB_DP0_CLKI1 (0x08)
810 #define MCB_DP0_CLKI0 (0x01)
811 #define MCI_DPADIF_DEF (MCB_DPADIF|MCB_DP0_CLKI1|MCB_DP0_CLKI0)
813 #define MCI_CKSEL (4)
814 #define MCB_CK1SEL (0x80)
815 #define MCB_CK0SEL (0x40)
817 #define MCI_CD_HW_ID (8)
818 #define MCI_CD_HW_ID_DEF (0x79)
820 #define MCI_PLL_RST (15)
821 #define MCB_PLLRST0 (0x01)
822 #define MCI_PLL_RST_DEF (MCB_PLLRST0)
824 #define MCI_DIVR0 (16)
825 #define MCI_DIVR0_DEF (0x0D)
827 #define MCI_DIVF0 (17)
828 #define MCI_DIVF0_DEF (0x55)
830 #define MCI_DIVR1 (18)
831 #define MCI_DIVR1_DEF (0x02)
833 #define MCI_DIVF1 (19)
834 #define MCI_DIVF1_DEF (0x48)
836 #define MCI_AD_AGC (70)
837 #define MCI_AD_AGC_DEF (0x03)
839 #define MCI_AD_START (72)
840 #define MCI_AD_START_DEF (0x00)
841 #define MCB_AD_START (0x01)
843 #define MCI_DCCUTOFF (77)
844 #define MCI_DCCUTOFF_DEF (0x00)
846 #define MCI_DAC_CONFIG (78)
847 #define MCI_DAC_CONFIG_DEF (0x02)
848 #define MCB_NSMUTE (0x02)
849 #define MCB_DACON (0x01)
852 #define MCI_DCL_DEF (0x00)
854 #define MCI_SYS_CEQ0_19_12 (80)
855 #define MCI_SYS_CEQ0_19_12_DEF (0x10)
857 #define MCI_SYS_CEQ0_11_4 (81)
858 #define MCI_SYS_CEQ0_11_4_DEF (0xC4)
860 #define MCI_SYS_CEQ0_3_0 (82)
861 #define MCI_SYS_CEQ0_3_0_DEF (0x50)
863 #define MCI_SYS_CEQ1_19_12 (83)
864 #define MCI_SYS_CEQ1_19_12_DEF (0x12)
866 #define MCI_SYS_CEQ1_11_4 (84)
867 #define MCI_SYS_CEQ1_11_4_DEF (0xC4)
869 #define MCI_SYS_CEQ1_3_0 (85)
870 #define MCI_SYS_CEQ1_3_0_DEF (0x40)
872 #define MCI_SYS_CEQ2_19_12 (86)
873 #define MCI_SYS_CEQ2_19_12_DEF (0x02)
875 #define MCI_SYS_CEQ2_11_4 (87)
876 #define MCI_SYS_CEQ2_11_4_DEF (0xA9)
878 #define MCI_SYS_CEQ2_3_0 (88)
879 #define MCI_SYS_CEQ2_3_0_DEF (0x60)
881 #define MCI_SYS_CEQ3_19_12 (89)
882 #define MCI_SYS_CEQ3_19_12_DEF (0xED)
884 #define MCI_SYS_CEQ3_11_4 (90)
885 #define MCI_SYS_CEQ3_11_4_DEF (0x3B)
887 #define MCI_SYS_CEQ3_3_0 (91)
888 #define MCI_SYS_CEQ3_3_0_DEF (0xC0)
890 #define MCI_SYS_CEQ4_19_12 (92)
891 #define MCI_SYS_CEQ4_19_12_DEF (0xFC)
893 #define MCI_SYS_CEQ4_11_4 (93)
894 #define MCI_SYS_CEQ4_11_4_DEF (0x92)
896 #define MCI_SYS_CEQ4_3_0 (94)
897 #define MCI_SYS_CEQ4_3_0_DEF (0x40)
899 #define MCI_SYSTEM_EQON (95)
900 #define MCB_SYSEQ_INTP (0x20)
901 #define MCB_SYSEQ_FLAG (0x10)
902 #define MCB_SYSTEM_EQON (0x01)
903 #define MCI_SYSTEM_EQON_DEF (MCB_SYSEQ_INTP|MCB_SYSTEM_EQON)
906 #define MCI_ANA_RST (0)
907 #define MCI_ANA_RST_DEF (0x01)
909 #define MCI_PWM_ANALOG_0 (2)
910 #define MCB_PWM_VR (0x01)
911 #define MCB_PWM_CP (0x02)
912 #define MCB_PWM_REFA (0x04)
913 #define MCB_PWM_LDOA (0x08)
914 #define MCI_PWM_ANALOG_0_DEF (MCB_PWM_VR|MCB_PWM_CP|MCB_PWM_REFA|MCB_PWM_LDOA)
916 #define MCI_PWM_ANALOG_1 (3)
917 #define MCB_PWM_SPL1 (0x01)
918 #define MCB_PWM_SPL2 (0x02)
919 #define MCB_PWM_SPR1 (0x04)
920 #define MCB_PWM_SPR2 (0x08)
921 #define MCB_PWM_HPL (0x10)
922 #define MCB_PWM_HPR (0x20)
923 #define MCB_PWM_ADL (0x40)
924 #define MCB_PWM_ADR (0x80)
925 #define MCI_PWM_ANALOG_1_DEF (MCB_PWM_SPL1|MCB_PWM_SPL2|MCB_PWM_SPR1|MCB_PWM_SPR2|MCB_PWM_HPL|MCB_PWM_HPR|MCB_PWM_ADL|MCB_PWM_ADR)
927 #define MCI_PWM_ANALOG_2 (4)
928 #define MCB_PWM_LO1L (0x01)
929 #define MCB_PWM_LO1R (0x02)
930 #define MCB_PWM_LO2L (0x04)
931 #define MCB_PWM_LO2R (0x08)
932 #define MCB_PWM_RC1 (0x10)
933 #define MCB_PWM_RC2 (0x20)
934 #define MCI_PWM_ANALOG_2_DEF (MCB_PWM_LO1L|MCB_PWM_LO1R|MCB_PWM_LO2L|MCB_PWM_LO2R|MCB_PWM_RC1|MCB_PWM_RC2)
936 #define MCI_PWM_ANALOG_3 (5)
937 #define MCB_PWM_MB1 (0x01)
938 #define MCB_PWM_MB2 (0x02)
939 #define MCB_PWM_MB3 (0x04)
940 #define MCB_PWM_DAL (0x08)
941 #define MCB_PWM_DAR (0x10)
942 #define MCI_PWM_ANALOG_3_DEF (MCB_PWM_MB1|MCB_PWM_MB2|MCB_PWM_MB3|MCB_PWM_DAL|MCB_PWM_DAR)
944 #define MCI_PWM_ANALOG_4 (6)
945 #define MCB_PWM_MC1 (0x10)
946 #define MCB_PWM_MC2 (0x20)
947 #define MCB_PWM_MC3 (0x40)
948 #define MCB_PWM_LI (0x80)
949 #define MCI_PWM_ANALOG_4_DEF (MCB_PWM_MC1|MCB_PWM_MC2|MCB_PWM_MC3|MCB_PWM_LI)
951 #define MCI_BUSY1 (12)
952 #define MCB_RC_BUSY (0x20)
953 #define MCB_HPL_BUSY (0x10)
954 #define MCB_SPL_BUSY (0x08)
956 #define MCI_BUSY2 (13)
957 #define MCB_HPR_BUSY (0x10)
958 #define MCB_SPR_BUSY (0x08)
960 #define MCI_APMOFF (16)
961 #define MCB_APMOFF_SP (0x01)
962 #define MCB_APMOFF_HP (0x02)
963 #define MCB_APMOFF_RC (0x04)
965 #define MCI_DIF_LINE (24)
966 #define MCI_DIF_LINE_DEF (0x00)
968 #define MCI_LI1VOL_L (25)
969 #define MCI_LI1VOL_L_DEF (0x00)
970 #define MCB_ALAT_LI1 (0x40)
971 #define MCB_LI1VOL_L (0x1F)
973 #define MCI_LI1VOL_R (26)
974 #define MCI_LI1VOL_R_DEF (0x00)
975 #define MCB_LI1VOL_R (0x1F)
977 #define MCI_LI2VOL_L (27)
978 #define MCI_LI2VOL_L_DEF (0x00)
979 #define MCB_ALAT_LI2 (0x40)
980 #define MCB_LI2VOL_L (0x1F)
982 #define MCI_LI2VOL_R (28)
983 #define MCI_LI2VOL_R_DEF (0x00)
984 #define MCB_LI2VOL_R (0x1F)
986 #define MCI_MC1VOL (29)
987 #define MCI_MC1VOL_DEF (0x00)
988 #define MCB_MC1VOL (0x1F)
990 #define MCI_MC2VOL (30)
991 #define MCI_MC2VOL_DEF (0x00)
992 #define MCB_MC2VOL (0x1F)
994 #define MCI_MC3VOL (31)
995 #define MCI_MC3VOL_DEF (0x00)
996 #define MCB_MC3VOL (0x1F)
998 #define MCI_ADVOL_L (32)
999 #define MCI_ADVOL_L_DEF (0x00)
1000 #define MCB_ALAT_AD (0x40)
1001 #define MCB_ADVOL_L (0x1F)
1003 #define MCI_ADVOL_R (33)
1004 #define MCB_ADVOL_R (0x1F)
1006 #define MCI_HPVOL_L (35)
1007 #define MCB_ALAT_HP (0x40)
1008 #define MCB_SVOL_HP (0x20)
1009 #define MCB_HPVOL_L (0x1F)
1010 #define MCI_HPVOL_L_DEF (MCB_SVOL_HP)
1012 #define MCI_HPVOL_R (36)
1013 #define MCI_HPVOL_R_DEF (0x00)
1014 #define MCB_HPVOL_R (0x1F)
1016 #define MCI_SPVOL_L (37)
1017 #define MCB_ALAT_SP (0x40)
1018 #define MCB_SVOL_SP (0x20)
1019 #define MCB_SPVOL_L (0x1F)
1020 #define MCI_SPVOL_L_DEF (MCB_SVOL_SP)
1022 #define MCI_SPVOL_R (38)
1023 #define MCI_SPVOL_R_DEF (0x00)
1024 #define MCB_SPVOL_R (0x1F)
1026 #define MCI_RCVOL (39)
1027 #define MCB_SVOL_RC (0x20)
1028 #define MCB_RCVOL (0x1F)
1029 #define MCI_RCVOL_DEF (MCB_SVOL_RC)
1031 #define MCI_LO1VOL_L (40)
1032 #define MCI_LO1VOL_L_DEF (0x20)
1033 #define MCB_ALAT_LO1 (0x40)
1034 #define MCB_LO1VOL_L (0x1F)
1036 #define MCI_LO1VOL_R (41)
1037 #define MCI_LO1VOL_R_DEF (0x00)
1038 #define MCB_LO1VOL_R (0x1F)
1040 #define MCI_LO2VOL_L (42)
1041 #define MCI_LO2VOL_L_DEF (0x20)
1042 #define MCB_ALAT_LO2 (0x40)
1043 #define MCB_LO2VOL_L (0x1F)
1045 #define MCI_LO2VOL_R (43)
1046 #define MCI_LO2VOL_R_DEF (0x00)
1047 #define MCB_LO2VOL_R (0x1F)
1049 #define MCI_SP_MODE (44)
1050 #define MCB_SPR_HIZ (0x20)
1051 #define MCB_SPL_HIZ (0x10)
1052 #define MCB_SPMN (0x02)
1053 #define MCB_SP_SWAP (0x01)
1055 #define MCI_MC_GAIN (45)
1056 #define MCI_MC_GAIN_DEF (0x00)
1057 #define MCB_MC2SNG (0x40)
1058 #define MCB_MC2GAIN (0x30)
1059 #define MCB_MC1SNG (0x04)
1060 #define MCB_MC1GAIN (0x03)
1062 #define MCI_MC3_GAIN (46)
1063 #define MCI_MC3_GAIN_DEF (0x00)
1064 #define MCB_MC3SNG (0x04)
1065 #define MCB_MC3GAIN (0x03)
1067 #define MCI_RDY_FLAG (47)
1068 #define MCB_LDO_RDY (0x80)
1069 #define MCB_VREF_RDY (0x40)
1070 #define MCB_SPRDY_R (0x20)
1071 #define MCB_SPRDY_L (0x10)
1072 #define MCB_HPRDY_R (0x08)
1073 #define MCB_HPRDY_L (0x04)
1074 #define MCB_CPPDRDY (0x02)
1076 /* analog mixer common */
1077 #define MCB_LI1MIX (0x01)
1078 #define MCB_M1MIX (0x08)
1079 #define MCB_M2MIX (0x10)
1080 #define MCB_M3MIX (0x20)
1081 #define MCB_DAMIX (0x40)
1082 #define MCB_DARMIX (0x40)
1083 #define MCB_DALMIX (0x80)
1085 #define MCB_MONO_DA (0x40)
1086 #define MCB_MONO_LI1 (0x01)
1088 #define MCI_ADL_MIX (50)
1089 #define MCI_ADL_MONO (51)
1090 #define MCI_ADR_MIX (52)
1091 #define MCI_ADR_MONO (53)
1093 #define MCI_LO1L_MIX (55)
1094 #define MCI_LO1L_MONO (56)
1095 #define MCI_LO1R_MIX (57)
1097 #define MCI_LO2L_MIX (58)
1098 #define MCI_LO2L_MONO (59)
1099 #define MCI_LO2R_MIX (60)
1101 #define MCI_HPL_MIX (61)
1102 #define MCI_HPL_MONO (62)
1103 #define MCI_HPR_MIX (63)
1105 #define MCI_SPL_MIX (64)
1106 #define MCI_SPL_MONO (65)
1107 #define MCI_SPR_MIX (66)
1108 #define MCI_SPR_MONO (67)
1110 #define MCI_RC_MIX (69)
1112 #define MCI_CPMOD (72)
1114 #define MCI_HP_GAIN (77)
1116 #define MCI_LEV (79)
1117 #define MCB_AVDDLEV (0x07)
1118 #define MCI_LEV_DEF (0x24)
1120 #define MCI_DNGATRT_HP (82)
1121 #define MCI_DNGATRT_HP_DEF (0x23)
1123 #define MCI_DNGTARGET_HP (83)
1124 #define MCI_DNGTARGET_HP_DEF (0x50)
1126 #define MCI_DNGON_HP (84)
1127 #define MCI_DNGON_HP_DEF (0x54)
1129 #define MCI_DNGATRT_SP (85)
1130 #define MCI_DNGATRT_SP_DEF (0x23)
1132 #define MCI_DNGTARGET_SP (86)
1133 #define MCI_DNGTARGET_SP_DEF (0x50)
1135 #define MCI_DNGON_SP (87)
1136 #define MCI_DNGON_SP_DEF (0x54)
1138 #define MCI_DNGATRT_RC (88)
1139 #define MCI_DNGATRT_RC_DEF (0x23)
1141 #define MCI_DNGTARGET_RC (89)
1142 #define MCI_DNGTARGET_RC_DEF (0x50)
1144 #define MCI_DNGON_RC (90)
1145 #define MCI_DNGON_RC_DEF (0x54)
1147 #define MCI_AP_A1 (123)
1148 #define MCB_AP_CP_A (0x10)
1149 #define MCB_AP_HPL_A (0x02)
1150 #define MCB_AP_HPR_A (0x01)
1152 #define MCI_AP_A2 (124)
1153 #define MCB_AP_RC1_A (0x20)
1154 #define MCB_AP_RC2_A (0x10)
1155 #define MCB_AP_SPL1_A (0x08)
1156 #define MCB_AP_SPR1_A (0x04)
1157 #define MCB_AP_SPL2_A (0x02)
1158 #define MCB_AP_SPR2_A (0x01)
1160 #endif /* __MCDEFS_H__ */