sound/soc/codecs/mc1n2/mc1n2_i2c.c

   1 /*
   2  * mc1n2_i2c.c  --  MC1N2 ALSA SoC Audio driver
   3  *
   4  * Copyright (C) 2010 Samsung Electronics Co.Ltd
   5  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/i2c.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc-dapm.h>
  25 #include <sound/initval.h>
  26 #include <sound/tlv.h>
  27
  28 #include <sound/mc1n2/mc1n2_priv.h>
  29
  30 #define mc1n2_i2c_read_byte_cw(c,r) i2c_smbus_read_byte_data((c), (r)<<1)
  31
  32 static int mc1n2_common_i2c(struct snd_soc_codec *codec, unsigned int reg,
  33         unsigned int value, u8 *rAddr, u8 *rData)
  34 {
  35         u8 rType;
  36
  37         rType = access_masks[reg].rType;
  38         switch (rType) {
  39                 case MC1N2_A:
  40                         rAddr[0] = -1;
  41                         rAddr[1] = -1;
  42
  43                         rData[0] = access_masks[reg].rAddr;
  44                         rData[1] = (u8)value;
  45                         return 2;
  46                 case MC1N2_BASE:
  47                         rAddr[0] = __MC1N2_A_BASE_ADR << 1;
  48                         rAddr[1] = access_masks[reg].rAddr;
  49
  50                         rData[0] = __MC1N2_A_BASE_WINDOW;
  51                         rData[1] = (u8)value;
  52                         break;
  53                 case MC1N2_ANA:
  54                         rAddr[0] = __MC1N2_A_ANA_ADR << 1;
  55                         rAddr[1] = access_masks[reg].rAddr;
  56
  57                         rData[0] = __MC1N2_A_ANA_WINDOW;
  58                         rData[1] = (u8)value;
  59                         break;
  60                 case MC1N2_CD:
  61                         rAddr[0] = __MC1N2_A_CD_ADR << 1;
  62                         rAddr[1] = access_masks[reg].rAddr;
  63
  64                         rData[0] = __MC1N2_A_CD_WINDOW;
  65                         rData[1] = (u8)value;
  66                         break;
  67                 case MC1N2_MIX:
  68                         rAddr[0] = __MC1N2_A_MIX_ADR << 1;
  69                         rAddr[1] = access_masks[reg].rAddr;
  70
  71                         rData[0] = __MC1N2_A_MIX_WINDOW;
  72                         rData[1] = (u8)value;
  73                         break;
  74                 case MC1N2_AE:
  75                         rAddr[0] = __MC1N2_A_AE_ADR << 1;
  76                         rAddr[1] = access_masks[reg].rAddr;
  77
  78                         rData[0] = __MC1N2_A_AE_WINDOW;
  79                         rData[1] = (u8)value;
  80                         break;
  81                 case MC1N2_BDSP:
  82                         rAddr[0] = __MC1N2_A_BDSP_ADR << 1;
  83                         rAddr[1] = access_masks[reg].rAddr;
  84
  85                         rData[0] = __MC1N2_A_BDSP_WINDOW;
  86                         rData[1] = (u8)value;
  87                         break;
  88                 default:
  89                         dev_err(codec->dev, "Failed to write the register of codec\n");
  90                         return -EINVAL;
  91         }
  92
  93         return i2c_master_send(codec->control_data, rAddr, 2);
  94 }
  95
  96 int mc1n2_i2c_write(struct snd_soc_codec *codec, unsigned int reg,
  97         unsigned int value)
  98 {
  99         u8 *reg_cache = codec->reg_cache;
 100         u8 rAddr[2];
 101         u8 rData[2];
 102         int ret;
 103
 104         ret = mc1n2_common_i2c(codec, reg, value, rAddr, rData);
 105         if (ret < 0) goto err1;
 106
 107         rData[0] = rData[0] << 1;
 108         ret = i2c_master_send(codec->control_data, rData, 2);
 109         if (ret < 0) goto err1;
 110
 111         reg_cache[reg] = value;
 112
 113         return 0;
 114 err1:
 115         dev_err(codec->dev, "Failed to write data on I2C bus: %d\n", ret);
 116         return ret;
 117 }
 118 EXPORT_SYMBOL(mc1n2_i2c_write);
 119
 120 #define mc1n2_i2c_read_byte(c,r) i2c_smbus_read_byte_data((c), (r)<<1)
 121 static unsigned int mc1n2_i2c_read(struct snd_soc_codec *codec,
 122                                 unsigned int reg)
 123 {
 124         u8 rAddr[2];
 125         u8 rData[2];
 126         /* u8 *reg_cache = codec->reg_cache; */
 127         int ret;
 128
 129         ret = mc1n2_common_i2c(codec, reg, -1, rAddr, rData);
 130         if (ret < 0) goto err1;
 131
 132         ret = mc1n2_i2c_read_byte(codec->control_data, rData[0]);
 133         if (ret < 0) goto err1;
 134
 135         return ret;
 136 err1:
 137         dev_err(codec->dev, "Failed to write data on I2C bus: %d\n", ret);
 138         return ret;
 139 }
 140
 141 static void mc1n2_set_path(struct snd_soc_codec *codec)
 142 {
 143         return;
 144 }
 145
 146 void mc1n2_show_reg(struct snd_soc_codec *codec)
 147 {
 148         int i;
 149         unsigned char rType;
 150         unsigned char rAddr;
 151         unsigned char rData;
 152
 153         mc1n2_set_path(codec);
 154
 155         printk("SHOW REGISTER \n");
 156         printk("MC1N2_MAX_REGISTER : %d\n", MC1N2_MAX_REGISTER);
 157
 158         for (i = 0 ; i < MC1N2_MAX_REGISTER ; i++) {
 159                 rType = access_masks[i].rType;
 160                 rAddr = access_masks[i].rAddr;
 161                 rData = mc1n2_i2c_read(codec, i);
 162
 163                 switch (rType) {
 164                         case MC1N2_A:
 165                                 printk("A_ADR #%d\t : 0x%x \t (%s)\n",
 166                                         rAddr, rData, access_masks_reg[i].name);
 167                                 break;
 168                         case MC1N2_BASE:
 169                                 printk("BASE_ADR #%d\t : 0x%x \t (%s)\n",
 170                                         rAddr, rData, access_masks_reg[i].name);
 171                                 break;
 172                         case MC1N2_ANA:
 173                                 printk("ANA_ADR #%d\t : 0x%x \t (%s)\n",
 174                                         rAddr, rData, access_masks_reg[i].name);
 175                                 break;
 176                         case MC1N2_CD:
 177                                 printk("CD_ADR #%d\t : 0x%x \t (%s)\n",
 178                                         rAddr, rData, access_masks_reg[i].name);
 179                                 break;
 180                         case MC1N2_MIX:
 181                                 printk("MIX_ADR #%d\t : 0x%x \t (%s)\n",
 182                                         rAddr, rData, access_masks_reg[i].name);
 183                                 break;
 184                         case MC1N2_AE:
 185                                 printk("AE_ADR #%d\t : 0x%x \t (%s)\n",
 186                                         rAddr, rData, access_masks_reg[i].name);
 187                                 break;
 188                         case MC1N2_BDSP:
 189                                 printk("BDSP_ADR #%d\t : 0x%x \t (%s)\n",
 190                                         rAddr, rData, access_masks_reg[i].name);
 191                                 break;
 192                         default:
 193                                 return;
 194                 }
 195         }
 196
 197         return;
 198 }
 199 EXPORT_SYMBOL(mc1n2_show_reg);