drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 static struct pll_map pll_value[] = {
  26         {25175000,
  27                 {99, 7, 3},
  28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
  29                 {141, 5, 4},
  30                 {141, 5, 4} },
  31         {29581000,
  32                 {33, 4, 2},
  33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
  34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
  35                 {165, 5, 4} },
  36         {26880000,
  37                 {15, 4, 1},
  38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
  39                 {150, 5, 4},
  40                 {150, 5, 4} },
  41         {31500000,
  42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
  43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
  44                 {176, 5, 4},
  45                 {176, 5, 4} },
  46         {31728000,
  47                 {31, 7, 1},
  48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
  49                 {177, 5, 4},
  50                 {142, 4, 4} },
  51         {32688000,
  52                 {73, 4, 3},
  53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
  54                 {183, 5, 4},
  55                 {146, 4, 4} },
  56         {36000000,
  57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
  58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
  59                 {202, 5, 4},
  60                 {161, 4, 4} },
  61         {40000000,
  62                 {89, 4, 3},
  63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
  64                 {112, 5, 3},
  65                 {112, 5, 3} },
  66         {41291000,
  67                 {23, 4, 1},
  68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
  69                 {115, 5, 3},
  70                 {115, 5, 3} },
  71         {43163000,
  72                 {121, 5, 3},
  73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
  74                 {121, 5, 3},
  75                 {121, 5, 3} },
  76         {45250000,
  77                 {127, 5, 3},
  78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
  79                 {127, 5, 3},
  80                 {127, 5, 3} },
  81         {46000000,
  82                 {90, 7, 2},
  83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
  84                 {129, 5, 3},
  85                 {103, 4, 3} },
  86         {46996000,
  87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
  88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  90                 {105, 4, 3} },
  91         {48000000,
  92                 {67, 20, 0},
  93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
  94                 {134, 5, 3},
  95                 {134, 5, 3} },
  96         {48875000,
  97                 {99, 29, 0},
  98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
  99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
 100                 {137, 5, 3} },
 101         {49500000,
 102                 {83, 6, 2},
 103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
 104                 {138, 5, 3},
 105                 {83, 3, 3} },
 106         {52406000,
 107                 {117, 4, 3},
 108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
 109                 {117, 4, 3},
 110                 {88, 3, 3} },
 111         {52977000,
 112                 {37, 5, 1},
 113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
 114                 {148, 5, 3},
 115                 {148, 5, 3} },
 116         {56250000,
 117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
 118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
 119                 {157, 5, 3},
 120                 {157, 5, 3} },
 121         {57275000,
 122                 {0, 0, 0},
 123                 {2, 2, 0},
 124                 {2, 2, 0},
 125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
 126         {60466000,
 127                 {76, 9, 1},
 128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
 129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
 130                 {169, 5, 3} },
 131         {61500000,
 132                 {86, 20, 0},
 133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
 134                 {172, 5, 3},
 135                 {172, 5, 3} },
 136         {65000000,
 137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
 138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
 139                 {109, 3, 3},
 140                 {109, 3, 3} },
 141         {65178000,
 142                 {91, 5, 2},
 143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
 144                 {109, 3, 3},
 145                 {182, 5, 3} },
 146         {66750000,
 147                 {75, 4, 2},
 148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
 149                 {150, 4, 3},
 150                 {112, 3, 3} },
 151         {68179000,
 152                 {19, 4, 0},
 153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
 154                 {190, 5, 3},
 155                 {191, 5, 3} },
 156         {69924000,
 157                 {83, 17, 0},
 158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
 159                 {195, 5, 3},
 160                 {195, 5, 3} },
 161         {70159000,
 162                 {98, 20, 0},
 163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
 164                 {196, 5, 3},
 165                 {195, 5, 3} },
 166         {72000000,
 167                 {121, 24, 0},
 168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
 169                 {161, 4, 3},
 170                 {161, 4, 3} },
 171         {78750000,
 172                 {33, 3, 1},
 173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
 174                 {110, 5, 2},
 175                 {110, 5, 2} },
 176         {80136000,
 177                 {28, 5, 0},
 178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
 179                 {112, 5, 2},
 180                 {112, 5, 2} },
 181         {83375000,
 182                 {93, 2, 3},
 183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 185                 {117, 5, 2} },
 186         {83950000,
 187                 {41, 7, 0},
 188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
 189                 {117, 5, 2},
 190                 {117, 5, 2} },
 191         {84750000,
 192                 {118, 5, 2},
 193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
 194                 {118, 5, 2},
 195                 {118, 5, 2} },
 196         {85860000,
 197                 {84, 7, 1},
 198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
 199                 {120, 5, 2},
 200                 {118, 5, 2} },
 201         {88750000,
 202                 {31, 5, 0},
 203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
 204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
 205                 {124, 5, 2} },
 206         {94500000,
 207                 {33, 5, 0},
 208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
 209                 {132, 5, 2},
 210                 {132, 5, 2} },
 211         {97750000,
 212                 {82, 6, 1},
 213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
 214                 {137, 5, 2},
 215                 {137, 5, 2} },
 216         {101000000,
 217                 {127, 9, 1},
 218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
 219                 {141, 5, 2},
 220                 {141, 5, 2} },
 221         {106500000,
 222                 {119, 4, 2},
 223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
 224                 {119, 4, 2},
 225                 {149, 5, 2} },
 226         {108000000,
 227                 {121, 4, 2},
 228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
 229                 {151, 5, 2},
 230                 {151, 5, 2} },
 231         {113309000,
 232                 {95, 12, 0},
 233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
 234                 {95, 3, 2},
 235                 {159, 5, 2} },
 236         {118840000,
 237                 {83, 5, 1},
 238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
 239                 {166, 5, 2},
 240                 {166, 5, 2} },
 241         {119000000,
 242                 {108, 13, 0},
 243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
 244                 {133, 4, 2},
 245                 {167, 5, 2} },
 246         {121750000,
 247                 {85, 5, 1},
 248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
 249                 {68, 2, 2},
 250                 {0, 0, 0} },
 251         {125104000,
 252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
 253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
 254                 {175, 5, 2},
 255                 {0, 0, 0} },
 256         {135000000,
 257                 {94, 5, 1},
 258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
 259                 {151, 4, 2},
 260                 {189, 5, 2} },
 261         {136700000,
 262                 {115, 12, 0},
 263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
 264                 {191, 5, 2},
 265                 {191, 5, 2} },
 266         {138400000,
 267                 {87, 9, 0},
 268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
 269                 {116, 3, 2},
 270                 {194, 5, 2} },
 271         {146760000,
 272                 {103, 5, 1},
 273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
 274                 {206, 5, 2},
 275                 {206, 5, 2} },
 276         {153920000,
 277                 {86, 8, 0},
 278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
 279                 {86, 4, 1},
 280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
 281         {156000000,
 282                 {109, 5, 1},
 283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
 284                 {109, 5, 1},
 285                 {108, 5, 1} },
 286         {157500000,
 287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
 288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
 289                 {110, 5, 1},
 290                 {110, 5, 1} },
 291         {162000000,
 292                 {113, 5, 1},
 293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
 294                 {113, 5, 1},
 295                 {113, 5, 1} },
 296         {187000000,
 297                 {118, 9, 0},
 298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
 299                 {131, 5, 1},
 300                 {131, 5, 1} },
 301         {193295000,
 302                 {108, 8, 0},
 303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
 304                 {135, 5, 1},
 305                 {135, 5, 1} },
 306         {202500000,
 307                 {99, 7, 0},
 308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
 309                 {142, 5, 1},
 310                 {142, 5, 1} },
 311         {204000000,
 312                 {100, 7, 0},
 313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
 314                 {143, 5, 1},
 315                 {143, 5, 1} },
 316         {218500000,
 317                 {92, 6, 0},
 318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
 319                 {153, 5, 1},
 320                 {153, 5, 1} },
 321         {234000000,
 322                 {98, 6, 0},
 323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
 324                 {98, 3, 1},
 325                 {164, 5, 1} },
 326         {267250000,
 327                 {112, 6, 0},
 328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
 329                 {187, 5, 1},
 330                 {187, 5, 1} },
 331         {297500000,
 332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
 333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
 334                 {208, 5, 1},
 335                 {208, 5, 1} },
 336         {74481000,
 337                 {26, 5, 0},
 338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
 339                 {208, 5, 3},
 340                 {209, 5, 3} },
 341         {172798000,
 342                 {121, 5, 1},
 343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
 344                 {121, 5, 1},
 345                 {121, 5, 1} },
 346         {122614000,
 347                 {60, 7, 0},
 348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
 349                 {137, 4, 2},
 350                 {172, 5, 2} },
 351         {74270000,
 352                 {83, 8, 1},
 353                 {208, 5, 3},
 354                 {208, 5, 3},
 355                 {0, 0, 0} },
 356         {148500000,
 357                 {83, 8, 0},
 358                 {208, 5, 2},
 359                 {166, 4, 2},
 360                 {208, 5, 2} }
 361 };
 362
 363 static struct fifo_depth_select display_fifo_depth_reg = {
 364         /* IGA1 FIFO Depth_Select */
 365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 366         /* IGA2 FIFO Depth_Select */
 367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 369 };
 370
 371 static struct fifo_threshold_select fifo_threshold_select_reg = {
 372         /* IGA1 FIFO Threshold Select */
 373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 374         /* IGA2 FIFO Threshold Select */
 375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 376 };
 377
 378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 379         /* IGA1 FIFO High Threshold Select */
 380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 381         /* IGA2 FIFO High Threshold Select */
 382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 383 };
 384
 385 static struct display_queue_expire_num display_queue_expire_num_reg = {
 386         /* IGA1 Display Queue Expire Num */
 387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 388         /* IGA2 Display Queue Expire Num */
 389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 390 };
 391
 392 /* Definition Fetch Count Registers*/
 393 static struct fetch_count fetch_count_reg = {
 394         /* IGA1 Fetch Count Register */
 395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 396         /* IGA2 Fetch Count Register */
 397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 398 };
 399
 400 static struct iga1_crtc_timing iga1_crtc_reg = {
 401         /* IGA1 Horizontal Total */
 402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 403         /* IGA1 Horizontal Addressable Video */
 404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 405         /* IGA1 Horizontal Blank Start */
 406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 407         /* IGA1 Horizontal Blank End */
 408         {IGA1_HOR_BLANK_END_REG_NUM,
 409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 410         /* IGA1 Horizontal Sync Start */
 411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 412         /* IGA1 Horizontal Sync End */
 413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 414         /* IGA1 Vertical Total */
 415         {IGA1_VER_TOTAL_REG_NUM,
 416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 417         /* IGA1 Vertical Addressable Video */
 418         {IGA1_VER_ADDR_REG_NUM,
 419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 420         /* IGA1 Vertical Blank Start */
 421         {IGA1_VER_BLANK_START_REG_NUM,
 422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 423         /* IGA1 Vertical Blank End */
 424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 425         /* IGA1 Vertical Sync Start */
 426         {IGA1_VER_SYNC_START_REG_NUM,
 427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 428         /* IGA1 Vertical Sync End */
 429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 430 };
 431
 432 static struct iga2_crtc_timing iga2_crtc_reg = {
 433         /* IGA2 Horizontal Total */
 434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 435         /* IGA2 Horizontal Addressable Video */
 436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 437         /* IGA2 Horizontal Blank Start */
 438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 439         /* IGA2 Horizontal Blank End */
 440         {IGA2_HOR_BLANK_END_REG_NUM,
 441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 442         /* IGA2 Horizontal Sync Start */
 443         {IGA2_HOR_SYNC_START_REG_NUM,
 444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 445         /* IGA2 Horizontal Sync End */
 446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 447         /* IGA2 Vertical Total */
 448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 449         /* IGA2 Vertical Addressable Video */
 450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 451         /* IGA2 Vertical Blank Start */
 452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 453         /* IGA2 Vertical Blank End */
 454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 455         /* IGA2 Vertical Sync Start */
 456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 457         /* IGA2 Vertical Sync End */
 458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 459 };
 460
 461 static struct rgbLUT palLUT_table[] = {
 462         /* {R,G,B} */
 463         /* Index 0x00~0x03 */
 464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 465                                                                      0x2A,
 466                                                                      0x2A},
 467         /* Index 0x04~0x07 */
 468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 469                                                                      0x2A,
 470                                                                      0x2A},
 471         /* Index 0x08~0x0B */
 472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 473                                                                      0x3F,
 474                                                                      0x3F},
 475         /* Index 0x0C~0x0F */
 476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 477                                                                      0x3F,
 478                                                                      0x3F},
 479         /* Index 0x10~0x13 */
 480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 481                                                                      0x0B,
 482                                                                      0x0B},
 483         /* Index 0x14~0x17 */
 484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 485                                                                      0x18,
 486                                                                      0x18},
 487         /* Index 0x18~0x1B */
 488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 489                                                                      0x28,
 490                                                                      0x28},
 491         /* Index 0x1C~0x1F */
 492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 493                                                                      0x3F,
 494                                                                      0x3F},
 495         /* Index 0x20~0x23 */
 496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 497                                                                      0x00,
 498                                                                      0x3F},
 499         /* Index 0x24~0x27 */
 500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 501                                                                      0x00,
 502                                                                      0x10},
 503         /* Index 0x28~0x2B */
 504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 505                                                                      0x2F,
 506                                                                      0x00},
 507         /* Index 0x2C~0x2F */
 508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 509                                                                      0x3F,
 510                                                                      0x00},
 511         /* Index 0x30~0x33 */
 512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 513                                                                      0x3F,
 514                                                                      0x2F},
 515         /* Index 0x34~0x37 */
 516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 517                                                                      0x10,
 518                                                                      0x3F},
 519         /* Index 0x38~0x3B */
 520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 521                                                                      0x1F,
 522                                                                      0x3F},
 523         /* Index 0x3C~0x3F */
 524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 525                                                                      0x1F,
 526                                                                      0x27},
 527         /* Index 0x40~0x43 */
 528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 529                                                                      0x3F,
 530                                                                      0x1F},
 531         /* Index 0x44~0x47 */
 532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 533                                                                      0x3F,
 534                                                                      0x1F},
 535         /* Index 0x48~0x4B */
 536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 537                                                                      0x3F,
 538                                                                      0x37},
 539         /* Index 0x4C~0x4F */
 540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 541                                                                      0x27,
 542                                                                      0x3F},
 543         /* Index 0x50~0x53 */
 544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 545                                                                      0x2D,
 546                                                                      0x3F},
 547         /* Index 0x54~0x57 */
 548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 549                                                                      0x2D,
 550                                                                      0x31},
 551         /* Index 0x58~0x5B */
 552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 553                                                                      0x3A,
 554                                                                      0x2D},
 555         /* Index 0x5C~0x5F */
 556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 557                                                                      0x3F,
 558                                                                      0x2D},
 559         /* Index 0x60~0x63 */
 560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 561                                                                      0x3F,
 562                                                                      0x3A},
 563         /* Index 0x64~0x67 */
 564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 565                                                                      0x31,
 566                                                                      0x3F},
 567         /* Index 0x68~0x6B */
 568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 569                                                                      0x00,
 570                                                                      0x1C},
 571         /* Index 0x6C~0x6F */
 572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 573                                                                      0x00,
 574                                                                      0x07},
 575         /* Index 0x70~0x73 */
 576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 577                                                                      0x15,
 578                                                                      0x00},
 579         /* Index 0x74~0x77 */
 580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 581                                                                      0x1C,
 582                                                                      0x00},
 583         /* Index 0x78~0x7B */
 584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 585                                                                      0x1C,
 586                                                                      0x15},
 587         /* Index 0x7C~0x7F */
 588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 589                                                                      0x07,
 590                                                                      0x1C},
 591         /* Index 0x80~0x83 */
 592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 593                                                                      0x0E,
 594                                                                      0x1C},
 595         /* Index 0x84~0x87 */
 596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 597                                                                      0x0E,
 598                                                                      0x11},
 599         /* Index 0x88~0x8B */
 600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 601                                                                      0x18,
 602                                                                      0x0E},
 603         /* Index 0x8C~0x8F */
 604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 605                                                                      0x1C,
 606                                                                      0x0E},
 607         /* Index 0x90~0x93 */
 608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 609                                                                      0x1C,
 610                                                                      0x18},
 611         /* Index 0x94~0x97 */
 612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 613                                                                      0x11,
 614                                                                      0x1C},
 615         /* Index 0x98~0x9B */
 616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 617                                                                      0x14,
 618                                                                      0x1C},
 619         /* Index 0x9C~0x9F */
 620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 621                                                                      0x14,
 622                                                                      0x16},
 623         /* Index 0xA0~0xA3 */
 624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 625                                                                      0x1A,
 626                                                                      0x14},
 627         /* Index 0xA4~0xA7 */
 628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 629                                                                      0x1C,
 630                                                                      0x14},
 631         /* Index 0xA8~0xAB */
 632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 633                                                                      0x1C,
 634                                                                      0x1A},
 635         /* Index 0xAC~0xAF */
 636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 637                                                                      0x16,
 638                                                                      0x1C},
 639         /* Index 0xB0~0xB3 */
 640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 641                                                                      0x00,
 642                                                                      0x10},
 643         /* Index 0xB4~0xB7 */
 644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 645                                                                      0x00,
 646                                                                      0x04},
 647         /* Index 0xB8~0xBB */
 648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 649                                                                      0x0C,
 650                                                                      0x00},
 651         /* Index 0xBC~0xBF */
 652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 653                                                                      0x10,
 654                                                                      0x00},
 655         /* Index 0xC0~0xC3 */
 656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 657                                                                      0x10,
 658                                                                      0x0C},
 659         /* Index 0xC4~0xC7 */
 660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 661                                                                      0x04,
 662                                                                      0x10},
 663         /* Index 0xC8~0xCB */
 664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 665                                                                      0x08,
 666                                                                      0x10},
 667         /* Index 0xCC~0xCF */
 668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 669                                                                      0x08,
 670                                                                      0x0A},
 671         /* Index 0xD0~0xD3 */
 672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 673                                                                      0x0E,
 674                                                                      0x08},
 675         /* Index 0xD4~0xD7 */
 676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 677                                                                      0x10,
 678                                                                      0x08},
 679         /* Index 0xD8~0xDB */
 680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 681                                                                      0x10,
 682                                                                      0x0E},
 683         /* Index 0xDC~0xDF */
 684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 685                                                                      0x0A,
 686                                                                      0x10},
 687         /* Index 0xE0~0xE3 */
 688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 689                                                                      0x0B,
 690                                                                      0x10},
 691         /* Index 0xE4~0xE7 */
 692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 693                                                                      0x0B,
 694                                                                      0x0C},
 695         /* Index 0xE8~0xEB */
 696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 697                                                                      0x0F,
 698                                                                      0x0B},
 699         /* Index 0xEC~0xEF */
 700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 701                                                                      0x10,
 702                                                                      0x0B},
 703         /* Index 0xF0~0xF3 */
 704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 705                                                                      0x10,
 706                                                                      0x0F},
 707         /* Index 0xF4~0xF7 */
 708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 709                                                                      0x0C,
 710                                                                      0x10},
 711         /* Index 0xF8~0xFB */
 712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 713                                                                      0x00,
 714                                                                      0x00},
 715         /* Index 0xFC~0xFF */
 716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 717                                                                      0x00,
 718                                                                      0x00}
 719 };
 720
 721 static void set_crt_output_path(int set_iga);
 722 static void dvi_patch_skew_dvp0(void);
 723 static void dvi_patch_skew_dvp1(void);
 724 static void dvi_patch_skew_dvp_low(void);
 725 static void set_dvi_output_path(int set_iga, int output_interface);
 726 static void set_lcd_output_path(int set_iga, int output_interface);
 727 static void load_fix_bit_crtc_reg(void);
 728 static void init_gfx_chip_info(int chip_type);
 729 static void init_tmds_chip_info(void);
 730 static void init_lvds_chip_info(void);
 731 static void device_screen_off(void);
 732 static void device_screen_on(void);
 733 static void set_display_channel(void);
 734 static void device_off(void);
 735 static void device_on(void);
 736 static void enable_second_display_channel(void);
 737 static void disable_second_display_channel(void);
 738
 739 void viafb_lock_crt(void)
 740 {
 741         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 742 }
 743
 744 void viafb_unlock_crt(void)
 745 {
 746         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 747         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 748 }
 749
 750 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 751 {
 752         outb(index, LUT_INDEX_WRITE);
 753         outb(r, LUT_DATA);
 754         outb(g, LUT_DATA);
 755         outb(b, LUT_DATA);
 756 }
 757
 758 /*Set IGA path for each device*/
 759 void viafb_set_iga_path(void)
 760 {
 761
 762         if (viafb_SAMM_ON == 1) {
 763                 if (viafb_CRT_ON) {
 764                         if (viafb_primary_dev == CRT_Device)
 765                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 766                         else
 767                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 768                 }
 769
 770                 if (viafb_DVI_ON) {
 771                         if (viafb_primary_dev == DVI_Device)
 772                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 773                         else
 774                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 775                 }
 776
 777                 if (viafb_LCD_ON) {
 778                         if (viafb_primary_dev == LCD_Device) {
 779                                 if (viafb_dual_fb &&
 780                                         (viaparinfo->chip_info->gfx_chip_name ==
 781                                         UNICHROME_CLE266)) {
 782                                         viaparinfo->
 783                                         lvds_setting_info->iga_path = IGA2;
 784                                         viaparinfo->
 785                                         crt_setting_info->iga_path = IGA1;
 786                                         viaparinfo->
 787                                         tmds_setting_info->iga_path = IGA1;
 788                                 } else
 789                                         viaparinfo->
 790                                         lvds_setting_info->iga_path = IGA1;
 791                         } else {
 792                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 793                         }
 794                 }
 795                 if (viafb_LCD2_ON) {
 796                         if (LCD2_Device == viafb_primary_dev)
 797                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 798                         else
 799                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 800                 }
 801         } else {
 802                 viafb_SAMM_ON = 0;
 803
 804                 if (viafb_CRT_ON && viafb_LCD_ON) {
 805                         viaparinfo->crt_setting_info->iga_path = IGA1;
 806                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 807                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 808                         viaparinfo->crt_setting_info->iga_path = IGA1;
 809                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 810                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 811                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 812                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 813                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 814                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 815                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 816                 } else if (viafb_CRT_ON) {
 817                         viaparinfo->crt_setting_info->iga_path = IGA1;
 818                 } else if (viafb_LCD_ON) {
 819                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 820                 } else if (viafb_DVI_ON) {
 821                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 822                 }
 823         }
 824 }
 825
 826 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 827 {
 828         outb(0xFF, 0x3C6); /* bit mask of palette */
 829         outb(index, 0x3C8);
 830         outb(red, 0x3C9);
 831         outb(green, 0x3C9);
 832         outb(blue, 0x3C9);
 833 }
 834
 835 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 836 {
 837         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 838         set_color_register(index, red, green, blue);
 839 }
 840
 841 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 842 {
 843         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 844         set_color_register(index, red, green, blue);
 845 }
 846
 847 void viafb_set_output_path(int device, int set_iga, int output_interface)
 848 {
 849         switch (device) {
 850         case DEVICE_CRT:
 851                 set_crt_output_path(set_iga);
 852                 break;
 853         case DEVICE_DVI:
 854                 set_dvi_output_path(set_iga, output_interface);
 855                 break;
 856         case DEVICE_LCD:
 857                 set_lcd_output_path(set_iga, output_interface);
 858                 break;
 859         }
 860 }
 861
 862 static void set_crt_output_path(int set_iga)
 863 {
 864         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 865
 866         switch (set_iga) {
 867         case IGA1:
 868                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 869                 break;
 870         case IGA2:
 871                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 872                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 873                 break;
 874         }
 875 }
 876
 877 static void dvi_patch_skew_dvp0(void)
 878 {
 879         /* Reset data driving first: */
 880         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 881         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 882
 883         switch (viaparinfo->chip_info->gfx_chip_name) {
 884         case UNICHROME_P4M890:
 885                 {
 886                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 887                                 (viaparinfo->tmds_setting_info->v_active ==
 888                                 1200))
 889                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 890                                                BIT0 + BIT1 + BIT2);
 891                         else
 892                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 893                                                BIT0 + BIT1 + BIT2);
 894                         break;
 895                 }
 896
 897         case UNICHROME_P4M900:
 898                 {
 899                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 900                                        BIT0 + BIT1 + BIT2 + BIT3);
 901                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 902                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 903                         break;
 904                 }
 905
 906         default:
 907                 {
 908                         break;
 909                 }
 910         }
 911 }
 912
 913 static void dvi_patch_skew_dvp1(void)
 914 {
 915         switch (viaparinfo->chip_info->gfx_chip_name) {
 916         case UNICHROME_CX700:
 917                 {
 918                         break;
 919                 }
 920
 921         default:
 922                 {
 923                         break;
 924                 }
 925         }
 926 }
 927
 928 static void dvi_patch_skew_dvp_low(void)
 929 {
 930         switch (viaparinfo->chip_info->gfx_chip_name) {
 931         case UNICHROME_K8M890:
 932                 {
 933                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 934                         break;
 935                 }
 936
 937         case UNICHROME_P4M900:
 938                 {
 939                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 940                                        BIT0 + BIT1 + BIT2 + BIT3);
 941                         break;
 942                 }
 943
 944         case UNICHROME_P4M890:
 945                 {
 946                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 947                                        BIT0 + BIT1 + BIT2 + BIT3);
 948                         break;
 949                 }
 950
 951         default:
 952                 {
 953                         break;
 954                 }
 955         }
 956 }
 957
 958 static void set_dvi_output_path(int set_iga, int output_interface)
 959 {
 960         switch (output_interface) {
 961         case INTERFACE_DVP0:
 962                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 963
 964                 if (set_iga == IGA1) {
 965                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 966                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 967                                 BIT5 + BIT7);
 968                 } else {
 969                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 970                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 971                                 BIT5 + BIT7);
 972                 }
 973
 974                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 975
 976                 dvi_patch_skew_dvp0();
 977                 break;
 978
 979         case INTERFACE_DVP1:
 980                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 981                         if (set_iga == IGA1)
 982                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 983                                                BIT0 + BIT5 + BIT7);
 984                         else
 985                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 986                                                BIT0 + BIT5 + BIT7);
 987                 } else {
 988                         if (set_iga == IGA1)
 989                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 990                         else
 991                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 992                 }
 993
 994                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 995                 dvi_patch_skew_dvp1();
 996                 break;
 997         case INTERFACE_DFP_HIGH:
 998                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 999                         if (set_iga == IGA1) {
1000                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1001                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
1002                                                BIT0 + BIT1 + BIT4);
1003                         } else {
1004                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1005                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
1006                                                BIT0 + BIT1 + BIT4);
1007                         }
1008                 }
1009                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
1010                 break;
1011
1012         case INTERFACE_DFP_LOW:
1013                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1014                         break;
1015
1016                 if (set_iga == IGA1) {
1017                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1018                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1019                 } else {
1020                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1021                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1022                 }
1023
1024                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
1025                 dvi_patch_skew_dvp_low();
1026                 break;
1027
1028         case INTERFACE_TMDS:
1029                 if (set_iga == IGA1)
1030                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1031                 else
1032                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1033                 break;
1034         }
1035
1036         if (set_iga == IGA2) {
1037                 enable_second_display_channel();
1038                 /* Disable LCD Scaling */
1039                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1040         }
1041 }
1042
1043 static void set_lcd_output_path(int set_iga, int output_interface)
1044 {
1045         DEBUG_MSG(KERN_INFO
1046                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
1047                   set_iga, output_interface);
1048         switch (set_iga) {
1049         case IGA1:
1050                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1051                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1052
1053                 disable_second_display_channel();
1054                 break;
1055
1056         case IGA2:
1057                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1058                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1059
1060                 enable_second_display_channel();
1061                 break;
1062         }
1063
1064         switch (output_interface) {
1065         case INTERFACE_DVP0:
1066                 if (set_iga == IGA1) {
1067                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1068                 } else {
1069                         viafb_write_reg(CR91, VIACR, 0x00);
1070                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1071                 }
1072                 break;
1073
1074         case INTERFACE_DVP1:
1075                 if (set_iga == IGA1)
1076                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1077                 else {
1078                         viafb_write_reg(CR91, VIACR, 0x00);
1079                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1080                 }
1081                 break;
1082
1083         case INTERFACE_DFP_HIGH:
1084                 if (set_iga == IGA1)
1085                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1086                 else {
1087                         viafb_write_reg(CR91, VIACR, 0x00);
1088                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1089                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1090                 }
1091                 break;
1092
1093         case INTERFACE_DFP_LOW:
1094                 if (set_iga == IGA1)
1095                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1096                 else {
1097                         viafb_write_reg(CR91, VIACR, 0x00);
1098                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1099                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1100                 }
1101
1102                 break;
1103
1104         case INTERFACE_DFP:
1105                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1106                     || (UNICHROME_P4M890 ==
1107                     viaparinfo->chip_info->gfx_chip_name))
1108                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1109                                        BIT7 + BIT2 + BIT1 + BIT0);
1110                 if (set_iga == IGA1) {
1111                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1112                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1113                 } else {
1114                         viafb_write_reg(CR91, VIACR, 0x00);
1115                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1116                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1117                 }
1118                 break;
1119
1120         case INTERFACE_LVDS0:
1121         case INTERFACE_LVDS0LVDS1:
1122                 if (set_iga == IGA1)
1123                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1124                 else
1125                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1126
1127                 break;
1128
1129         case INTERFACE_LVDS1:
1130                 if (set_iga == IGA1)
1131                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1132                 else
1133                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1134                 break;
1135         }
1136 }
1137
1138 static void load_fix_bit_crtc_reg(void)
1139 {
1140         /* always set to 1 */
1141         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1142         /* line compare should set all bits = 1 (extend modes) */
1143         viafb_write_reg(CR18, VIACR, 0xff);
1144         /* line compare should set all bits = 1 (extend modes) */
1145         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1146         /* line compare should set all bits = 1 (extend modes) */
1147         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1148         /* line compare should set all bits = 1 (extend modes) */
1149         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1150         /* line compare should set all bits = 1 (extend modes) */
1151         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1152         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1153         /* extend mode always set to e3h */
1154         viafb_write_reg(CR17, VIACR, 0xe3);
1155         /* extend mode always set to 0h */
1156         viafb_write_reg(CR08, VIACR, 0x00);
1157         /* extend mode always set to 0h */
1158         viafb_write_reg(CR14, VIACR, 0x00);
1159
1160         /* If K8M800, enable Prefetch Mode. */
1161         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1162                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1163                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1164         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1165             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1166                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1167
1168 }
1169
1170 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1171         struct io_register *reg,
1172               int io_type)
1173 {
1174         int reg_mask;
1175         int bit_num = 0;
1176         int data;
1177         int i, j;
1178         int shift_next_reg;
1179         int start_index, end_index, cr_index;
1180         u16 get_bit;
1181
1182         for (i = 0; i < viafb_load_reg_num; i++) {
1183                 reg_mask = 0;
1184                 data = 0;
1185                 start_index = reg[i].start_bit;
1186                 end_index = reg[i].end_bit;
1187                 cr_index = reg[i].io_addr;
1188
1189                 shift_next_reg = bit_num;
1190                 for (j = start_index; j <= end_index; j++) {
1191                         /*if (bit_num==8) timing_value = timing_value >>8; */
1192                         reg_mask = reg_mask | (BIT0 << j);
1193                         get_bit = (timing_value & (BIT0 << bit_num));
1194                         data =
1195                             data | ((get_bit >> shift_next_reg) << start_index);
1196                         bit_num++;
1197                 }
1198                 if (io_type == VIACR)
1199                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1200                 else
1201                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1202         }
1203
1204 }
1205
1206 /* Write Registers */
1207 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1208 {
1209         int i;
1210
1211         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1212
1213         for (i = 0; i < ItemNum; i++)
1214                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1215                         RegTable[i].value, RegTable[i].mask);
1216 }
1217
1218 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1219 {
1220         int reg_value;
1221         int viafb_load_reg_num;
1222         struct io_register *reg = NULL;
1223
1224         switch (set_iga) {
1225         case IGA1:
1226                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1227                 viafb_load_reg_num = fetch_count_reg.
1228                         iga1_fetch_count_reg.reg_num;
1229                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1230                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1231                 break;
1232         case IGA2:
1233                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1234                 viafb_load_reg_num = fetch_count_reg.
1235                         iga2_fetch_count_reg.reg_num;
1236                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1237                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1238                 break;
1239         }
1240
1241 }
1242
1243 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1244 {
1245         int reg_value;
1246         int viafb_load_reg_num;
1247         struct io_register *reg = NULL;
1248         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1249             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1250         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1251             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1252
1253         if (set_iga == IGA1) {
1254                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1255                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1256                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1257                         iga1_fifo_high_threshold =
1258                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1259                         /* If resolution > 1280x1024, expire length = 64, else
1260                            expire length = 128 */
1261                         if ((hor_active > 1280) && (ver_active > 1024))
1262                                 iga1_display_queue_expire_num = 16;
1263                         else
1264                                 iga1_display_queue_expire_num =
1265                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1266
1267                 }
1268
1269                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1270                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1271                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1272                         iga1_fifo_high_threshold =
1273                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1274                         iga1_display_queue_expire_num =
1275                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1276
1277                         /* If resolution > 1280x1024, expire length = 64, else
1278                            expire length = 128 */
1279                         if ((hor_active > 1280) && (ver_active > 1024))
1280                                 iga1_display_queue_expire_num = 16;
1281                         else
1282                                 iga1_display_queue_expire_num =
1283                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1284                 }
1285
1286                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1287                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1288                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1289                         iga1_fifo_high_threshold =
1290                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1291
1292                         /* If resolution > 1280x1024, expire length = 64,
1293                            else expire length = 128 */
1294                         if ((hor_active > 1280) && (ver_active > 1024))
1295                                 iga1_display_queue_expire_num = 16;
1296                         else
1297                                 iga1_display_queue_expire_num =
1298                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1299                 }
1300
1301                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1302                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1303                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1304                         iga1_fifo_high_threshold =
1305                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1306                         iga1_display_queue_expire_num =
1307                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1308                 }
1309
1310                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1311                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1312                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1313                         iga1_fifo_high_threshold =
1314                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1315                         iga1_display_queue_expire_num =
1316                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1317                 }
1318
1319                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1320                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1321                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1322                         iga1_fifo_high_threshold =
1323                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1324                         iga1_display_queue_expire_num =
1325                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1326                 }
1327
1328                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1329                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1330                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1331                         iga1_fifo_high_threshold =
1332                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1333                         iga1_display_queue_expire_num =
1334                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1335                 }
1336
1337                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1338                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1339                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1340                         iga1_fifo_high_threshold =
1341                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1342                         iga1_display_queue_expire_num =
1343                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1344                 }
1345
1346                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1347                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1348                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1349                         iga1_fifo_high_threshold =
1350                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1351                         iga1_display_queue_expire_num =
1352                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1353                 }
1354
1355                 /* Set Display FIFO Depath Select */
1356                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1357                 viafb_load_reg_num =
1358                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1359                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1360                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1361
1362                 /* Set Display FIFO Threshold Select */
1363                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1364                 viafb_load_reg_num =
1365                     fifo_threshold_select_reg.
1366                     iga1_fifo_threshold_select_reg.reg_num;
1367                 reg =
1368                     fifo_threshold_select_reg.
1369                     iga1_fifo_threshold_select_reg.reg;
1370                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1371
1372                 /* Set FIFO High Threshold Select */
1373                 reg_value =
1374                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1375                 viafb_load_reg_num =
1376                     fifo_high_threshold_select_reg.
1377                     iga1_fifo_high_threshold_select_reg.reg_num;
1378                 reg =
1379                     fifo_high_threshold_select_reg.
1380                     iga1_fifo_high_threshold_select_reg.reg;
1381                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1382
1383                 /* Set Display Queue Expire Num */
1384                 reg_value =
1385                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1386                     (iga1_display_queue_expire_num);
1387                 viafb_load_reg_num =
1388                     display_queue_expire_num_reg.
1389                     iga1_display_queue_expire_num_reg.reg_num;
1390                 reg =
1391                     display_queue_expire_num_reg.
1392                     iga1_display_queue_expire_num_reg.reg;
1393                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1394
1395         } else {
1396                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1397                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1398                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1399                         iga2_fifo_high_threshold =
1400                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1401
1402                         /* If resolution > 1280x1024, expire length = 64,
1403                            else  expire length = 128 */
1404                         if ((hor_active > 1280) && (ver_active > 1024))
1405                                 iga2_display_queue_expire_num = 16;
1406                         else
1407                                 iga2_display_queue_expire_num =
1408                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1409                 }
1410
1411                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1412                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1413                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1414                         iga2_fifo_high_threshold =
1415                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1416
1417                         /* If resolution > 1280x1024, expire length = 64,
1418                            else  expire length = 128 */
1419                         if ((hor_active > 1280) && (ver_active > 1024))
1420                                 iga2_display_queue_expire_num = 16;
1421                         else
1422                                 iga2_display_queue_expire_num =
1423                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1424                 }
1425
1426                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1427                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1428                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1429                         iga2_fifo_high_threshold =
1430                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1431
1432                         /* If resolution > 1280x1024, expire length = 64,
1433                            else expire length = 128 */
1434                         if ((hor_active > 1280) && (ver_active > 1024))
1435                                 iga2_display_queue_expire_num = 16;
1436                         else
1437                                 iga2_display_queue_expire_num =
1438                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1439                 }
1440
1441                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1442                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1443                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1444                         iga2_fifo_high_threshold =
1445                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1446                         iga2_display_queue_expire_num =
1447                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1448                 }
1449
1450                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1451                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1452                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1453                         iga2_fifo_high_threshold =
1454                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1455                         iga2_display_queue_expire_num =
1456                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1457                 }
1458
1459                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1460                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1461                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1462                         iga2_fifo_high_threshold =
1463                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1464                         iga2_display_queue_expire_num =
1465                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1466                 }
1467
1468                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1469                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1470                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1471                         iga2_fifo_high_threshold =
1472                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1473                         iga2_display_queue_expire_num =
1474                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1475                 }
1476
1477                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1478                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1479                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1480                         iga2_fifo_high_threshold =
1481                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1482                         iga2_display_queue_expire_num =
1483                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1484                 }
1485
1486                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1487                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1488                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1489                         iga2_fifo_high_threshold =
1490                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1491                         iga2_display_queue_expire_num =
1492                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1493                 }
1494
1495                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1496                         /* Set Display FIFO Depath Select */
1497                         reg_value =
1498                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1499                             - 1;
1500                         /* Patch LCD in IGA2 case */
1501                         viafb_load_reg_num =
1502                             display_fifo_depth_reg.
1503                             iga2_fifo_depth_select_reg.reg_num;
1504                         reg =
1505                             display_fifo_depth_reg.
1506                             iga2_fifo_depth_select_reg.reg;
1507                         viafb_load_reg(reg_value,
1508                                 viafb_load_reg_num, reg, VIACR);
1509                 } else {
1510
1511                         /* Set Display FIFO Depath Select */
1512                         reg_value =
1513                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1514                         viafb_load_reg_num =
1515                             display_fifo_depth_reg.
1516                             iga2_fifo_depth_select_reg.reg_num;
1517                         reg =
1518                             display_fifo_depth_reg.
1519                             iga2_fifo_depth_select_reg.reg;
1520                         viafb_load_reg(reg_value,
1521                                 viafb_load_reg_num, reg, VIACR);
1522                 }
1523
1524                 /* Set Display FIFO Threshold Select */
1525                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1526                 viafb_load_reg_num =
1527                     fifo_threshold_select_reg.
1528                     iga2_fifo_threshold_select_reg.reg_num;
1529                 reg =
1530                     fifo_threshold_select_reg.
1531                     iga2_fifo_threshold_select_reg.reg;
1532                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1533
1534                 /* Set FIFO High Threshold Select */
1535                 reg_value =
1536                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1537                 viafb_load_reg_num =
1538                     fifo_high_threshold_select_reg.
1539                     iga2_fifo_high_threshold_select_reg.reg_num;
1540                 reg =
1541                     fifo_high_threshold_select_reg.
1542                     iga2_fifo_high_threshold_select_reg.reg;
1543                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1544
1545                 /* Set Display Queue Expire Num */
1546                 reg_value =
1547                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1548                     (iga2_display_queue_expire_num);
1549                 viafb_load_reg_num =
1550                     display_queue_expire_num_reg.
1551                     iga2_display_queue_expire_num_reg.reg_num;
1552                 reg =
1553                     display_queue_expire_num_reg.
1554                     iga2_display_queue_expire_num_reg.reg;
1555                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1556
1557         }
1558
1559 }
1560
1561 static u32 cle266_encode_pll(struct pll_config pll)
1562 {
1563         return (pll.multiplier << 8)
1564                 | (pll.rshift << 6)
1565                 | pll.divisor;
1566 }
1567
1568 static u32 k800_encode_pll(struct pll_config pll)
1569 {
1570         return ((pll.divisor - 2) << 16)
1571                 | (pll.rshift << 10)
1572                 | (pll.multiplier - 2);
1573 }
1574
1575 static u32 vx855_encode_pll(struct pll_config pll)
1576 {
1577         return (pll.divisor << 16)
1578                 | (pll.rshift << 10)
1579                 | pll.multiplier;
1580 }
1581
1582 u32 viafb_get_clk_value(int clk)
1583 {
1584         u32 value = 0;
1585         int i = 0;
1586
1587         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1588                 i++;
1589
1590         if (i == NUM_TOTAL_PLL_TABLE) {
1591                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1592         } else {
1593                 switch (viaparinfo->chip_info->gfx_chip_name) {
1594                 case UNICHROME_CLE266:
1595                 case UNICHROME_K400:
1596                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1597                         break;
1598
1599                 case UNICHROME_K800:
1600                 case UNICHROME_PM800:
1601                 case UNICHROME_CN700:
1602                         value = k800_encode_pll(pll_value[i].k800_pll);
1603                         break;
1604
1605                 case UNICHROME_CX700:
1606                 case UNICHROME_CN750:
1607                 case UNICHROME_K8M890:
1608                 case UNICHROME_P4M890:
1609                 case UNICHROME_P4M900:
1610                 case UNICHROME_VX800:
1611                         value = k800_encode_pll(pll_value[i].cx700_pll);
1612                         break;
1613
1614                 case UNICHROME_VX855:
1615                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1616                         break;
1617                 }
1618         }
1619
1620         return value;
1621 }
1622
1623 /* Set VCLK*/
1624 void viafb_set_vclock(u32 clk, int set_iga)
1625 {
1626         /* H.W. Reset : ON */
1627         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1628
1629         if (set_iga == IGA1) {
1630                 /* Change D,N FOR VCLK */
1631                 switch (viaparinfo->chip_info->gfx_chip_name) {
1632                 case UNICHROME_CLE266:
1633                 case UNICHROME_K400:
1634                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1635                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1636                         break;
1637
1638                 case UNICHROME_K800:
1639                 case UNICHROME_PM800:
1640                 case UNICHROME_CN700:
1641                 case UNICHROME_CX700:
1642                 case UNICHROME_CN750:
1643                 case UNICHROME_K8M890:
1644                 case UNICHROME_P4M890:
1645                 case UNICHROME_P4M900:
1646                 case UNICHROME_VX800:
1647                 case UNICHROME_VX855:
1648                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1649                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1650                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1651                         break;
1652                 }
1653         }
1654
1655         if (set_iga == IGA2) {
1656                 /* Change D,N FOR LCK */
1657                 switch (viaparinfo->chip_info->gfx_chip_name) {
1658                 case UNICHROME_CLE266:
1659                 case UNICHROME_K400:
1660                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1661                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1662                         break;
1663
1664                 case UNICHROME_K800:
1665                 case UNICHROME_PM800:
1666                 case UNICHROME_CN700:
1667                 case UNICHROME_CX700:
1668                 case UNICHROME_CN750:
1669                 case UNICHROME_K8M890:
1670                 case UNICHROME_P4M890:
1671                 case UNICHROME_P4M900:
1672                 case UNICHROME_VX800:
1673                 case UNICHROME_VX855:
1674                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1675                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1676                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1677                         break;
1678                 }
1679         }
1680
1681         /* H.W. Reset : OFF */
1682         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1683
1684         /* Reset PLL */
1685         if (set_iga == IGA1) {
1686                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1687                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1688         }
1689
1690         if (set_iga == IGA2) {
1691                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1692                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1693         }
1694
1695         /* Fire! */
1696         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1697 }
1698
1699 void viafb_load_crtc_timing(struct display_timing device_timing,
1700         int set_iga)
1701 {
1702         int i;
1703         int viafb_load_reg_num = 0;
1704         int reg_value = 0;
1705         struct io_register *reg = NULL;
1706
1707         viafb_unlock_crt();
1708
1709         for (i = 0; i < 12; i++) {
1710                 if (set_iga == IGA1) {
1711                         switch (i) {
1712                         case H_TOTAL_INDEX:
1713                                 reg_value =
1714                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1715                                                            hor_total);
1716                                 viafb_load_reg_num =
1717                                         iga1_crtc_reg.hor_total.reg_num;
1718                                 reg = iga1_crtc_reg.hor_total.reg;
1719                                 break;
1720                         case H_ADDR_INDEX:
1721                                 reg_value =
1722                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1723                                                           hor_addr);
1724                                 viafb_load_reg_num =
1725                                         iga1_crtc_reg.hor_addr.reg_num;
1726                                 reg = iga1_crtc_reg.hor_addr.reg;
1727                                 break;
1728                         case H_BLANK_START_INDEX:
1729                                 reg_value =
1730                                     IGA1_HOR_BLANK_START_FORMULA
1731                                     (device_timing.hor_blank_start);
1732                                 viafb_load_reg_num =
1733                                     iga1_crtc_reg.hor_blank_start.reg_num;
1734                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1735                                 break;
1736                         case H_BLANK_END_INDEX:
1737                                 reg_value =
1738                                     IGA1_HOR_BLANK_END_FORMULA
1739                                     (device_timing.hor_blank_start,
1740                                      device_timing.hor_blank_end);
1741                                 viafb_load_reg_num =
1742                                     iga1_crtc_reg.hor_blank_end.reg_num;
1743                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1744                                 break;
1745                         case H_SYNC_START_INDEX:
1746                                 reg_value =
1747                                     IGA1_HOR_SYNC_START_FORMULA
1748                                     (device_timing.hor_sync_start);
1749                                 viafb_load_reg_num =
1750                                     iga1_crtc_reg.hor_sync_start.reg_num;
1751                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1752                                 break;
1753                         case H_SYNC_END_INDEX:
1754                                 reg_value =
1755                                     IGA1_HOR_SYNC_END_FORMULA
1756                                     (device_timing.hor_sync_start,
1757                                      device_timing.hor_sync_end);
1758                                 viafb_load_reg_num =
1759                                     iga1_crtc_reg.hor_sync_end.reg_num;
1760                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1761                                 break;
1762                         case V_TOTAL_INDEX:
1763                                 reg_value =
1764                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1765                                                            ver_total);
1766                                 viafb_load_reg_num =
1767                                         iga1_crtc_reg.ver_total.reg_num;
1768                                 reg = iga1_crtc_reg.ver_total.reg;
1769                                 break;
1770                         case V_ADDR_INDEX:
1771                                 reg_value =
1772                                     IGA1_VER_ADDR_FORMULA(device_timing.
1773                                                           ver_addr);
1774                                 viafb_load_reg_num =
1775                                         iga1_crtc_reg.ver_addr.reg_num;
1776                                 reg = iga1_crtc_reg.ver_addr.reg;
1777                                 break;
1778                         case V_BLANK_START_INDEX:
1779                                 reg_value =
1780                                     IGA1_VER_BLANK_START_FORMULA
1781                                     (device_timing.ver_blank_start);
1782                                 viafb_load_reg_num =
1783                                     iga1_crtc_reg.ver_blank_start.reg_num;
1784                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1785                                 break;
1786                         case V_BLANK_END_INDEX:
1787                                 reg_value =
1788                                     IGA1_VER_BLANK_END_FORMULA
1789                                     (device_timing.ver_blank_start,
1790                                      device_timing.ver_blank_end);
1791                                 viafb_load_reg_num =
1792                                     iga1_crtc_reg.ver_blank_end.reg_num;
1793                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1794                                 break;
1795                         case V_SYNC_START_INDEX:
1796                                 reg_value =
1797                                     IGA1_VER_SYNC_START_FORMULA
1798                                     (device_timing.ver_sync_start);
1799                                 viafb_load_reg_num =
1800                                     iga1_crtc_reg.ver_sync_start.reg_num;
1801                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1802                                 break;
1803                         case V_SYNC_END_INDEX:
1804                                 reg_value =
1805                                     IGA1_VER_SYNC_END_FORMULA
1806                                     (device_timing.ver_sync_start,
1807                                      device_timing.ver_sync_end);
1808                                 viafb_load_reg_num =
1809                                     iga1_crtc_reg.ver_sync_end.reg_num;
1810                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1811                                 break;
1812
1813                         }
1814                 }
1815
1816                 if (set_iga == IGA2) {
1817                         switch (i) {
1818                         case H_TOTAL_INDEX:
1819                                 reg_value =
1820                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1821                                                            hor_total);
1822                                 viafb_load_reg_num =
1823                                         iga2_crtc_reg.hor_total.reg_num;
1824                                 reg = iga2_crtc_reg.hor_total.reg;
1825                                 break;
1826                         case H_ADDR_INDEX:
1827                                 reg_value =
1828                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1829                                                           hor_addr);
1830                                 viafb_load_reg_num =
1831                                         iga2_crtc_reg.hor_addr.reg_num;
1832                                 reg = iga2_crtc_reg.hor_addr.reg;
1833                                 break;
1834                         case H_BLANK_START_INDEX:
1835                                 reg_value =
1836                                     IGA2_HOR_BLANK_START_FORMULA
1837                                     (device_timing.hor_blank_start);
1838                                 viafb_load_reg_num =
1839                                     iga2_crtc_reg.hor_blank_start.reg_num;
1840                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1841                                 break;
1842                         case H_BLANK_END_INDEX:
1843                                 reg_value =
1844                                     IGA2_HOR_BLANK_END_FORMULA
1845                                     (device_timing.hor_blank_start,
1846                                      device_timing.hor_blank_end);
1847                                 viafb_load_reg_num =
1848                                     iga2_crtc_reg.hor_blank_end.reg_num;
1849                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1850                                 break;
1851                         case H_SYNC_START_INDEX:
1852                                 reg_value =
1853                                     IGA2_HOR_SYNC_START_FORMULA
1854                                     (device_timing.hor_sync_start);
1855                                 if (UNICHROME_CN700 <=
1856                                         viaparinfo->chip_info->gfx_chip_name)
1857                                         viafb_load_reg_num =
1858                                             iga2_crtc_reg.hor_sync_start.
1859                                             reg_num;
1860                                 else
1861                                         viafb_load_reg_num = 3;
1862                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1863                                 break;
1864                         case H_SYNC_END_INDEX:
1865                                 reg_value =
1866                                     IGA2_HOR_SYNC_END_FORMULA
1867                                     (device_timing.hor_sync_start,
1868                                      device_timing.hor_sync_end);
1869                                 viafb_load_reg_num =
1870                                     iga2_crtc_reg.hor_sync_end.reg_num;
1871                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1872                                 break;
1873                         case V_TOTAL_INDEX:
1874                                 reg_value =
1875                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1876                                                            ver_total);
1877                                 viafb_load_reg_num =
1878                                         iga2_crtc_reg.ver_total.reg_num;
1879                                 reg = iga2_crtc_reg.ver_total.reg;
1880                                 break;
1881                         case V_ADDR_INDEX:
1882                                 reg_value =
1883                                     IGA2_VER_ADDR_FORMULA(device_timing.
1884                                                           ver_addr);
1885                                 viafb_load_reg_num =
1886                                         iga2_crtc_reg.ver_addr.reg_num;
1887                                 reg = iga2_crtc_reg.ver_addr.reg;
1888                                 break;
1889                         case V_BLANK_START_INDEX:
1890                                 reg_value =
1891                                     IGA2_VER_BLANK_START_FORMULA
1892                                     (device_timing.ver_blank_start);
1893                                 viafb_load_reg_num =
1894                                     iga2_crtc_reg.ver_blank_start.reg_num;
1895                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1896                                 break;
1897                         case V_BLANK_END_INDEX:
1898                                 reg_value =
1899                                     IGA2_VER_BLANK_END_FORMULA
1900                                     (device_timing.ver_blank_start,
1901                                      device_timing.ver_blank_end);
1902                                 viafb_load_reg_num =
1903                                     iga2_crtc_reg.ver_blank_end.reg_num;
1904                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1905                                 break;
1906                         case V_SYNC_START_INDEX:
1907                                 reg_value =
1908                                     IGA2_VER_SYNC_START_FORMULA
1909                                     (device_timing.ver_sync_start);
1910                                 viafb_load_reg_num =
1911                                     iga2_crtc_reg.ver_sync_start.reg_num;
1912                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1913                                 break;
1914                         case V_SYNC_END_INDEX:
1915                                 reg_value =
1916                                     IGA2_VER_SYNC_END_FORMULA
1917                                     (device_timing.ver_sync_start,
1918                                      device_timing.ver_sync_end);
1919                                 viafb_load_reg_num =
1920                                     iga2_crtc_reg.ver_sync_end.reg_num;
1921                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1922                                 break;
1923
1924                         }
1925                 }
1926                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1927         }
1928
1929         viafb_lock_crt();
1930 }
1931
1932 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1933         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1934 {
1935         struct display_timing crt_reg;
1936         int i;
1937         int index = 0;
1938         int h_addr, v_addr;
1939         u32 pll_D_N;
1940         u8 polarity = 0;
1941
1942         for (i = 0; i < video_mode->mode_array; i++) {
1943                 index = i;
1944
1945                 if (crt_table[i].refresh_rate == viaparinfo->
1946                         crt_setting_info->refresh_rate)
1947                         break;
1948         }
1949
1950         crt_reg = crt_table[index].crtc;
1951
1952         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1953         /* So we would delete border. */
1954         if ((viafb_LCD_ON | viafb_DVI_ON)
1955             && video_mode->crtc[0].crtc.hor_addr == 640
1956             && video_mode->crtc[0].crtc.ver_addr == 480
1957             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1958                 /* The border is 8 pixels. */
1959                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1960
1961                 /* Blanking time should add left and right borders. */
1962                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1963         }
1964
1965         h_addr = crt_reg.hor_addr;
1966         v_addr = crt_reg.ver_addr;
1967
1968         /* update polarity for CRT timing */
1969         if (crt_table[index].h_sync_polarity == NEGATIVE)
1970                 polarity |= BIT6;
1971         if (crt_table[index].v_sync_polarity == NEGATIVE)
1972                 polarity |= BIT7;
1973         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1974
1975         if (set_iga == IGA1) {
1976                 viafb_unlock_crt();
1977                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1978                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1979                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1980         }
1981
1982         switch (set_iga) {
1983         case IGA1:
1984                 viafb_load_crtc_timing(crt_reg, IGA1);
1985                 break;
1986         case IGA2:
1987                 viafb_load_crtc_timing(crt_reg, IGA2);
1988                 break;
1989         }
1990
1991         load_fix_bit_crtc_reg();
1992         viafb_lock_crt();
1993         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1994         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1995
1996         /* load FIFO */
1997         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1998             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1999                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2000
2001         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
2002         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2003         viafb_set_vclock(pll_D_N, set_iga);
2004
2005 }
2006
2007 void viafb_init_chip_info(int chip_type)
2008 {
2009         init_gfx_chip_info(chip_type);
2010         init_tmds_chip_info();
2011         init_lvds_chip_info();
2012
2013         viaparinfo->crt_setting_info->iga_path = IGA1;
2014         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
2015
2016         /*Set IGA path for each device */
2017         viafb_set_iga_path();
2018
2019         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
2020         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
2021         viaparinfo->lvds_setting_info2->display_method =
2022                 viaparinfo->lvds_setting_info->display_method;
2023         viaparinfo->lvds_setting_info2->lcd_mode =
2024                 viaparinfo->lvds_setting_info->lcd_mode;
2025 }
2026
2027 void viafb_update_device_setting(int hres, int vres,
2028         int bpp, int vmode_refresh, int flag)
2029 {
2030         if (flag == 0) {
2031                 viaparinfo->crt_setting_info->h_active = hres;
2032                 viaparinfo->crt_setting_info->v_active = vres;
2033                 viaparinfo->crt_setting_info->bpp = bpp;
2034                 viaparinfo->crt_setting_info->refresh_rate =
2035                         vmode_refresh;
2036
2037                 viaparinfo->tmds_setting_info->h_active = hres;
2038                 viaparinfo->tmds_setting_info->v_active = vres;
2039
2040                 viaparinfo->lvds_setting_info->h_active = hres;
2041                 viaparinfo->lvds_setting_info->v_active = vres;
2042                 viaparinfo->lvds_setting_info->bpp = bpp;
2043                 viaparinfo->lvds_setting_info->refresh_rate =
2044                         vmode_refresh;
2045                 viaparinfo->lvds_setting_info2->h_active = hres;
2046                 viaparinfo->lvds_setting_info2->v_active = vres;
2047                 viaparinfo->lvds_setting_info2->bpp = bpp;
2048                 viaparinfo->lvds_setting_info2->refresh_rate =
2049                         vmode_refresh;
2050         } else {
2051
2052                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2053                         viaparinfo->tmds_setting_info->h_active = hres;
2054                         viaparinfo->tmds_setting_info->v_active = vres;
2055                 }
2056
2057                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2058                         viaparinfo->lvds_setting_info->h_active = hres;
2059                         viaparinfo->lvds_setting_info->v_active = vres;
2060                         viaparinfo->lvds_setting_info->bpp = bpp;
2061                         viaparinfo->lvds_setting_info->refresh_rate =
2062                                 vmode_refresh;
2063                 }
2064                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2065                         viaparinfo->lvds_setting_info2->h_active = hres;
2066                         viaparinfo->lvds_setting_info2->v_active = vres;
2067                         viaparinfo->lvds_setting_info2->bpp = bpp;
2068                         viaparinfo->lvds_setting_info2->refresh_rate =
2069                                 vmode_refresh;
2070                 }
2071         }
2072 }
2073
2074 static void init_gfx_chip_info(int chip_type)
2075 {
2076         u8 tmp;
2077
2078         viaparinfo->chip_info->gfx_chip_name = chip_type;
2079
2080         /* Check revision of CLE266 Chip */
2081         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2082                 /* CR4F only define in CLE266.CX chip */
2083                 tmp = viafb_read_reg(VIACR, CR4F);
2084                 viafb_write_reg(CR4F, VIACR, 0x55);
2085                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2086                         viaparinfo->chip_info->gfx_chip_revision =
2087                         CLE266_REVISION_AX;
2088                 else
2089                         viaparinfo->chip_info->gfx_chip_revision =
2090                         CLE266_REVISION_CX;
2091                 /* restore orignal CR4F value */
2092                 viafb_write_reg(CR4F, VIACR, tmp);
2093         }
2094
2095         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2096                 tmp = viafb_read_reg(VIASR, SR43);
2097                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2098                 if (tmp & 0x02) {
2099                         viaparinfo->chip_info->gfx_chip_revision =
2100                                 CX700_REVISION_700M2;
2101                 } else if (tmp & 0x40) {
2102                         viaparinfo->chip_info->gfx_chip_revision =
2103                                 CX700_REVISION_700M;
2104                 } else {
2105                         viaparinfo->chip_info->gfx_chip_revision =
2106                                 CX700_REVISION_700;
2107                 }
2108         }
2109
2110         /* Determine which 2D engine we have */
2111         switch (viaparinfo->chip_info->gfx_chip_name) {
2112         case UNICHROME_VX800:
2113         case UNICHROME_VX855:
2114                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2115                 break;
2116         case UNICHROME_K8M890:
2117         case UNICHROME_P4M900:
2118                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2119                 break;
2120         default:
2121                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2122                 break;
2123         }
2124 }
2125
2126 static void init_tmds_chip_info(void)
2127 {
2128         viafb_tmds_trasmitter_identify();
2129
2130         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2131                 output_interface) {
2132                 switch (viaparinfo->chip_info->gfx_chip_name) {
2133                 case UNICHROME_CX700:
2134                         {
2135                                 /* we should check support by hardware layout.*/
2136                                 if ((viafb_display_hardware_layout ==
2137                                      HW_LAYOUT_DVI_ONLY)
2138                                     || (viafb_display_hardware_layout ==
2139                                         HW_LAYOUT_LCD_DVI)) {
2140                                         viaparinfo->chip_info->tmds_chip_info.
2141                                             output_interface = INTERFACE_TMDS;
2142                                 } else {
2143                                         viaparinfo->chip_info->tmds_chip_info.
2144                                                 output_interface =
2145                                                 INTERFACE_NONE;
2146                                 }
2147                                 break;
2148                         }
2149                 case UNICHROME_K8M890:
2150                 case UNICHROME_P4M900:
2151                 case UNICHROME_P4M890:
2152                         /* TMDS on PCIE, we set DFPLOW as default. */
2153                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2154                             INTERFACE_DFP_LOW;
2155                         break;
2156                 default:
2157                         {
2158                                 /* set DVP1 default for DVI */
2159                                 viaparinfo->chip_info->tmds_chip_info
2160                                 .output_interface = INTERFACE_DVP1;
2161                         }
2162                 }
2163         }
2164
2165         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2166                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2167         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2168                 &viaparinfo->shared->tmds_setting_info);
2169 }
2170
2171 static void init_lvds_chip_info(void)
2172 {
2173         viafb_lvds_trasmitter_identify();
2174         viafb_init_lcd_size();
2175         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2176                                    viaparinfo->lvds_setting_info);
2177         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2178                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2179                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2180         }
2181         /*If CX700,two singel LCD, we need to reassign
2182            LCD interface to different LVDS port */
2183         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2184             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2185                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2186                         lvds_chip_name) && (INTEGRATED_LVDS ==
2187                         viaparinfo->chip_info->
2188                         lvds_chip_info2.lvds_chip_name)) {
2189                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2190                                 INTERFACE_LVDS0;
2191                         viaparinfo->chip_info->lvds_chip_info2.
2192                                 output_interface =
2193                             INTERFACE_LVDS1;
2194                 }
2195         }
2196
2197         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2198                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2199         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2200                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2201         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2202                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2203 }
2204
2205 void viafb_init_dac(int set_iga)
2206 {
2207         int i;
2208         u8 tmp;
2209
2210         if (set_iga == IGA1) {
2211                 /* access Primary Display's LUT */
2212                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2213                 /* turn off LCK */
2214                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2215                 for (i = 0; i < 256; i++) {
2216                         write_dac_reg(i, palLUT_table[i].red,
2217                                       palLUT_table[i].green,
2218                                       palLUT_table[i].blue);
2219                 }
2220                 /* turn on LCK */
2221                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2222         } else {
2223                 tmp = viafb_read_reg(VIACR, CR6A);
2224                 /* access Secondary Display's LUT */
2225                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2226                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2227                 for (i = 0; i < 256; i++) {
2228                         write_dac_reg(i, palLUT_table[i].red,
2229                                       palLUT_table[i].green,
2230                                       palLUT_table[i].blue);
2231                 }
2232                 /* set IGA1 DAC for default */
2233                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2234                 viafb_write_reg(CR6A, VIACR, tmp);
2235         }
2236 }
2237
2238 static void device_screen_off(void)
2239 {
2240         /* turn off CRT screen (IGA1) */
2241         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2242 }
2243
2244 static void device_screen_on(void)
2245 {
2246         /* turn on CRT screen (IGA1) */
2247         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2248 }
2249
2250 static void set_display_channel(void)
2251 {
2252         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2253         is keeped on lvds_setting_info2 */
2254         if (viafb_LCD2_ON &&
2255                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2256                 /* For dual channel LCD: */
2257                 /* Set to Dual LVDS channel. */
2258                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2259         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2260                 /* For LCD+DFP: */
2261                 /* Set to LVDS1 + TMDS channel. */
2262                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2263         } else if (viafb_DVI_ON) {
2264                 /* Set to single TMDS channel. */
2265                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2266         } else if (viafb_LCD_ON) {
2267                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2268                         /* For dual channel LCD: */
2269                         /* Set to Dual LVDS channel. */
2270                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2271                 } else {
2272                         /* Set to LVDS0 + LVDS1 channel. */
2273                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2274                 }
2275         }
2276 }
2277
2278 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2279         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2280 {
2281         int i, j;
2282         int port;
2283         u8 value, index, mask;
2284         struct crt_mode_table *crt_timing;
2285         struct crt_mode_table *crt_timing1 = NULL;
2286
2287         device_screen_off();
2288         crt_timing = vmode_tbl->crtc;
2289
2290         if (viafb_SAMM_ON == 1) {
2291                 crt_timing1 = vmode_tbl1->crtc;
2292         }
2293
2294         inb(VIAStatus);
2295         outb(0x00, VIAAR);
2296
2297         /* Write Common Setting for Video Mode */
2298         switch (viaparinfo->chip_info->gfx_chip_name) {
2299         case UNICHROME_CLE266:
2300                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2301                 break;
2302
2303         case UNICHROME_K400:
2304                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2305                 break;
2306
2307         case UNICHROME_K800:
2308         case UNICHROME_PM800:
2309                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2310                 break;
2311
2312         case UNICHROME_CN700:
2313         case UNICHROME_K8M890:
2314         case UNICHROME_P4M890:
2315         case UNICHROME_P4M900:
2316                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2317                 break;
2318
2319         case UNICHROME_CX700:
2320         case UNICHROME_VX800:
2321                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2322                 break;
2323
2324         case UNICHROME_VX855:
2325                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2326                 break;
2327         }
2328
2329         device_off();
2330
2331         /* Fill VPIT Parameters */
2332         /* Write Misc Register */
2333         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2334
2335         /* Write Sequencer */
2336         for (i = 1; i <= StdSR; i++)
2337                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2338
2339         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2340         viafb_set_iga_path();
2341
2342         /* Write CRTC */
2343         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2344
2345         /* Write Graphic Controller */
2346         for (i = 0; i < StdGR; i++)
2347                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2348
2349         /* Write Attribute Controller */
2350         for (i = 0; i < StdAR; i++) {
2351                 inb(VIAStatus);
2352                 outb(i, VIAAR);
2353                 outb(VPIT.AR[i], VIAAR);
2354         }
2355
2356         inb(VIAStatus);
2357         outb(0x20, VIAAR);
2358
2359         /* Update Patch Register */
2360
2361         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2362             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2363             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2364             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2365                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2366                         index = res_patch_table[0].io_reg_table[j].index;
2367                         port = res_patch_table[0].io_reg_table[j].port;
2368                         value = res_patch_table[0].io_reg_table[j].value;
2369                         mask = res_patch_table[0].io_reg_table[j].mask;
2370                         viafb_write_reg_mask(index, port, value, mask);
2371                 }
2372         }
2373
2374         via_set_primary_pitch(viafbinfo->fix.line_length);
2375         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2376                 : viafbinfo->fix.line_length);
2377         via_set_primary_color_depth(viaparinfo->depth);
2378         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2379                 : viaparinfo->depth);
2380         /* Update Refresh Rate Setting */
2381
2382         /* Clear On Screen */
2383
2384         /* CRT set mode */
2385         if (viafb_CRT_ON) {
2386                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2387                         IGA2)) {
2388                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2389                                 video_bpp1 / 8,
2390                                 viaparinfo->crt_setting_info->iga_path);
2391                 } else {
2392                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2393                                 video_bpp / 8,
2394                                 viaparinfo->crt_setting_info->iga_path);
2395                 }
2396
2397                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2398
2399                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2400                 to 8 alignment (1368),there is several pixels (2 pixels)
2401                 on right side of screen. */
2402                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2403                         viafb_unlock_crt();
2404                         viafb_write_reg(CR02, VIACR,
2405                                 viafb_read_reg(VIACR, CR02) - 1);
2406                         viafb_lock_crt();
2407                 }
2408         }
2409
2410         if (viafb_DVI_ON) {
2411                 if (viafb_SAMM_ON &&
2412                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2413                         viafb_dvi_set_mode(viafb_get_mode
2414                                      (viaparinfo->tmds_setting_info->h_active,
2415                                       viaparinfo->tmds_setting_info->
2416                                       v_active),
2417                                      video_bpp1, viaparinfo->
2418                                      tmds_setting_info->iga_path);
2419                 } else {
2420                         viafb_dvi_set_mode(viafb_get_mode
2421                                      (viaparinfo->tmds_setting_info->h_active,
2422                                       viaparinfo->
2423                                       tmds_setting_info->v_active),
2424                                      video_bpp, viaparinfo->
2425                                      tmds_setting_info->iga_path);
2426                 }
2427         }
2428
2429         if (viafb_LCD_ON) {
2430                 if (viafb_SAMM_ON &&
2431                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2432                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2433                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2434                                 lvds_setting_info,
2435                                      &viaparinfo->chip_info->lvds_chip_info);
2436                 } else {
2437                         /* IGA1 doesn't have LCD scaling, so set it center. */
2438                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2439                                 viaparinfo->lvds_setting_info->display_method =
2440                                     LCD_CENTERING;
2441                         }
2442                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2443                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2444                                 lvds_setting_info,
2445                                      &viaparinfo->chip_info->lvds_chip_info);
2446                 }
2447         }
2448         if (viafb_LCD2_ON) {
2449                 if (viafb_SAMM_ON &&
2450                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2451                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2452                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2453                                 lvds_setting_info2,
2454                                      &viaparinfo->chip_info->lvds_chip_info2);
2455                 } else {
2456                         /* IGA1 doesn't have LCD scaling, so set it center. */
2457                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2458                                 viaparinfo->lvds_setting_info2->display_method =
2459                                     LCD_CENTERING;
2460                         }
2461                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2462                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2463                                 lvds_setting_info2,
2464                                      &viaparinfo->chip_info->lvds_chip_info2);
2465                 }
2466         }
2467
2468         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2469             && (viafb_LCD_ON || viafb_DVI_ON))
2470                 set_display_channel();
2471
2472         /* If set mode normally, save resolution information for hot-plug . */
2473         if (!viafb_hotplug) {
2474                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2475                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2476                 viafb_hotplug_bpp = video_bpp;
2477                 viafb_hotplug_refresh = viafb_refresh;
2478
2479                 if (viafb_DVI_ON)
2480                         viafb_DeviceStatus = DVI_Device;
2481                 else
2482                         viafb_DeviceStatus = CRT_Device;
2483         }
2484         device_on();
2485
2486         if (viafb_SAMM_ON == 1)
2487                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2488
2489         device_screen_on();
2490         return 1;
2491 }
2492
2493 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2494 {
2495         int i;
2496
2497         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2498                 if ((hres == res_map_refresh_tbl[i].hres)
2499                     && (vres == res_map_refresh_tbl[i].vres)
2500                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2501                         return res_map_refresh_tbl[i].pixclock;
2502         }
2503         return RES_640X480_60HZ_PIXCLOCK;
2504
2505 }
2506
2507 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2508 {
2509 #define REFRESH_TOLERANCE 3
2510         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2511         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2512                 if ((hres == res_map_refresh_tbl[i].hres)
2513                     && (vres == res_map_refresh_tbl[i].vres)
2514                     && (diff > (abs(long_refresh -
2515                     res_map_refresh_tbl[i].vmode_refresh)))) {
2516                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2517                                 vmode_refresh);
2518                         nearest = i;
2519                 }
2520         }
2521 #undef REFRESH_TOLERANCE
2522         if (nearest > 0)
2523                 return res_map_refresh_tbl[nearest].vmode_refresh;
2524         return 60;
2525 }
2526
2527 static void device_off(void)
2528 {
2529         viafb_crt_disable();
2530         viafb_dvi_disable();
2531         viafb_lcd_disable();
2532 }
2533
2534 static void device_on(void)
2535 {
2536         if (viafb_CRT_ON == 1)
2537                 viafb_crt_enable();
2538         if (viafb_DVI_ON == 1)
2539                 viafb_dvi_enable();
2540         if (viafb_LCD_ON == 1)
2541                 viafb_lcd_enable();
2542 }
2543
2544 void viafb_crt_disable(void)
2545 {
2546         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2547 }
2548
2549 void viafb_crt_enable(void)
2550 {
2551         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2552 }
2553
2554 static void enable_second_display_channel(void)
2555 {
2556         /* to enable second display channel. */
2557         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2558         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2559         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2560 }
2561
2562 static void disable_second_display_channel(void)
2563 {
2564         /* to disable second display channel. */
2565         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2566         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2567         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2568 }
2569
2570
2571 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2572                                         *p_gfx_dpa_setting)
2573 {
2574         switch (output_interface) {
2575         case INTERFACE_DVP0:
2576                 {
2577                         /* DVP0 Clock Polarity and Adjust: */
2578                         viafb_write_reg_mask(CR96, VIACR,
2579                                        p_gfx_dpa_setting->DVP0, 0x0F);
2580
2581                         /* DVP0 Clock and Data Pads Driving: */
2582                         viafb_write_reg_mask(SR1E, VIASR,
2583                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2584                         viafb_write_reg_mask(SR2A, VIASR,
2585                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2586                                        BIT4);
2587                         viafb_write_reg_mask(SR1B, VIASR,
2588                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2589                         viafb_write_reg_mask(SR2A, VIASR,
2590                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2591                         break;
2592                 }
2593
2594         case INTERFACE_DVP1:
2595                 {
2596                         /* DVP1 Clock Polarity and Adjust: */
2597                         viafb_write_reg_mask(CR9B, VIACR,
2598                                        p_gfx_dpa_setting->DVP1, 0x0F);
2599
2600                         /* DVP1 Clock and Data Pads Driving: */
2601                         viafb_write_reg_mask(SR65, VIASR,
2602                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2603                         break;
2604                 }
2605
2606         case INTERFACE_DFP_HIGH:
2607                 {
2608                         viafb_write_reg_mask(CR97, VIACR,
2609                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2610                         break;
2611                 }
2612
2613         case INTERFACE_DFP_LOW:
2614                 {
2615                         viafb_write_reg_mask(CR99, VIACR,
2616                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2617                         break;
2618                 }
2619
2620         case INTERFACE_DFP:
2621                 {
2622                         viafb_write_reg_mask(CR97, VIACR,
2623                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2624                         viafb_write_reg_mask(CR99, VIACR,
2625                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2626                         break;
2627                 }
2628         }
2629 }
2630
2631 /*According var's xres, yres fill var's other timing information*/
2632 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2633         struct VideoModeTable *vmode_tbl)
2634 {
2635         struct crt_mode_table *crt_timing = NULL;
2636         struct display_timing crt_reg;
2637         int i = 0, index = 0;
2638         crt_timing = vmode_tbl->crtc;
2639         for (i = 0; i < vmode_tbl->mode_array; i++) {
2640                 index = i;
2641                 if (crt_timing[i].refresh_rate == refresh)
2642                         break;
2643         }
2644
2645         crt_reg = crt_timing[index].crtc;
2646         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2647         var->left_margin =
2648             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2649         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2650         var->hsync_len = crt_reg.hor_sync_end;
2651         var->upper_margin =
2652             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2653         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2654         var->vsync_len = crt_reg.ver_sync_end;
2655 }