drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28
  29 #include "ieee80211/dot11d.h"
  30
  31
  32 //#define CONFIG_RTL8180_IO_MAP
  33
  34 #define TC_3W_POLL_MAX_TRY_CNT 5
  35 static u8 MAC_REG_TABLE[][2]={
  36                         //PAGA 0:
  37                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  38                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  39                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  40                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  41                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  42                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  43                         {0x94, 0x0F}, {0x95, 0x32},
  44                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  45                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  46                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  47                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  48                         {0xff, 0x00},
  49
  50                         //PAGE 1:
  51                         // For Flextronics system Logo PCIHCT failure:
  52                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  53                         {0x5e, 0x01},
  54                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  55                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  56                         {0x82, 0xFF}, {0x83, 0x03},
  57                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  58                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  59                         {0xe2, 0x00},
  60
  61
  62                         //PAGE 2:
  63                         {0x5e, 0x02},
  64                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  65                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  66                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  67                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  68                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  69                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  70                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  71
  72                         //PAGA 0:
  73                         {0x5e, 0x00},{0x9f, 0x03}
  74                 };
  75
  76
  77 static u8  ZEBRA_AGC[]={
  78                         0,
  79                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  80                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  81                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  82                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  83                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  84                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  85                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  86                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  87                         };
  88
  89 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  90                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  91                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  92                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  93                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
  94                         0x0183,0x0163,0x0143,0x0123,0x0103
  95         };
  96
  97 static u8 OFDM_CONFIG[]={
  98                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
  99                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 100                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 101
 102                         // 0x00
 103                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 104                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 105                         // 0x10
 106                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 107                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 108                         // 0x20
 109                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 110                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 111                         // 0x30
 112                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 113                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 114                 };
 115
 116 /*---------------------------------------------------------------
 117   * Hardware IO
 118   * the code is ported from Windows source code
 119   ----------------------------------------------------------------*/
 120
 121 void
 122 PlatformIOWrite1Byte(
 123         struct net_device *dev,
 124         u32             offset,
 125         u8              data
 126         )
 127 {
 128         write_nic_byte(dev, offset, data);
 129         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 130
 131 }
 132
 133 void
 134 PlatformIOWrite2Byte(
 135         struct net_device *dev,
 136         u32             offset,
 137         u16             data
 138         )
 139 {
 140         write_nic_word(dev, offset, data);
 141         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 142
 143
 144 }
 145 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 146
 147 void
 148 PlatformIOWrite4Byte(
 149         struct net_device *dev,
 150         u32             offset,
 151         u32             data
 152         )
 153 {
 154 //{by amy 080312
 155 if (offset == PhyAddr)
 156         {//For Base Band configuration.
 157                 unsigned char   cmdByte;
 158                 unsigned long   dataBytes;
 159                 unsigned char   idx;
 160                 u8      u1bTmp;
 161
 162                 cmdByte = (u8)(data & 0x000000ff);
 163                 dataBytes = data>>8;
 164
 165                 //
 166                 // 071010, rcnjko:
 167                 // The critical section is only BB read/write race condition.
 168                 // Assumption:
 169                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 170                 // acquiring the spinlock in such context.
 171                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 172                 //
 173 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 174
 175                 for(idx = 0; idx < 30; idx++)
 176                 { // Make sure command bit is clear before access it.
 177                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 178                         if((u1bTmp & BIT7) == 0)
 179                                 break;
 180                         else
 181                                 mdelay(10);
 182                 }
 183
 184                 for(idx=0; idx < 3; idx++)
 185                 {
 186                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 187                 }
 188                 write_nic_byte(dev, offset, cmdByte);
 189
 190 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 191         }
 192 //by amy 080312}
 193         else{
 194                 write_nic_dword(dev, offset, data);
 195                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 196         }
 197 }
 198
 199 u8
 200 PlatformIORead1Byte(
 201         struct net_device *dev,
 202         u32             offset
 203         )
 204 {
 205         u8      data = 0;
 206
 207         data = read_nic_byte(dev, offset);
 208
 209
 210         return data;
 211 }
 212
 213 u16
 214 PlatformIORead2Byte(
 215         struct net_device *dev,
 216         u32             offset
 217         )
 218 {
 219         u16     data = 0;
 220
 221         data = read_nic_word(dev, offset);
 222
 223
 224         return data;
 225 }
 226
 227 u32
 228 PlatformIORead4Byte(
 229         struct net_device *dev,
 230         u32             offset
 231         )
 232 {
 233         u32     data = 0;
 234
 235         data = read_nic_dword(dev, offset);
 236
 237
 238         return data;
 239 }
 240
 241 void SetOutputEnableOfRfPins(struct net_device *dev)
 242 {
 243         write_nic_word(dev, RFPinsEnable, 0x1bff);
 244 }
 245
 246 static int
 247 HwHSSIThreeWire(
 248         struct net_device *dev,
 249         u8                      *pDataBuf,
 250         u8                      nDataBufBitCnt,
 251         int                     bSI,
 252         int                     bWrite
 253         )
 254 {
 255         int     bResult = 1;
 256         u8      TryCnt;
 257         u8      u1bTmp;
 258
 259         do
 260         {
 261                 // Check if WE and RE are cleared.
 262                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 263                 {
 264                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 265                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 266                         {
 267                                 break;
 268                         }
 269                         udelay(10);
 270                 }
 271                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
 272                         printk(KERN_ERR "rtl8187se: HwThreeWire(): CmdReg:"
 273                                " %#X RE|WE bits are not clear!!\n", u1bTmp);
 274                         dump_stack();
 275                         return 0;
 276                 }
 277
 278                 // RTL8187S HSSI Read/Write Function
 279                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 280
 281                 if(bSI)
 282                 {
 283                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 284                 }else
 285                 {
 286                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 287                 }
 288
 289                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 290
 291                 if(bSI)
 292                 {
 293                         // jong: HW SI read must set reg84[3]=0.
 294                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 295                         u1bTmp &= ~BIT3;
 296                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 297                 }
 298                 // Fill up data buffer for write operation.
 299
 300                 if(bWrite)
 301                 {
 302                         if(nDataBufBitCnt == 16)
 303                         {
 304                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 305                         }
 306                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 307                         {
 308                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 309                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 310                         }
 311                         else
 312                         {
 313                                 int idx;
 314                                 int ByteCnt = nDataBufBitCnt / 8;
 315                                 //printk("%d\n",nDataBufBitCnt);
 316                                 if ((nDataBufBitCnt % 8) != 0) {
 317                                         printk(KERN_ERR "rtl8187se: "
 318                                                "HwThreeWire(): nDataBufBitCnt(%d)"
 319                                                " should be multiple of 8!!!\n",
 320                                                nDataBufBitCnt);
 321                                         dump_stack();
 322                                         nDataBufBitCnt += 8;
 323                                         nDataBufBitCnt &= ~7;
 324                                 }
 325
 326                                if (nDataBufBitCnt > 64) {
 327                                         printk(KERN_ERR "rtl8187se: HwThreeWire():"
 328                                                " nDataBufBitCnt(%d) should <= 64!!!\n",
 329                                                nDataBufBitCnt);
 330                                         dump_stack();
 331                                         nDataBufBitCnt = 64;
 332                                 }
 333
 334                                 for(idx = 0; idx < ByteCnt; idx++)
 335                                 {
 336                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 337                                 }
 338                         }
 339                 }
 340                 else            //read
 341                 {
 342                         if(bSI)
 343                         {
 344                                 // SI - reg274[3:0] : RF register's Address
 345                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 346                         }
 347                         else
 348                         {
 349                                 // PI - reg274[15:12] : RF register's Address
 350                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 351                         }
 352                 }
 353
 354                 // Set up command: WE or RE.
 355                 if(bWrite)
 356                 {
 357                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 358                 }
 359                 else
 360                 {
 361                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 362                 }
 363
 364                 // Check if DONE is set.
 365                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 366                 {
 367                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 368                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 369                         {
 370                                 break;
 371                         }
 372                         udelay(10);
 373                 }
 374
 375                 write_nic_byte(dev, SW_3W_CMD1, 0);
 376
 377                 // Read back data for read operation.
 378                 if(bWrite == 0)
 379                 {
 380                         if(bSI)
 381                         {
 382                                 //Serial Interface : reg363_362[11:0]
 383                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 384                         }
 385                         else
 386                         {
 387                                 //Parallel Interface : reg361_360[11:0]
 388                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 389                         }
 390
 391                         *((u16*)pDataBuf) &= 0x0FFF;
 392                 }
 393
 394         }while(0);
 395
 396         return bResult;
 397 }
 398
 399 void
 400 RF_WriteReg(struct net_device *dev, u8 offset, u32 data)
 401 {
 402         u32 data2Write;
 403         u8 len;
 404
 405         /* Pure HW 3-wire. */
 406         data2Write = (data << 4) | (u32)(offset & 0x0f);
 407         len = 16;
 408
 409         HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1);
 410 }
 411
 412 u32 RF_ReadReg(struct net_device *dev, u8 offset)
 413 {
 414         u32 data2Write;
 415         u8 wlen;
 416         u32 dataRead;
 417
 418         data2Write = ((u32)(offset & 0x0f));
 419         wlen = 16;
 420         HwHSSIThreeWire(dev, (u8 *)(&data2Write), wlen, 1, 0);
 421         dataRead = data2Write;
 422
 423         return dataRead;
 424 }
 425
 426
 427 // by Owen on 04/07/14 for writing BB register successfully
 428 void
 429 WriteBBPortUchar(
 430         struct net_device *dev,
 431         u32             Data
 432         )
 433 {
 434         //u8    TimeoutCounter;
 435         u8      RegisterContent;
 436         u8      UCharData;
 437
 438         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 439         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 440         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
 441         {
 442                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 443                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 444                 //if(UCharData == RegisterContent)
 445                 //      break;
 446         }
 447 }
 448
 449 u8
 450 ReadBBPortUchar(
 451         struct net_device *dev,
 452         u32             addr
 453         )
 454 {
 455         //u8    TimeoutCounter;
 456         u8      RegisterContent;
 457
 458         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 459         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 460
 461         return RegisterContent;
 462 }
 463 //{by amy 080312
 464 //
 465 //      Description:
 466 //              Perform Antenna settings with antenna diversity on 87SE.
 467 //    Created by Roger, 2008.01.25.
 468 //
 469 bool
 470 SetAntennaConfig87SE(
 471         struct net_device *dev,
 472         u8                      DefaultAnt,             // 0: Main, 1: Aux.
 473         bool            bAntDiversity   // 1:Enable, 0: Disable.
 474 )
 475 {
 476         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 477         bool   bAntennaSwitched = true;
 478
 479         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
 480
 481         // Threshold for antenna diversity.
 482         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
 483
 484         if( bAntDiversity )  //  Enable Antenna Diversity.
 485         {
 486                 if( DefaultAnt == 1 )  // aux antenna
 487                 {
 488                         // Mac register, aux antenna
 489                         write_nic_byte(dev, ANTSEL, 0x00);
 490
 491                         // Config CCK RX antenna.
 492                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 493                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 494
 495                         // Config OFDM RX antenna.
 496                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 497                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 498                 }
 499                 else //  use main antenna
 500                 {
 501                         // Mac register, main antenna
 502                         write_nic_byte(dev, ANTSEL, 0x03);
 503                         //base band
 504                         // Config CCK RX antenna.
 505                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 506                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 507
 508                         // Config OFDM RX antenna.
 509                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
 510                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 511                 }
 512         }
 513         else   // Disable Antenna Diversity.
 514         {
 515                 if( DefaultAnt == 1 ) // aux Antenna
 516                 {
 517                         // Mac register, aux antenna
 518                         write_nic_byte(dev, ANTSEL, 0x00);
 519
 520                         // Config CCK RX antenna.
 521                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 522                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 523
 524                         // Config OFDM RX antenna.
 525                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 526                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 527                 }
 528                 else // main Antenna
 529                 {
 530                         // Mac register, main antenna
 531                         write_nic_byte(dev, ANTSEL, 0x03);
 532
 533                         // Config CCK RX antenna.
 534                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 535                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 536
 537                         // Config OFDM RX antenna.
 538                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
 539                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 540                 }
 541         }
 542         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
 543         return  bAntennaSwitched;
 544 }
 545 //by amy 080312
 546 /*---------------------------------------------------------------
 547   * Hardware Initialization.
 548   * the code is ported from Windows source code
 549   ----------------------------------------------------------------*/
 550
 551 void
 552 ZEBRA_Config_85BASIC_HardCode(
 553         struct net_device *dev
 554         )
 555 {
 556
 557         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 558         u32                     i;
 559         u32     addr,data;
 560         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
 561        u8                       u1b24E;
 562         int d_cut = 0;
 563
 564
 565         //=============================================================================
 566         // 87S_PCIE :: RADIOCFG.TXT
 567         //=============================================================================
 568
 569
 570         // Page1 : reg16-reg30
 571         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
 572         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
 573         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
 574
 575         if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
 576                 d_cut = 1;
 577                 printk(KERN_INFO "rtl8187se: card type changed from C- to D-cut\n");
 578         }
 579
 580         // Page0 : reg0-reg15
 581
 582         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
 583
 584         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
 585
 586         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
 587
 588         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
 589
 590         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
 591         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
 592         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
 593         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
 594         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
 595         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
 596         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
 597         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
 598         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
 599         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
 600         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
 601         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
 602
 603
 604         // Page1 : reg16-reg30
 605         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
 606
 607         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
 608
 609         RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
 610         RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
 611         RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
 612
 613
 614         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
 615 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
 616         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
 617         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
 618
 619         if (d_cut) {
 620                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
 621                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
 622                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
 623         } else {
 624                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
 625                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
 626                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
 627         }
 628
 629         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
 630
 631         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
 632
 633         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
 634         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
 635         for(i=0;i<=36;i++)
 636         {
 637                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
 638                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
 639         }
 640
 641         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
 642         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
 643
 644         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
 645         mdelay(10);     // Deay 10 ms. //0xfd
 646
 647         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
 648         mdelay(10);     // Deay 10 ms. //0xfd
 649
 650         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
 651         mdelay(10);     // Deay 10 ms. //0xfd
 652
 653         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
 654         mdelay(10);     // Deay 10 ms. //0xfd
 655
 656         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
 657         mdelay(10);     // Deay 10 ms. //0xfd
 658
 659         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
 660         mdelay(200);    // Deay 200 ms. //0xfd
 661         mdelay(10);     // Deay 10 ms. //0xfd
 662         mdelay(10);     // Deay 10 ms. //0xfd
 663
 664         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
 665         mdelay(10);     // Deay 10 ms. //0xfd
 666
 667         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
 668         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
 669         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
 670         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
 671
 672         // DAC calibration off 20070702
 673         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
 674         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
 675 //{by amy 080312
 676         // For crystal calibration, added by Roger, 2007.12.11.
 677         if( priv->bXtalCalibration ) // reg 30.
 678         { // enable crystal calibration.
 679                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
 680                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
 681                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
 682                 // So we should minus 4 BITs offset.
 683                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
 684                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
 685                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
 686         }
 687         else
 688         { // using default value. Xin=6, Xout=6.
 689                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
 690         }
 691 //by amy 080312
 692
 693         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
 694         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
 695         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
 696         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
 697         mdelay(10);     // Deay 10 ms. //0xfe
 698         mdelay(10);     // Deay 10 ms. //0xfe
 699         mdelay(10);     // Deay 10 ms. //0xfe
 700         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
 701         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
 702         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
 703
 704         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
 705         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
 706         //power save parameters.
 707         u1b24E = read_nic_byte(dev, 0x24E);
 708         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
 709
 710         //=============================================================================
 711
 712         //=============================================================================
 713         // CCKCONF.TXT
 714         //=============================================================================
 715
 716         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
 717                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
 718                 CCK reg0x00[6]=1'b1: power saving for RX (default)
 719                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
 720                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
 721                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
 722         */
 723
 724         write_phy_cck(dev,0x00,0xc8);
 725         write_phy_cck(dev,0x06,0x1c);
 726         write_phy_cck(dev,0x10,0x78);
 727         write_phy_cck(dev,0x2e,0xd0);
 728         write_phy_cck(dev,0x2f,0x06);
 729         write_phy_cck(dev,0x01,0x46);
 730
 731         // power control
 732         write_nic_byte(dev, CCK_TXAGC, 0x10);
 733         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
 734         write_nic_byte(dev, ANTSEL, 0x03);
 735
 736
 737
 738         //=============================================================================
 739         // AGC.txt
 740         //=============================================================================
 741
 742         write_phy_ofdm(dev, 0x00, 0x12);
 743
 744         for (i=0; i<128; i++)
 745         {
 746
 747                 data = ZEBRA_AGC[i+1];
 748                 data = data << 8;
 749                 data = data | 0x0000008F;
 750
 751                 addr = i + 0x80; //enable writing AGC table
 752                 addr = addr << 8;
 753                 addr = addr | 0x0000008E;
 754
 755                 WriteBBPortUchar(dev, data);
 756                 WriteBBPortUchar(dev, addr);
 757                 WriteBBPortUchar(dev, 0x0000008E);
 758         }
 759
 760         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
 761
 762         //=============================================================================
 763
 764         //=============================================================================
 765         // OFDMCONF.TXT
 766         //=============================================================================
 767
 768         for(i=0; i<60; i++)
 769         {
 770                 u4bRegOffset=i;
 771                 u4bRegValue=OFDM_CONFIG[i];
 772
 773                 WriteBBPortUchar(dev,
 774                                                 (0x00000080 |
 775                                                 (u4bRegOffset & 0x7f) |
 776                                                 ((u4bRegValue & 0xff) << 8)));
 777         }
 778
 779         //=============================================================================
 780 //by amy for antenna
 781         //=============================================================================
 782 //{by amy 080312
 783         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
 784         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
 785 //by amy 080312}
 786 //by amy for antenna
 787 }
 788
 789
 790 void
 791 UpdateInitialGain(
 792         struct net_device *dev
 793         )
 794 {
 795         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 796
 797         //lzm add 080826
 798         if(priv->eRFPowerState != eRfOn)
 799         {
 800                 //Don't access BB/RF under disable PLL situation.
 801                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
 802                 // Back to the original state
 803                 priv->InitialGain= priv->InitialGainBackUp;
 804                 return;
 805         }
 806
 807         switch (priv->InitialGain) {
 808         case 1: /* m861dBm */
 809                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 810                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 811                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 812                 break;
 813
 814         case 2: /* m862dBm */
 815                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 816                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 817                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 818                 break;
 819
 820         case 3: /* m863dBm */
 821                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 822                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 823                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 824                 break;
 825
 826         case 4: /* m864dBm */
 827                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 828                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 829                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 830                 break;
 831
 832         case 5: /* m82dBm */
 833                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 834                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 835                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 836                 break;
 837
 838         case 6: /* m78dBm */
 839                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 840                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 841                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 842                 break;
 843
 844         case 7: /* m74dBm */
 845                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 846                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
 847                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 848                 break;
 849
 850         case 8:
 851                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
 852                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
 853                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 854                 break;
 855
 856         default:        /* MP */
 857                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 858                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 859                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 860                 break;
 861         }
 862 }
 863 //
 864 //      Description:
 865 //              Tx Power tracking mechanism routine on 87SE.
 866 //      Created by Roger, 2007.12.11.
 867 //
 868 void
 869 InitTxPwrTracking87SE(
 870         struct net_device *dev
 871 )
 872 {
 873         u32     u4bRfReg;
 874
 875         u4bRfReg = RF_ReadReg(dev, 0x02);
 876
 877         // Enable Thermal meter indication.
 878         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
 879 }
 880
 881 void
 882 PhyConfig8185(
 883         struct net_device *dev
 884         )
 885 {
 886         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 887        write_nic_dword(dev, RCR, priv->ReceiveConfig);
 888            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
 889         /*  RF config */
 890         ZEBRA_Config_85BASIC_HardCode(dev);
 891 //{by amy 080312
 892         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
 893         if(priv->bDigMechanism)
 894         {
 895                 if(priv->InitialGain == 0)
 896                         priv->InitialGain = 4;
 897         }
 898
 899         //
 900         // Enable thermal meter indication to implement TxPower tracking on 87SE.
 901         // We initialize thermal meter here to avoid unsuccessful configuration.
 902         // Added by Roger, 2007.12.11.
 903         //
 904         if(priv->bTxPowerTrack)
 905                 InitTxPwrTracking87SE(dev);
 906
 907 //by amy 080312}
 908         priv->InitialGainBackUp= priv->InitialGain;
 909         UpdateInitialGain(dev);
 910
 911         return;
 912 }
 913
 914 void
 915 HwConfigureRTL8185(
 916                 struct net_device *dev
 917                 )
 918 {
 919         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
 920         u8              bUNIVERSAL_CONTROL_RL = 0;
 921         u8              bUNIVERSAL_CONTROL_AGC = 1;
 922         u8              bUNIVERSAL_CONTROL_ANT = 1;
 923         u8              bAUTO_RATE_FALLBACK_CTL = 1;
 924         u8              val8;
 925         write_nic_word(dev, BRSR, 0x0fff);
 926         // Retry limit
 927         val8 = read_nic_byte(dev, CW_CONF);
 928
 929         if(bUNIVERSAL_CONTROL_RL)
 930                 val8 = val8 & 0xfd;
 931         else
 932                 val8 = val8 | 0x02;
 933
 934         write_nic_byte(dev, CW_CONF, val8);
 935
 936         // Tx AGC
 937         val8 = read_nic_byte(dev, TXAGC_CTL);
 938         if(bUNIVERSAL_CONTROL_AGC)
 939         {
 940                 write_nic_byte(dev, CCK_TXAGC, 128);
 941                 write_nic_byte(dev, OFDM_TXAGC, 128);
 942                 val8 = val8 & 0xfe;
 943         }
 944         else
 945         {
 946                 val8 = val8 | 0x01 ;
 947         }
 948
 949
 950         write_nic_byte(dev, TXAGC_CTL, val8);
 951
 952         // Tx Antenna including Feedback control
 953         val8 = read_nic_byte(dev, TXAGC_CTL );
 954
 955         if(bUNIVERSAL_CONTROL_ANT)
 956         {
 957                 write_nic_byte(dev, ANTSEL, 0x00);
 958                 val8 = val8 & 0xfd;
 959         }
 960         else
 961         {
 962                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
 963         }
 964
 965         write_nic_byte(dev, TXAGC_CTL, val8);
 966
 967         // Auto Rate fallback control
 968         val8 = read_nic_byte(dev, RATE_FALLBACK);
 969         val8 &= 0x7c;
 970         if( bAUTO_RATE_FALLBACK_CTL )
 971         {
 972                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
 973
 974                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
 975                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
 976         }
 977         write_nic_byte(dev, RATE_FALLBACK, val8);
 978 }
 979
 980 static void
 981 MacConfig_85BASIC_HardCode(
 982         struct net_device *dev)
 983 {
 984         //============================================================================
 985         // MACREG.TXT
 986         //============================================================================
 987         int                     nLinesRead = 0;
 988
 989         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
 990         int     i;
 991
 992         nLinesRead=sizeof(MAC_REG_TABLE)/2;
 993
 994         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
 995         {
 996                 u4bRegOffset=MAC_REG_TABLE[i][0];
 997                 u4bRegValue=MAC_REG_TABLE[i][1];
 998
 999                 if(u4bRegOffset == 0x5e)
1000                 {
1001                     u4bPageIndex = u4bRegValue;
1002                 }
1003                 else
1004                 {
1005                     u4bRegOffset |= (u4bPageIndex << 8);
1006                 }
1007                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1008         }
1009         //============================================================================
1010 }
1011
1012 static void
1013 MacConfig_85BASIC(
1014         struct net_device *dev)
1015 {
1016
1017        u8                       u1DA;
1018         MacConfig_85BASIC_HardCode(dev);
1019
1020         //============================================================================
1021
1022         // Follow TID_AC_MAP of WMac.
1023         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1024
1025         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1026         write_nic_word(dev, IntMig, 0x0000);
1027
1028         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1029         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1030         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1031         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1032
1033         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1034         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1035
1036         //Enable DA10 TX power saving
1037         u1DA = read_nic_byte(dev, PHYPR);
1038         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1039
1040         //POWER:
1041         write_nic_word(dev, 0x360, 0x1000);
1042         write_nic_word(dev, 0x362, 0x1000);
1043
1044         // AFE.
1045         write_nic_word(dev, 0x370, 0x0560);
1046         write_nic_word(dev, 0x372, 0x0560);
1047         write_nic_word(dev, 0x374, 0x0DA4);
1048         write_nic_word(dev, 0x376, 0x0DA4);
1049         write_nic_word(dev, 0x378, 0x0560);
1050         write_nic_word(dev, 0x37A, 0x0560);
1051         write_nic_word(dev, 0x37C, 0x00EC);
1052         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1053        write_nic_byte(dev, 0x24E,0x01);
1054 }
1055
1056 u8
1057 GetSupportedWirelessMode8185(
1058         struct net_device *dev
1059 )
1060 {
1061         u8                      btSupportedWirelessMode = 0;
1062
1063         btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1064         return btSupportedWirelessMode;
1065 }
1066
1067 void
1068 ActUpdateChannelAccessSetting(
1069         struct net_device *dev,
1070         WIRELESS_MODE                   WirelessMode,
1071         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1072         )
1073 {
1074         struct r8180_priv *priv = ieee80211_priv(dev);
1075         struct ieee80211_device *ieee = priv->ieee80211;
1076         AC_CODING       eACI;
1077         AC_PARAM        AcParam;
1078         u8      bFollowLegacySetting = 0;
1079         u8   u1bAIFS;
1080
1081         //
1082         // <RJ_TODO_8185B>
1083         // TODO: We still don't know how to set up these registers, just follow WMAC to
1084         // verify 8185B FPAG.
1085         //
1086         // <RJ_TODO_8185B>
1087         // Jong said CWmin/CWmax register are not functional in 8185B,
1088         // so we shall fill channel access realted register into AC parameter registers,
1089         // even in nQBss.
1090         //
1091         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1092         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1093         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1094         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1095         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1096         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1097
1098         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1099         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1100
1101         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1102
1103         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1104
1105         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1106
1107         { // Legacy 802.11.
1108                 bFollowLegacySetting = 1;
1109
1110         }
1111
1112         // this setting is copied from rtl8187B.  xiong-2006-11-13
1113         if(bFollowLegacySetting)
1114         {
1115
1116
1117                 //
1118                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1119                 // 2005.12.01, by rcnjko.
1120                 //
1121                 AcParam.longData = 0;
1122                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1123                 AcParam.f.AciAifsn.f.ACM = 0;
1124                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1125                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1126                 AcParam.f.TXOPLimit = 0;
1127
1128                 //lzm reserved 080826
1129                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1130                 if( ieee->current_network.Turbo_Enable == 1 )
1131                         AcParam.f.TXOPLimit = 0x01FF;
1132                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
1133                 if (ieee->iw_mode == IW_MODE_ADHOC)
1134                         AcParam.f.TXOPLimit = 0x0020;
1135
1136                 for(eACI = 0; eACI < AC_MAX; eACI++)
1137                 {
1138                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1139                         {
1140                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1141                                 AC_CODING       eACI;
1142                                 u8              u1bAIFS;
1143                                 u32             u4bAcParam;
1144
1145                                 // Retrive paramters to udpate.
1146                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1147                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1148                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
1149                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1150                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1151                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1152
1153                                 switch(eACI)
1154                                 {
1155                                         case AC1_BK:
1156                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1157                                                 break;
1158
1159                                         case AC0_BE:
1160                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1161                                                 break;
1162
1163                                         case AC2_VI:
1164                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1165                                                 break;
1166
1167                                         case AC3_VO:
1168                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1169                                                 break;
1170
1171                                         default:
1172                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1173                                                 break;
1174                                 }
1175
1176                                 // Cehck ACM bit.
1177                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1178                                 {
1179                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1180                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1181
1182                                         //modified Joseph
1183                                         //for 8187B AsynIORead issue
1184                                         u8      AcmCtrl = 0;
1185                                         if( pAciAifsn->f.ACM )
1186                                         { // ACM bit is 1.
1187                                                 switch(eACI)
1188                                                 {
1189                                                         case AC0_BE:
1190                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
1191                                                                 break;
1192
1193                                                         case AC2_VI:
1194                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
1195                                                                 break;
1196
1197                                                         case AC3_VO:
1198                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
1199                                                                 break;
1200
1201                                                         default:
1202                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1203                                                                 break;
1204                                                 }
1205                                         }
1206                                         else
1207                                         { // ACM bit is 0.
1208                                                 switch(eACI)
1209                                                 {
1210                                                         case AC0_BE:
1211                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
1212                                                                 break;
1213
1214                                                         case AC2_VI:
1215                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
1216                                                                 break;
1217
1218                                                         case AC3_VO:
1219                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
1220                                                                 break;
1221
1222                                                         default:
1223                                                                 break;
1224                                                 }
1225                                         }
1226                                         write_nic_byte(dev, ACM_CONTROL, 0);
1227                                 }
1228                         }
1229                 }
1230         }
1231 }
1232
1233 void
1234 ActSetWirelessMode8185(
1235         struct net_device *dev,
1236         u8                              btWirelessMode
1237         )
1238 {
1239         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1240         struct ieee80211_device *ieee = priv->ieee80211;
1241         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1242
1243         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1244         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1245                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1246                         btWirelessMode, btSupportedWirelessMode);
1247                 return;
1248         }
1249
1250         // 1. Assign wireless mode to swtich if necessary.
1251         if (btWirelessMode == WIRELESS_MODE_AUTO)
1252         {
1253                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1254                 {
1255                         btWirelessMode = WIRELESS_MODE_A;
1256                 }
1257                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1258                 {
1259                         btWirelessMode = WIRELESS_MODE_G;
1260                 }
1261                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1262                 {
1263                         btWirelessMode = WIRELESS_MODE_B;
1264                 }
1265                 else
1266                 {
1267                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1268                                          btSupportedWirelessMode);
1269                         btWirelessMode = WIRELESS_MODE_B;
1270                 }
1271         }
1272
1273         /* 2. Swtich band: RF or BB specific actions,
1274          * for example, refresh tables in omc8255, or change initial gain if necessary.
1275          * Nothing to do for Zebra to switch band.
1276          * Update current wireless mode if we swtich to specified band successfully. */
1277         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1278
1279         // 3. Change related setting.
1280         if( ieee->mode == WIRELESS_MODE_A ){
1281                 DMESG("WIRELESS_MODE_A\n");
1282         }
1283         else if( ieee->mode == WIRELESS_MODE_B ){
1284                 DMESG("WIRELESS_MODE_B\n");
1285         }
1286         else if( ieee->mode == WIRELESS_MODE_G ){
1287                 DMESG("WIRELESS_MODE_G\n");
1288         }
1289         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1290 }
1291
1292 void rtl8185b_irq_enable(struct net_device *dev)
1293 {
1294         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1295
1296         priv->irq_enabled = 1;
1297         write_nic_dword(dev, IMR, priv->IntrMask);
1298 }
1299 //by amy for power save
1300 void
1301 DrvIFIndicateDisassociation(
1302         struct net_device *dev,
1303         u16                     reason
1304         )
1305 {
1306         // nothing is needed after disassociation request.
1307 }
1308 void
1309 MgntDisconnectIBSS(
1310         struct net_device *dev
1311 )
1312 {
1313         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1314         u8                      i;
1315
1316         DrvIFIndicateDisassociation(dev, unspec_reason);
1317         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
1318
1319         priv->ieee80211->state = IEEE80211_NOLINK;
1320
1321         //Stop Beacon.
1322
1323         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1324         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1325         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1326
1327         // Disable Beacon Queue Own bit, suggested by jong
1328         ieee80211_stop_send_beacons(priv->ieee80211);
1329
1330         priv->ieee80211->link_change(dev);
1331         notify_wx_assoc_event(priv->ieee80211);
1332 }
1333 void
1334 MlmeDisassociateRequest(
1335         struct net_device *dev,
1336         u8*                     asSta,
1337         u8                      asRsn
1338         )
1339 {
1340         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1341         u8 i;
1342
1343         SendDisassociation(priv->ieee80211, asSta, asRsn );
1344
1345         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
1346                 //ShuChen TODO: change media status.
1347                 //ShuChen TODO: What to do when disassociate.
1348                 DrvIFIndicateDisassociation(dev, unspec_reason);
1349
1350
1351                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
1352                 ieee80211_disassociate(priv->ieee80211);
1353         }
1354
1355 }
1356
1357 void
1358 MgntDisconnectAP(
1359         struct net_device *dev,
1360         u8                      asRsn
1361 )
1362 {
1363         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1364
1365 //
1366 // Commented out by rcnjko, 2005.01.27:
1367 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1368 //
1369 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
1370
1371         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
1372         // 2004.10.11, by rcnjko.
1373         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
1374
1375         priv->ieee80211->state = IEEE80211_NOLINK;
1376 }
1377 bool
1378 MgntDisconnect(
1379         struct net_device *dev,
1380         u8                      asRsn
1381 )
1382 {
1383         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1384         //
1385         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1386         //
1387
1388         if(IS_DOT11D_ENABLE(priv->ieee80211))
1389                 Dot11d_Reset(priv->ieee80211);
1390         // In adhoc mode, update beacon frame.
1391         if( priv->ieee80211->state == IEEE80211_LINKED )
1392         {
1393                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
1394                 {
1395                         MgntDisconnectIBSS(dev);
1396                 }
1397                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
1398                 {
1399                         // We clear key here instead of MgntDisconnectAP() because that
1400                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
1401                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
1402                         // used to handle disassociation related things to AP, e.g. send Disassoc
1403                         // frame to AP.  2005.01.27, by rcnjko.
1404                         MgntDisconnectAP(dev, asRsn);
1405                 }
1406                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
1407         }
1408         return true;
1409 }
1410 //
1411 //      Description:
1412 //              Chang RF Power State.
1413 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
1414 //
1415 //      Assumption:
1416 //              PASSIVE LEVEL.
1417 //
1418 bool
1419 SetRFPowerState(
1420         struct net_device *dev,
1421         RT_RF_POWER_STATE       eRFPowerState
1422         )
1423 {
1424         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1425         bool                    bResult = false;
1426
1427         if(eRFPowerState == priv->eRFPowerState)
1428         {
1429                 return bResult;
1430         }
1431
1432          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1433
1434         return bResult;
1435 }
1436 void
1437 HalEnableRx8185Dummy(
1438         struct net_device *dev
1439         )
1440 {
1441 }
1442 void
1443 HalDisableRx8185Dummy(
1444         struct net_device *dev
1445         )
1446 {
1447 }
1448
1449 bool
1450 MgntActSet_RF_State(
1451         struct net_device *dev,
1452         RT_RF_POWER_STATE       StateToSet,
1453         u32     ChangeSource
1454         )
1455 {
1456         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1457         bool                            bActionAllowed = false;
1458         bool                            bConnectBySSID = false;
1459         RT_RF_POWER_STATE       rtState;
1460         u16                             RFWaitCounter = 0;
1461         unsigned long flag;
1462         //
1463         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1464         // Only one thread can change the RF state at one time, and others should wait to be executed.
1465         //
1466         while(true)
1467         {
1468                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
1469                 if(priv->RFChangeInProgress)
1470                 {
1471                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
1472                         // Set RF after the previous action is done.
1473                         while(priv->RFChangeInProgress)
1474                         {
1475                                 RFWaitCounter ++;
1476                                 udelay(1000); // 1 ms
1477
1478                                 // Wait too long, return FALSE to avoid to be stuck here.
1479                                 if(RFWaitCounter > 1000) // 1sec
1480                                 {
1481                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1482                                         // TODO: Reset RF state?
1483                                         return false;
1484                                 }
1485                         }
1486                 }
1487                 else
1488                 {
1489                         priv->RFChangeInProgress = true;
1490                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
1491                         break;
1492                 }
1493         }
1494         rtState = priv->eRFPowerState;
1495
1496         switch(StateToSet)
1497         {
1498         case eRfOn:
1499                 //
1500                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
1501                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
1502                 //
1503                 priv->RfOffReason &= (~ChangeSource);
1504
1505                 if(! priv->RfOffReason)
1506                 {
1507                         priv->RfOffReason = 0;
1508                         bActionAllowed = true;
1509
1510                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
1511                         {
1512                                 bConnectBySSID = true;
1513                         }
1514                 }
1515                 else
1516                         ;
1517                 break;
1518
1519         case eRfOff:
1520                  // 070125, rcnjko: we always keep connected in AP mode.
1521
1522                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
1523                         {
1524                                 //
1525                                 // 060808, Annie:
1526                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
1527                                 //
1528
1529                                 //
1530                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
1531                                 // because we do NOT need to set ssid to dummy ones.
1532                                 //
1533                                 MgntDisconnect( dev, disas_lv_ss );
1534
1535                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
1536                         }
1537
1538                 priv->RfOffReason |= ChangeSource;
1539                 bActionAllowed = true;
1540                 break;
1541         case eRfSleep:
1542                 priv->RfOffReason |= ChangeSource;
1543                 bActionAllowed = true;
1544                 break;
1545         default:
1546                 break;
1547         }
1548
1549         if(bActionAllowed)
1550         {
1551                 // Config HW to the specified mode.
1552                 SetRFPowerState(dev, StateToSet);
1553
1554                 // Turn on RF.
1555                 if(StateToSet == eRfOn)
1556                 {
1557                         HalEnableRx8185Dummy(dev);
1558                         if(bConnectBySSID)
1559                         {
1560                         // by amy not supported
1561                         }
1562                 }
1563                 // Turn off RF.
1564                 else if(StateToSet == eRfOff)
1565                 {
1566                         HalDisableRx8185Dummy(dev);
1567                 }
1568         }
1569
1570         // Release RF spinlock
1571         spin_lock_irqsave(&priv->rf_ps_lock,flag);
1572         priv->RFChangeInProgress = false;
1573         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
1574         return bActionAllowed;
1575 }
1576 void
1577 InactivePowerSave(
1578         struct net_device *dev
1579         )
1580 {
1581         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1582         //
1583         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
1584         // is really scheduled.
1585         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
1586         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
1587         // blocks the IPS procedure of switching RF.
1588         //
1589         priv->bSwRfProcessing = true;
1590
1591         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1592
1593         //
1594         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
1595         //
1596
1597         priv->bSwRfProcessing = false;
1598 }
1599
1600 //
1601 //      Description:
1602 //              Enter the inactive power save mode. RF will be off
1603 //
1604 void
1605 IPSEnter(
1606         struct net_device *dev
1607         )
1608 {
1609         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1610         RT_RF_POWER_STATE rtState;
1611         if (priv->bInactivePs)
1612         {
1613                 rtState = priv->eRFPowerState;
1614
1615                 //
1616                 // Do not enter IPS in the following conditions:
1617                 // (1) RF is already OFF or Sleep
1618                 // (2) bSwRfProcessing (indicates the IPS is still under going)
1619                 // (3) Connectted (only disconnected can trigger IPS)
1620                 // (4) IBSS (send Beacon)
1621                 // (5) AP mode (send Beacon)
1622                 //
1623                 if (rtState == eRfOn && !priv->bSwRfProcessing
1624                         && (priv->ieee80211->state != IEEE80211_LINKED ))
1625                 {
1626                         priv->eInactivePowerState = eRfOff;
1627                         InactivePowerSave(dev);
1628                 }
1629         }
1630 }
1631 void
1632 IPSLeave(
1633         struct net_device *dev
1634         )
1635 {
1636         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1637         RT_RF_POWER_STATE rtState;
1638         if (priv->bInactivePs)
1639         {
1640                 rtState = priv->eRFPowerState;
1641                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
1642                 {
1643                         priv->eInactivePowerState = eRfOn;
1644                         InactivePowerSave(dev);
1645                 }
1646         }
1647 }
1648
1649 void rtl8185b_adapter_start(struct net_device *dev)
1650 {
1651       struct r8180_priv *priv = ieee80211_priv(dev);
1652         struct ieee80211_device *ieee = priv->ieee80211;
1653
1654         u8 SupportedWirelessMode;
1655         u8                      InitWirelessMode;
1656         u8                      bInvalidWirelessMode = 0;
1657         u8 tmpu8;
1658         u8 btCR9346;
1659         u8 TmpU1b;
1660         u8 btPSR;
1661
1662         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
1663         rtl8180_reset(dev);
1664
1665         priv->dma_poll_mask = 0;
1666         priv->dma_poll_stop_mask = 0;
1667
1668         HwConfigureRTL8185(dev);
1669         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
1670         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
1671         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
1672         write_nic_word(dev, BcnItv, 100);
1673         write_nic_word(dev, AtimWnd, 2);
1674         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1675         write_nic_byte(dev, WPA_CONFIG, 0);
1676         MacConfig_85BASIC(dev);
1677         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
1678         // BT_DEMO_BOARD type
1679         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1680
1681         //-----------------------------------------------------------------------------
1682         // Set up PHY related.
1683         //-----------------------------------------------------------------------------
1684         // Enable Config3.PARAM_En to revise AnaaParm.
1685         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
1686         tmpu8 = read_nic_byte(dev, CONFIG3);
1687         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
1688         // Turn on Analog power.
1689         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
1690         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1691         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1692         write_nic_word(dev, ANAPARAM3, 0x0010);
1693
1694         write_nic_byte(dev, CONFIG3, tmpu8);
1695         write_nic_byte(dev, CR9346, 0x00);
1696         // enable EEM0 and EEM1 in 9346CR
1697         btCR9346 = read_nic_byte(dev, CR9346);
1698         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
1699
1700         // B cut use LED1 to control HW RF on/off
1701         TmpU1b = read_nic_byte(dev, CONFIG5);
1702         TmpU1b = TmpU1b & ~BIT3;
1703         write_nic_byte(dev,CONFIG5, TmpU1b);
1704
1705         // disable EEM0 and EEM1 in 9346CR
1706         btCR9346 &= ~(0xC0);
1707         write_nic_byte(dev, CR9346, btCR9346);
1708
1709         //Enable Led (suggested by Jong)
1710         // B-cut RF Radio on/off  5e[3]=0
1711         btPSR = read_nic_byte(dev, PSR);
1712         write_nic_byte(dev, PSR, (btPSR | BIT3));
1713         // setup initial timing for RFE.
1714         write_nic_word(dev, RFPinsOutput, 0x0480);
1715         SetOutputEnableOfRfPins(dev);
1716         write_nic_word(dev, RFPinsSelect, 0x2488);
1717
1718         // PHY config.
1719         PhyConfig8185(dev);
1720
1721         // We assume RegWirelessMode has already been initialized before,
1722         // however, we has to validate the wireless mode here and provide a
1723         // reasonable initialized value if necessary. 2005.01.13, by rcnjko.
1724         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1725         if(     (ieee->mode != WIRELESS_MODE_B) &&
1726                 (ieee->mode != WIRELESS_MODE_G) &&
1727                 (ieee->mode != WIRELESS_MODE_A) &&
1728                 (ieee->mode != WIRELESS_MODE_AUTO))
1729         { // It should be one of B, G, A, or AUTO.
1730                 bInvalidWirelessMode = 1;
1731         }
1732         else
1733         { // One of B, G, A, or AUTO.
1734                 // Check if the wireless mode is supported by RF.
1735                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
1736                         (ieee->mode & SupportedWirelessMode) == 0 )
1737                 {
1738                         bInvalidWirelessMode = 1;
1739                 }
1740         }
1741
1742         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
1743         { // Auto or other invalid value.
1744                 // Assigne a wireless mode to initialize.
1745                 if((SupportedWirelessMode & WIRELESS_MODE_A))
1746                 {
1747                         InitWirelessMode = WIRELESS_MODE_A;
1748                 }
1749                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
1750                 {
1751                         InitWirelessMode = WIRELESS_MODE_G;
1752                 }
1753                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
1754                 {
1755                         InitWirelessMode = WIRELESS_MODE_B;
1756                 }
1757                 else
1758                 {
1759                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1760                                  SupportedWirelessMode);
1761                         InitWirelessMode = WIRELESS_MODE_B;
1762                 }
1763
1764                 // Initialize RegWirelessMode if it is not a valid one.
1765                 if(bInvalidWirelessMode)
1766                 {
1767                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1768                 }
1769         }
1770         else
1771         { // One of B, G, A.
1772                 InitWirelessMode = ieee->mode;
1773         }
1774 //by amy for power save
1775         priv->eRFPowerState = eRfOff;
1776         priv->RfOffReason = 0;
1777         {
1778                 MgntActSet_RF_State(dev, eRfOn, 0);
1779         }
1780                 //
1781                 // If inactive power mode is enabled, disable rf while in disconnected state.
1782                 //
1783         if (priv->bInactivePs)
1784         {
1785                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
1786         }
1787 //by amy for power save
1788
1789         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1790
1791         //-----------------------------------------------------------------------------
1792
1793         rtl8185b_irq_enable(dev);
1794
1795         netif_start_queue(dev);
1796  }
1797
1798 void rtl8185b_rx_enable(struct net_device *dev)
1799 {
1800         u8 cmd;
1801         /* for now we accept data, management & ctl frame*/
1802         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1803
1804         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
1805
1806         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1807            dev->flags & IFF_PROMISC){
1808                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1809                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1810         }
1811
1812         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1813                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
1814         }
1815
1816         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1817                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1818
1819         write_nic_dword(dev, RCR, priv->ReceiveConfig);
1820
1821         fix_rx_fifo(dev);
1822
1823         cmd=read_nic_byte(dev,CMD);
1824         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1825
1826 }
1827
1828 void rtl8185b_tx_enable(struct net_device *dev)
1829 {
1830         u8 cmd;
1831         u8 byte;
1832         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1833
1834         write_nic_dword(dev, TCR, priv->TransmitConfig);
1835         byte = read_nic_byte(dev, MSR);
1836         byte |= MSR_LINK_ENEDCA;
1837         write_nic_byte(dev, MSR, byte);
1838
1839         fix_tx_fifo(dev);
1840
1841         cmd=read_nic_byte(dev,CMD);
1842         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1843 }
1844