drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #include "mite.h"
  53
  54 #include "comedi_fc.h"
  55 #include "comedi_pci.h"
  56 #include "../comedidev.h"
  57
  58 #include <asm/system.h>
  59
  60 #define PCI_MITE_SIZE           4096
  61 #define PCI_DAQ_SIZE            4096
  62 #define PCI_DAQ_SIZE_660X       8192
  63
  64 MODULE_LICENSE("GPL");
  65
  66 struct mite_struct *mite_devices;
  67 EXPORT_SYMBOL(mite_devices);
  68
  69 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  70
  71 void mite_init(void)
  72 {
  73         struct pci_dev *pcidev = NULL;
  74         struct mite_struct *mite;
  75
  76         for_each_pci_dev(pcidev) {
  77                 if (pcidev->vendor == PCI_VENDOR_ID_NI) {
  78                         unsigned i;
  79
  80                         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  81                         if (!mite) {
  82                                 printk(KERN_ERR "mite: allocation failed\n");
  83                                 pci_dev_put(pcidev);
  84                                 return;
  85                         }
  86                         spin_lock_init(&mite->lock);
  87                         mite->pcidev = pci_dev_get(pcidev);
  88                         for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  89                                 mite->channels[i].mite = mite;
  90                                 mite->channels[i].channel = i;
  91                                 mite->channels[i].done = 1;
  92                         }
  93                         mite->next = mite_devices;
  94                         mite_devices = mite;
  95                 }
  96         }
  97 }
  98
  99 static void dump_chip_signature(u32 csigr_bits)
 100 {
 101         printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
 102                "interface mode = %i\n",
 103                mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
 104                mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
 105         printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
 106                "wins = %i, iowins = %i\n",
 107                mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
 108                mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
 109 }
 110
 111 unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
 112 {
 113         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
 114         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 115         unsigned full_count = fcr_bits & 0xff;
 116         return empty_count + full_count;
 117 }
 118
 119 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 120 {
 121         unsigned long length;
 122         resource_size_t addr;
 123         int i;
 124         u32 csigr_bits;
 125         unsigned unknown_dma_burst_bits;
 126
 127         if (comedi_pci_enable(mite->pcidev, "mite")) {
 128                 printk(KERN_ERR "error enabling mite and requesting io regions\n");
 129                 return -EIO;
 130         }
 131         pci_set_master(mite->pcidev);
 132
 133         addr = pci_resource_start(mite->pcidev, 0);
 134         mite->mite_phys_addr = addr;
 135         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 136         if (!mite->mite_io_addr) {
 137                 printk(KERN_ERR "Failed to remap mite io memory address\n");
 138                 return -ENOMEM;
 139         }
 140         printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
 141                (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
 142
 143         addr = pci_resource_start(mite->pcidev, 1);
 144         mite->daq_phys_addr = addr;
 145         length = pci_resource_len(mite->pcidev, 1);
 146         /*
 147          * In case of a 660x board, DAQ size is 8k instead of 4k
 148          * (see as shown by lspci output)
 149          */
 150         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 151         if (!mite->daq_io_addr) {
 152                 printk(KERN_ERR "Failed to remap daq io memory address\n");
 153                 return -ENOMEM;
 154         }
 155         printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
 156                (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
 157
 158         if (use_iodwbsr_1) {
 159                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 160                 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
 161                 writel(mite->daq_phys_addr | WENAB |
 162                        MITE_IODWBSR_1_WSIZE_bits(length),
 163                        mite->mite_io_addr + MITE_IODWBSR_1);
 164                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 165         } else {
 166                 writel(mite->daq_phys_addr | WENAB,
 167                        mite->mite_io_addr + MITE_IODWBSR);
 168         }
 169         /*
 170          * make sure dma bursts work. I got this from running a bus analyzer
 171          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 172          * of 0x61f and bursts worked. 6281 powered up with register value of
 173          * 0x1f and bursts didn't work. The NI windows driver reads the
 174          * register, then does a bitwise-or of 0x600 with it and writes it back.
 175          */
 176         unknown_dma_burst_bits =
 177             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 178         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 179         writel(unknown_dma_burst_bits,
 180                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 181
 182         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 183         mite->num_channels = mite_csigr_dmac(csigr_bits);
 184         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 185                 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
 186                        "channels. Setting to %i.\n",
 187                        mite->num_channels, MAX_MITE_DMA_CHANNELS);
 188                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 189         }
 190         dump_chip_signature(csigr_bits);
 191         for (i = 0; i < mite->num_channels; i++) {
 192                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 193                 /* disable interrupts */
 194                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 195                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 196                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 197                        mite->mite_io_addr + MITE_CHCR(i));
 198         }
 199         mite->fifo_size = mite_fifo_size(mite, 0);
 200         printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
 201         mite->used = 1;
 202
 203         return 0;
 204 }
 205 EXPORT_SYMBOL(mite_setup2);
 206
 207 int mite_setup(struct mite_struct *mite)
 208 {
 209         return mite_setup2(mite, 0);
 210 }
 211 EXPORT_SYMBOL(mite_setup);
 212
 213 void mite_cleanup(void)
 214 {
 215         struct mite_struct *mite, *next;
 216
 217         for (mite = mite_devices; mite; mite = next) {
 218                 pci_dev_put(mite->pcidev);
 219                 next = mite->next;
 220                 kfree(mite);
 221         }
 222 }
 223
 224 void mite_unsetup(struct mite_struct *mite)
 225 {
 226         /* unsigned long offset, start, length; */
 227
 228         if (!mite)
 229                 return;
 230
 231         if (mite->mite_io_addr) {
 232                 iounmap(mite->mite_io_addr);
 233                 mite->mite_io_addr = NULL;
 234         }
 235         if (mite->daq_io_addr) {
 236                 iounmap(mite->daq_io_addr);
 237                 mite->daq_io_addr = NULL;
 238         }
 239         if (mite->mite_phys_addr) {
 240                 comedi_pci_disable(mite->pcidev);
 241                 mite->mite_phys_addr = 0;
 242         }
 243
 244         mite->used = 0;
 245 }
 246 EXPORT_SYMBOL(mite_unsetup);
 247
 248 void mite_list_devices(void)
 249 {
 250         struct mite_struct *mite, *next;
 251
 252         printk(KERN_INFO "Available NI device IDs:");
 253         if (mite_devices)
 254                 for (mite = mite_devices; mite; mite = next) {
 255                         next = mite->next;
 256                         printk(KERN_INFO " 0x%04x", mite_device_id(mite));
 257                         if (mite->used)
 258                                 printk(KERN_INFO "(used)");
 259                 }
 260         printk(KERN_INFO "\n");
 261 }
 262 EXPORT_SYMBOL(mite_list_devices);
 263
 264 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 265                                                    struct
 266                                                    mite_dma_descriptor_ring
 267                                                    *ring, unsigned min_channel,
 268                                                    unsigned max_channel)
 269 {
 270         int i;
 271         unsigned long flags;
 272         struct mite_channel *channel = NULL;
 273
 274         /* spin lock so mite_release_channel can be called safely
 275          * from interrupts
 276          */
 277         spin_lock_irqsave(&mite->lock, flags);
 278         for (i = min_channel; i <= max_channel; ++i) {
 279                 if (mite->channel_allocated[i] == 0) {
 280                         mite->channel_allocated[i] = 1;
 281                         channel = &mite->channels[i];
 282                         channel->ring = ring;
 283                         break;
 284                 }
 285         }
 286         spin_unlock_irqrestore(&mite->lock, flags);
 287         return channel;
 288 }
 289 EXPORT_SYMBOL(mite_request_channel_in_range);
 290
 291 void mite_release_channel(struct mite_channel *mite_chan)
 292 {
 293         struct mite_struct *mite = mite_chan->mite;
 294         unsigned long flags;
 295
 296         /*  spin lock to prevent races with mite_request_channel */
 297         spin_lock_irqsave(&mite->lock, flags);
 298         if (mite->channel_allocated[mite_chan->channel]) {
 299                 mite_dma_disarm(mite_chan);
 300                 mite_dma_reset(mite_chan);
 301         /*
 302          * disable all channel's interrupts (do it after disarm/reset so
 303          * MITE_CHCR reg isn't changed while dma is still active!)
 304          */
 305                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 306                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 307                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 308                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 309                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 310                 mite->channel_allocated[mite_chan->channel] = 0;
 311                 mite_chan->ring = NULL;
 312                 mmiowb();
 313         }
 314         spin_unlock_irqrestore(&mite->lock, flags);
 315 }
 316 EXPORT_SYMBOL(mite_release_channel);
 317
 318 void mite_dma_arm(struct mite_channel *mite_chan)
 319 {
 320         struct mite_struct *mite = mite_chan->mite;
 321         int chor;
 322         unsigned long flags;
 323
 324         MDPRINTK("mite_dma_arm ch%i\n", channel);
 325         /*
 326          * memory barrier is intended to insure any twiddling with the buffer
 327          * is done before writing to the mite to arm dma transfer
 328          */
 329         smp_mb();
 330         /* arm */
 331         chor = CHOR_START;
 332         spin_lock_irqsave(&mite->lock, flags);
 333         mite_chan->done = 0;
 334         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 335         mmiowb();
 336         spin_unlock_irqrestore(&mite->lock, flags);
 337 /*       mite_dma_tcr(mite, channel); */
 338 }
 339 EXPORT_SYMBOL(mite_dma_arm);
 340
 341 /**************************************/
 342
 343 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 344                     struct comedi_async *async)
 345 {
 346         unsigned int n_links;
 347         int i;
 348
 349         if (ring->descriptors) {
 350                 dma_free_coherent(ring->hw_dev,
 351                                   ring->n_links *
 352                                   sizeof(struct mite_dma_descriptor),
 353                                   ring->descriptors,
 354                                   ring->descriptors_dma_addr);
 355         }
 356         ring->descriptors = NULL;
 357         ring->descriptors_dma_addr = 0;
 358         ring->n_links = 0;
 359
 360         if (async->prealloc_bufsz == 0)
 361                 return 0;
 362
 363         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 364
 365         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 366
 367         ring->descriptors =
 368             dma_alloc_coherent(ring->hw_dev,
 369                                n_links * sizeof(struct mite_dma_descriptor),
 370                                &ring->descriptors_dma_addr, GFP_KERNEL);
 371         if (!ring->descriptors) {
 372                 printk(KERN_ERR "mite: ring buffer allocation failed\n");
 373                 return -ENOMEM;
 374         }
 375         ring->n_links = n_links;
 376
 377         for (i = 0; i < n_links; i++) {
 378                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 379                 ring->descriptors[i].addr =
 380                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 381                 ring->descriptors[i].next =
 382                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 383                                                               1) *
 384                                 sizeof(struct mite_dma_descriptor));
 385         }
 386         ring->descriptors[n_links - 1].next =
 387             cpu_to_le32(ring->descriptors_dma_addr);
 388         /*
 389          * barrier is meant to insure that all the writes to the dma descriptors
 390          * have completed before the dma controller is commanded to read them
 391          */
 392         smp_wmb();
 393         return 0;
 394 }
 395 EXPORT_SYMBOL(mite_buf_change);
 396
 397 void mite_prep_dma(struct mite_channel *mite_chan,
 398                    unsigned int num_device_bits, unsigned int num_memory_bits)
 399 {
 400         unsigned int chor, chcr, mcr, dcr, lkcr;
 401         struct mite_struct *mite = mite_chan->mite;
 402
 403         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 404
 405         /* reset DMA and FIFO */
 406         chor = CHOR_DMARESET | CHOR_FRESET;
 407         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 408
 409         /* short link chaining mode */
 410         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 411             CHCR_BURSTEN;
 412         /*
 413          * Link Complete Interrupt: interrupt every time a link
 414          * in MITE_RING is completed. This can generate a lot of
 415          * extra interrupts, but right now we update the values
 416          * of buf_int_ptr and buf_int_count at each interrupt. A
 417          * better method is to poll the MITE before each user
 418          * "read()" to calculate the number of bytes available.
 419          */
 420         chcr |= CHCR_SET_LC_IE;
 421         if (num_memory_bits == 32 && num_device_bits == 16) {
 422                 /*
 423                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 424                  * samples into the fifo in the right order. Tested doing 32 bit
 425                  * memory to 16 bit device transfers to the analog out of a
 426                  * pxi-6281, which has mite version = 1, type = 4. This also
 427                  * works for dma reads from the counters on e-series boards.
 428                  */
 429                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 430         }
 431         if (mite_chan->dir == COMEDI_INPUT)
 432                 chcr |= CHCR_DEV_TO_MEM;
 433
 434         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 435
 436         /* to/from memory */
 437         mcr = CR_RL(64) | CR_ASEQUP;
 438         switch (num_memory_bits) {
 439         case 8:
 440                 mcr |= CR_PSIZE8;
 441                 break;
 442         case 16:
 443                 mcr |= CR_PSIZE16;
 444                 break;
 445         case 32:
 446                 mcr |= CR_PSIZE32;
 447                 break;
 448         default:
 449                 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
 450                        "transfer\n");
 451                 break;
 452         }
 453         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 454
 455         /* from/to device */
 456         dcr = CR_RL(64) | CR_ASEQUP;
 457         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 458         switch (num_device_bits) {
 459         case 8:
 460                 dcr |= CR_PSIZE8;
 461                 break;
 462         case 16:
 463                 dcr |= CR_PSIZE16;
 464                 break;
 465         case 32:
 466                 dcr |= CR_PSIZE32;
 467                 break;
 468         default:
 469                 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
 470                        "transfer\n");
 471                 break;
 472         }
 473         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 474
 475         /* reset the DAR */
 476         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 477
 478         /* the link is 32bits */
 479         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 480         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 481
 482         /* starting address for link chaining */
 483         writel(mite_chan->ring->descriptors_dma_addr,
 484                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 485
 486         MDPRINTK("exit mite_prep_dma\n");
 487 }
 488 EXPORT_SYMBOL(mite_prep_dma);
 489
 490 u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 491 {
 492         struct mite_struct *mite = mite_chan->mite;
 493         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 494 }
 495
 496 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 497 {
 498         struct mite_struct *mite = mite_chan->mite;
 499         return readl(mite->mite_io_addr +
 500                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 501 }
 502 EXPORT_SYMBOL(mite_bytes_in_transit);
 503
 504 /* returns lower bound for number of bytes transferred from device to memory */
 505 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 506 {
 507         u32 device_byte_count;
 508
 509         device_byte_count = mite_device_bytes_transferred(mite_chan);
 510         return device_byte_count - mite_bytes_in_transit(mite_chan);
 511 }
 512 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 513
 514 /* returns upper bound for number of bytes transferred from device to memory */
 515 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 516 {
 517         u32 in_transit_count;
 518
 519         in_transit_count = mite_bytes_in_transit(mite_chan);
 520         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 521 }
 522 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 523
 524 /* returns lower bound for number of bytes read from memory to device */
 525 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 526 {
 527         u32 device_byte_count;
 528
 529         device_byte_count = mite_device_bytes_transferred(mite_chan);
 530         return device_byte_count + mite_bytes_in_transit(mite_chan);
 531 }
 532 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 533
 534 /* returns upper bound for number of bytes read from memory to device */
 535 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 536 {
 537         u32 in_transit_count;
 538
 539         in_transit_count = mite_bytes_in_transit(mite_chan);
 540         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 541 }
 542 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 543
 544 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 545 {
 546         struct mite_struct *mite = mite_chan->mite;
 547         int tcr;
 548         int lkar;
 549
 550         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 551         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 552         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 553                  lkar, tcr);
 554
 555         return tcr;
 556 }
 557 EXPORT_SYMBOL(mite_dma_tcr);
 558
 559 void mite_dma_disarm(struct mite_channel *mite_chan)
 560 {
 561         struct mite_struct *mite = mite_chan->mite;
 562         unsigned chor;
 563
 564         /* disarm */
 565         chor = CHOR_ABORT;
 566         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 567 }
 568 EXPORT_SYMBOL(mite_dma_disarm);
 569
 570 int mite_sync_input_dma(struct mite_channel *mite_chan,
 571                         struct comedi_async *async)
 572 {
 573         int count;
 574         unsigned int nbytes, old_alloc_count;
 575         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 576
 577         old_alloc_count = async->buf_write_alloc_count;
 578         /* write alloc as much as we can */
 579         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 580
 581         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 582         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 583                   old_alloc_count) > 0) {
 584                 printk("mite: DMA overwrite of free area\n");
 585                 async->events |= COMEDI_CB_OVERFLOW;
 586                 return -1;
 587         }
 588
 589         count = nbytes - async->buf_write_count;
 590         /* it's possible count will be negative due to
 591          * conservative value returned by mite_bytes_written_to_memory_lb */
 592         if (count <= 0)
 593                 return 0;
 594
 595         comedi_buf_write_free(async, count);
 596
 597         async->scan_progress += count;
 598         if (async->scan_progress >= bytes_per_scan) {
 599                 async->scan_progress %= bytes_per_scan;
 600                 async->events |= COMEDI_CB_EOS;
 601         }
 602         async->events |= COMEDI_CB_BLOCK;
 603         return 0;
 604 }
 605 EXPORT_SYMBOL(mite_sync_input_dma);
 606
 607 int mite_sync_output_dma(struct mite_channel *mite_chan,
 608                          struct comedi_async *async)
 609 {
 610         int count;
 611         u32 nbytes_ub, nbytes_lb;
 612         unsigned int old_alloc_count;
 613         u32 stop_count =
 614             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 615
 616         old_alloc_count = async->buf_read_alloc_count;
 617         /*  read alloc as much as we can */
 618         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 619         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 620         if (async->cmd.stop_src == TRIG_COUNT &&
 621             (int)(nbytes_lb - stop_count) > 0)
 622                 nbytes_lb = stop_count;
 623         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 624         if (async->cmd.stop_src == TRIG_COUNT &&
 625             (int)(nbytes_ub - stop_count) > 0)
 626                 nbytes_ub = stop_count;
 627         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 628                 printk(KERN_ERR "mite: DMA underrun\n");
 629                 async->events |= COMEDI_CB_OVERFLOW;
 630                 return -1;
 631         }
 632         count = nbytes_lb - async->buf_read_count;
 633         if (count <= 0)
 634                 return 0;
 635
 636         if (count) {
 637                 comedi_buf_read_free(async, count);
 638                 async->events |= COMEDI_CB_BLOCK;
 639         }
 640         return 0;
 641 }
 642 EXPORT_SYMBOL(mite_sync_output_dma);
 643
 644 unsigned mite_get_status(struct mite_channel *mite_chan)
 645 {
 646         struct mite_struct *mite = mite_chan->mite;
 647         unsigned status;
 648         unsigned long flags;
 649
 650         spin_lock_irqsave(&mite->lock, flags);
 651         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 652         if (status & CHSR_DONE) {
 653                 mite_chan->done = 1;
 654                 writel(CHOR_CLRDONE,
 655                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 656         }
 657         mmiowb();
 658         spin_unlock_irqrestore(&mite->lock, flags);
 659         return status;
 660 }
 661 EXPORT_SYMBOL(mite_get_status);
 662
 663 int mite_done(struct mite_channel *mite_chan)
 664 {
 665         struct mite_struct *mite = mite_chan->mite;
 666         unsigned long flags;
 667         int done;
 668
 669         mite_get_status(mite_chan);
 670         spin_lock_irqsave(&mite->lock, flags);
 671         done = mite_chan->done;
 672         spin_unlock_irqrestore(&mite->lock, flags);
 673         return done;
 674 }
 675 EXPORT_SYMBOL(mite_done);
 676
 677 #ifdef DEBUG_MITE
 678
 679 static void mite_decode(char **bit_str, unsigned int bits);
 680
 681 /* names of bits in mite registers */
 682
 683 static const char *const mite_CHOR_strings[] = {
 684         "start", "cont", "stop", "abort",
 685         "freset", "clrlc", "clrrb", "clrdone",
 686         "clr_lpause", "set_lpause", "clr_send_tc",
 687         "set_send_tc", "12", "13", "14",
 688         "15", "16", "17", "18",
 689         "19", "20", "21", "22",
 690         "23", "24", "25", "26",
 691         "27", "28", "29", "30",
 692         "dmareset",
 693 };
 694
 695 static const char *const mite_CHCR_strings[] = {
 696         "continue", "ringbuff", "2", "3",
 697         "4", "5", "6", "7",
 698         "8", "9", "10", "11",
 699         "12", "13", "bursten", "fifodis",
 700         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 701         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 702         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 703         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 704 };
 705
 706 static const char *const mite_MCR_strings[] = {
 707         "amdevice", "1", "2", "3",
 708         "4", "5", "portio", "portvxi",
 709         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 710         "12", "13", "blocken", "berhand",
 711         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 712         "rd512", "rl1", "rl2", "rl8",
 713         "24", "25", "26", "27",
 714         "28", "29", "30", "stopen",
 715 };
 716
 717 static const char *const mite_DCR_strings[] = {
 718         "amdevice", "1", "2", "3",
 719         "4", "5", "portio", "portvxi",
 720         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 721         "aseqxp8", "13", "blocken", "berhand",
 722         "reqsintlim", "reqs1", "reqs2", "rd32",
 723         "rd512", "rl1", "rl2", "rl8",
 724         "23", "24", "25", "27",
 725         "28", "wsdevc", "wsdevs", "rwdevpack",
 726 };
 727
 728 static const char *const mite_LKCR_strings[] = {
 729         "amdevice", "1", "2", "3",
 730         "4", "5", "portio", "portvxi",
 731         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 732         "12", "13", "14", "berhand",
 733         "16", "17", "18", "rd32",
 734         "rd512", "rl1", "rl2", "rl8",
 735         "24", "25", "26", "27",
 736         "28", "29", "30", "chngend",
 737 };
 738
 739 static const char *const mite_CHSR_strings[] = {
 740         "d.err0", "d.err1", "m.err0", "m.err1",
 741         "l.err0", "l.err1", "drq0", "drq1",
 742         "end", "xferr", "operr0", "operr1",
 743         "stops", "habort", "sabort", "error",
 744         "16", "conts_rb", "18", "linkc",
 745         "20", "drdy", "22", "mrdy",
 746         "24", "done", "26", "sars",
 747         "28", "lpauses", "30", "int",
 748 };
 749
 750 void mite_dump_regs(struct mite_channel *mite_chan)
 751 {
 752         unsigned long mite_io_addr =
 753             (unsigned long)mite_chan->mite->mite_io_addr;
 754         unsigned long addr = 0;
 755         unsigned long temp = 0;
 756
 757         printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
 758         printk(KERN_DEBUG "mite address is  =0x%08lx\n", mite_io_addr);
 759
 760         addr = mite_io_addr + MITE_CHOR(channel);
 761         printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
 762                temp = readl(addr));
 763         mite_decode(mite_CHOR_strings, temp);
 764         addr = mite_io_addr + MITE_CHCR(channel);
 765         printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
 766                temp = readl(addr));
 767         mite_decode(mite_CHCR_strings, temp);
 768         addr = mite_io_addr + MITE_TCR(channel);
 769         printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
 770                readl(addr));
 771         addr = mite_io_addr + MITE_MCR(channel);
 772         printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
 773                temp = readl(addr));
 774         mite_decode(mite_MCR_strings, temp);
 775
 776         addr = mite_io_addr + MITE_MAR(channel);
 777         printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
 778                readl(addr));
 779         addr = mite_io_addr + MITE_DCR(channel);
 780         printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
 781                temp = readl(addr));
 782         mite_decode(mite_DCR_strings, temp);
 783         addr = mite_io_addr + MITE_DAR(channel);
 784         printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
 785                readl(addr));
 786         addr = mite_io_addr + MITE_LKCR(channel);
 787         printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
 788                temp = readl(addr));
 789         mite_decode(mite_LKCR_strings, temp);
 790         addr = mite_io_addr + MITE_LKAR(channel);
 791         printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
 792                readl(addr));
 793         addr = mite_io_addr + MITE_CHSR(channel);
 794         printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
 795                temp = readl(addr));
 796         mite_decode(mite_CHSR_strings, temp);
 797         addr = mite_io_addr + MITE_FCR(channel);
 798         printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
 799                readl(addr));
 800 }
 801 EXPORT_SYMBOL(mite_dump_regs);
 802
 803 static void mite_decode(char **bit_str, unsigned int bits)
 804 {
 805         int i;
 806
 807         for (i = 31; i >= 0; i--) {
 808                 if (bits & (1 << i))
 809                         printk(KERN_DEBUG " %s", bit_str[i]);
 810         }
 811         printk(KERN_DEBUG "\n");
 812 }
 813 EXPORT_SYMBOL(mite_decode);
 814 #endif
 815
 816 #ifdef MODULE
 817 int __init init_module(void)
 818 {
 819         mite_init();
 820         mite_list_devices();
 821
 822         return 0;
 823 }
 824
 825 void __exit cleanup_module(void)
 826 {
 827         mite_cleanup();
 828 }
 829 #endif
 830
 831 MODULE_AUTHOR("Comedi http://www.comedi.org");
 832 MODULE_DESCRIPTION("Comedi low-level driver");
 833 MODULE_LICENSE("GPL");