2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
5 * Copyright (C) 1999-2011, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: aiutils.c,v 1.26.2.1 2010-03-09 18:41:21 $
37 #include "siutils_priv.h"
39 #define BCM47162_DMP() (0)
44 get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
47 uint inv = 0, nom = 0;
50 ent = R_REG(si_osh(sih), *eromptr);
56 if ((ent & ER_VALID) == 0) {
61 if (ent == (ER_END | ER_VALID))
64 if ((ent & mask) == match)
70 SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
72 SI_VMSG((" after %d invalid and %d non-matching entries\n", inv, nom));
78 get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
79 uint32 *sizel, uint32 *sizeh)
83 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
84 if (((asd & ER_TAG1) != ER_ADD) ||
85 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
86 ((asd & AD_ST_MASK) != st)) {
87 /* This is not what we want, "push" it back */
91 *addrl = asd & AD_ADDR_MASK;
93 *addrh = get_erom_ent(sih, eromptr, 0, 0);
97 sz = asd & AD_SZ_MASK;
98 if (sz == AD_SZ_SZD) {
99 szd = get_erom_ent(sih, eromptr, 0, 0);
100 *sizel = szd & SD_SZ_MASK;
102 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
104 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
106 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
107 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
113 ai_hwfixup(si_info_t *sii)
117 /* parse the enumeration rom to identify all cores */
119 ai_scan(si_t *sih, void *regs, uint devid)
121 si_info_t *sii = SI_INFO(sih);
122 chipcregs_t *cc = (chipcregs_t *)regs;
123 uint32 erombase, *eromptr, *eromlim;
125 erombase = R_REG(sii->osh, &cc->eromptr);
127 switch (BUSTYPE(sih->bustype)) {
129 eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
133 /* Set wrappers address */
134 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
136 /* Now point the window at the erom */
137 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
143 eromptr = (uint32 *)(uintptr)erombase;
148 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
152 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
154 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
155 regs, erombase, eromptr, eromlim));
156 while (eromptr < eromlim) {
157 uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
158 uint32 mpd, asd, addrl, addrh, sizel, sizeh;
165 /* Grok a component */
166 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
167 if (cia == (ER_END | ER_VALID)) {
168 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
173 cib = get_erom_ent(sih, &eromptr, 0, 0);
175 if ((cib & ER_TAG) != ER_CI) {
176 SI_ERROR(("CIA not followed by CIB\n"));
180 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
181 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
182 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
183 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
184 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
185 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
186 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
188 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
189 "nsw = %d, nmp = %d & nsp = %d\n",
190 mfg, cid, crev, base, nmw, nsw, nmp, nsp));
192 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
194 if ((nmw + nsw == 0)) {
195 /* A component which is not a core */
196 if (cid == OOB_ROUTER_CORE_ID) {
197 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
198 &addrl, &addrh, &sizel, &sizeh);
200 sii->oob_router = addrl;
207 /* sii->eromptr[idx] = base; */
210 sii->coreid[idx] = cid;
212 for (i = 0; i < nmp; i++) {
213 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
214 if ((mpd & ER_TAG) != ER_MP) {
215 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
218 SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
219 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
220 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
223 /* First Slave Address Descriptor should be port 0:
224 * the main register space for the core
226 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
228 /* Try again to see if it is a bridge */
229 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
234 if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
235 SI_ERROR(("First Slave ASD for core 0x%04x malformed "
236 "(0x%08x)\n", cid, asd));
240 sii->coresba[idx] = addrl;
241 sii->coresba_size[idx] = sizel;
242 /* Get any more ASDs in port 0 */
245 asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
247 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
248 sii->coresba2[idx] = addrl;
249 sii->coresba2_size[idx] = sizel;
254 /* Go through the ASDs for other slave ports */
255 for (i = 1; i < nsp; i++) {
258 asd = get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE, &addrl, &addrh,
262 SI_ERROR((" SP %d has no address descriptors\n", i));
267 /* Now get master wrappers */
268 for (i = 0; i < nmw; i++) {
269 asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
272 SI_ERROR(("Missing descriptor for MW %d\n", i));
275 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
276 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
280 sii->wrapba[idx] = addrl;
283 /* And finally slave wrappers */
284 for (i = 0; i < nsw; i++) {
285 uint fwp = (nsp == 1) ? 0 : 1;
286 asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
289 SI_ERROR(("Missing descriptor for SW %d\n", i));
292 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
293 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
296 if ((nmw == 0) && (i == 0))
297 sii->wrapba[idx] = addrl;
300 /* Don't record bridges */
308 SI_ERROR(("Reached end of erom without finding END"));
315 /* This function changes the logical "focus" to the indicated core.
316 * Return the current core's virtual address.
319 ai_setcoreidx(si_t *sih, uint coreidx)
321 si_info_t *sii = SI_INFO(sih);
322 uint32 addr = sii->coresba[coreidx];
323 uint32 wrap = sii->wrapba[coreidx];
326 if (coreidx >= sii->numcores)
330 * If the user has provided an interrupt mask enabled function,
331 * then assert interrupts are disabled before switching the core.
333 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
335 switch (BUSTYPE(sih->bustype)) {
338 if (!sii->regs[coreidx]) {
339 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
340 ASSERT(GOODREGS(sii->regs[coreidx]));
342 sii->curmap = regs = sii->regs[coreidx];
343 if (!sii->wrappers[coreidx]) {
344 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
345 ASSERT(GOODREGS(sii->wrappers[coreidx]));
347 sii->curwrap = sii->wrappers[coreidx];
353 sii->curmap = regs = (void *)((uintptr)addr);
354 sii->curwrap = (void *)((uintptr)wrap);
365 sii->curidx = coreidx;
370 /* Return the number of address spaces in current core */
372 ai_numaddrspaces(si_t *sih)
377 /* Return the address of the nth address space in the current core */
379 ai_addrspace(si_t *sih, uint asidx)
388 return sii->coresba[cidx];
390 return sii->coresba2[cidx];
392 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
393 __FUNCTION__, asidx));
398 /* Return the size of the nth address space in the current core */
400 ai_addrspacesize(si_t *sih, uint asidx)
409 return sii->coresba_size[cidx];
411 return sii->coresba2_size[cidx];
413 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
414 __FUNCTION__, asidx));
426 if (BCM47162_DMP()) {
427 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __FUNCTION__));
432 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
436 ai_setint(si_t *sih, int siflag)
441 ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
443 si_info_t *sii = SI_INFO(sih);
444 uint32 *map = (uint32 *) sii->curwrap;
447 uint32 w = R_REG(sii->osh, map+(offset/4));
450 W_REG(sii->osh, map+(offset/4), val);
453 return (R_REG(sii->osh, map+(offset/4)));
457 ai_corevendor(si_t *sih)
463 cia = sii->cia[sii->curidx];
464 return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
468 ai_corerev(si_t *sih)
474 cib = sii->cib[sii->curidx];
475 return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
479 ai_iscoreup(si_t *sih)
487 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
488 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
492 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
493 * switch back to the original core, and return the new value.
495 * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
497 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
498 * and (on newer pci cores) chipcommon registers.
501 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
512 ASSERT(GOODIDX(coreidx));
513 ASSERT(regoff < SI_CORE_SIZE);
514 ASSERT((val & ~mask) == 0);
516 if (coreidx >= SI_MAXCORES)
519 if (BUSTYPE(sih->bustype) == SI_BUS) {
520 /* If internal bus, we can always get at everything */
522 /* map if does not exist */
523 if (!sii->regs[coreidx]) {
524 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
526 ASSERT(GOODREGS(sii->regs[coreidx]));
528 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
529 } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
530 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
532 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
533 /* Chipc registers are mapped at 12KB */
536 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
537 } else if (sii->pub.buscoreidx == coreidx) {
538 /* pci registers are at either in the last 2KB of an 8KB window
539 * or, in pcie and pci rev 13 at 8KB
543 r = (uint32 *)((char *)sii->curmap +
544 PCI_16KB0_PCIREGS_OFFSET + regoff);
546 r = (uint32 *)((char *)sii->curmap +
547 ((regoff >= SBCONFIGOFF) ?
548 PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
554 INTR_OFF(sii, intr_val);
556 /* save current core index */
557 origidx = si_coreidx(&sii->pub);
560 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
566 w = (R_REG(sii->osh, r) & ~mask) | val;
567 W_REG(sii->osh, r, w);
571 w = R_REG(sii->osh, r);
574 /* restore core index */
575 if (origidx != coreidx)
576 ai_setcoreidx(&sii->pub, origidx);
578 INTR_RESTORE(sii, intr_val);
585 ai_core_disable(si_t *sih, uint32 bits)
588 volatile uint32 dummy;
593 ASSERT(GOODREGS(sii->curwrap));
596 /* if core is already in reset, just return */
597 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
600 W_REG(sii->osh, &ai->ioctrl, bits);
601 dummy = R_REG(sii->osh, &ai->ioctrl);
604 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
608 /* reset and re-enable a core
610 * bits - core specific bits that are set during and after reset sequence
611 * resetbits - core specific bits that are set only during reset sequence
614 ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
618 volatile uint32 dummy;
621 ASSERT(GOODREGS(sii->curwrap));
625 * Must do the disable sequence first to work for arbitrary current core state.
627 ai_core_disable(sih, (bits | resetbits));
630 * Now do the initialization sequence.
632 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
633 dummy = R_REG(sii->osh, &ai->ioctrl);
634 W_REG(sii->osh, &ai->resetctrl, 0);
637 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
638 dummy = R_REG(sii->osh, &ai->ioctrl);
644 ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
652 if (BCM47162_DMP()) {
653 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
658 ASSERT(GOODREGS(sii->curwrap));
661 ASSERT((val & ~mask) == 0);
664 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
665 W_REG(sii->osh, &ai->ioctrl, w);
670 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
677 if (BCM47162_DMP()) {
678 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
683 ASSERT(GOODREGS(sii->curwrap));
686 ASSERT((val & ~mask) == 0);
689 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
690 W_REG(sii->osh, &ai->ioctrl, w);
693 return R_REG(sii->osh, &ai->ioctrl);
697 ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
704 if (BCM47162_DMP()) {
705 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0",
710 ASSERT(GOODREGS(sii->curwrap));
713 ASSERT((val & ~mask) == 0);
714 ASSERT((mask & ~SISF_CORE_BITS) == 0);
717 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
718 W_REG(sii->osh, &ai->iostatus, w);
721 return R_REG(sii->osh, &ai->iostatus);