2 * Misc utility routines for accessing the SOC Interconnects
3 * of Broadcom HNBU chips.
5 * Copyright (C) 1999-2011, Broadcom Corporation
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11 * following added to such license:
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15 * distribute the resulting executable under terms of your choice, provided that
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18 * derived from this software. The special exception does not apply to any
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21 * Notwithstanding the above, under no circumstances may you combine this
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23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: siutils.h,v 13.251.2.9 2011-01-13 18:53:43 $
32 * Data structure to export all chip specific common variables
33 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
36 uint socitype; /* SOCI_SB, SOCI_AI */
38 uint bustype; /* SI_BUS, PCI_BUS */
39 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
40 uint buscorerev; /* buscore rev */
41 uint buscoreidx; /* buscore index */
42 int ccrev; /* chip common core rev */
43 uint32 cccaps; /* chip common capabilities */
44 uint32 cccaps_ext; /* chip common capabilities extension */
45 int pmurev; /* pmu core rev */
46 uint32 pmucaps; /* pmu capabilities */
47 uint boardtype; /* board type */
48 uint boardvendor; /* board vendor */
49 uint boardflags; /* board flags */
50 uint boardflags2; /* board flags2 */
51 uint chip; /* chip number */
52 uint chiprev; /* chip revision */
53 uint chippkg; /* chip package option */
54 uint32 chipst; /* chip status */
55 bool issim; /* chip is in simulation or emulation */
56 uint socirev; /* SOC interconnect rev */
61 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
62 * for monolithic driver, it is readonly to prevent accident change
64 typedef const struct si_pub si_t;
67 * Many of the routines below take an 'sih' handle as their first arg.
68 * Allocate this by calling si_attach(). Free it by calling si_detach().
69 * At any one time, the sih is logically focused on one particular si core
70 * (the "current core").
71 * Use si_setcore() or si_setcoreidx() to change the association to another core.
73 #define SI_OSH NULL /* Use for si_kattach when no osh is available */
75 #define BADIDX (SI_MAXCORES + 1)
77 /* clkctl xtal what flags */
78 #define XTAL 0x1 /* primary crystal oscillator (2050) */
79 #define PLL 0x2 /* main chip pll */
82 #define CLK_FAST 0 /* force fast (pll) clock */
83 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
85 /* GPIO usage priorities */
86 #define GPIO_DRV_PRIORITY 0 /* Driver */
87 #define GPIO_APP_PRIORITY 1 /* Application */
88 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
90 /* GPIO pull up/down */
94 /* GPIO event regtype */
95 #define GPIO_REGEVT 0 /* GPIO register event */
96 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
97 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
100 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
102 /* SI routine enumeration: to be used by update function with multiple hooks */
103 #define SI_DOATTACH 1
107 #define ISSIM_ENAB(sih) 0
109 /* PMU clock/power control */
110 #if defined(BCMPMUCTL)
111 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
113 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
116 /* chipcommon clock/power control (exclusive with PMU's) */
117 #if defined(BCMPMUCTL) && BCMPMUCTL
118 #define CCCTL_ENAB(sih) (0)
119 #define CCPLL_ENAB(sih) (0)
121 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
122 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
125 typedef void (*gpio_handler_t)(uint32 stat, void *arg);
128 /* === exported functions === */
129 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
130 void *sdh, char **vars, uint *varsz);
131 extern si_t *si_kattach(osl_t *osh);
132 extern void si_detach(si_t *sih);
133 extern bool si_pci_war16165(si_t *sih);
135 extern uint si_corelist(si_t *sih, uint coreid[]);
136 extern uint si_coreid(si_t *sih);
137 extern uint si_flag(si_t *sih);
138 extern uint si_intflag(si_t *sih);
139 extern uint si_coreidx(si_t *sih);
140 extern uint si_coreunit(si_t *sih);
141 extern uint si_corevendor(si_t *sih);
142 extern uint si_corerev(si_t *sih);
143 extern void *si_osh(si_t *sih);
144 extern void si_setosh(si_t *sih, osl_t *osh);
145 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
146 extern void *si_coreregs(si_t *sih);
147 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
148 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
149 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
150 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
151 extern bool si_iscoreup(si_t *sih);
152 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
153 extern void *si_setcoreidx(si_t *sih, uint coreidx);
154 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
155 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
156 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
157 extern int si_numaddrspaces(si_t *sih);
158 extern uint32 si_addrspace(si_t *sih, uint asidx);
159 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
160 extern int si_corebist(si_t *sih);
161 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
162 extern void si_core_disable(si_t *sih, uint32 bits);
163 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
164 extern bool si_read_pmu_autopll(si_t *sih);
165 extern uint32 si_clock(si_t *sih);
166 extern uint32 si_alp_clock(si_t *sih);
167 extern uint32 si_ilp_clock(si_t *sih);
168 extern void si_pci_setup(si_t *sih, uint coremask);
169 extern void si_pcmcia_init(si_t *sih);
170 extern void si_setint(si_t *sih, int siflag);
171 extern bool si_backplane64(si_t *sih);
172 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
173 void *intrsenabled_fn, void *intr_arg);
174 extern void si_deregister_intr_callback(si_t *sih);
175 extern void si_clkctl_init(si_t *sih);
176 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
177 extern bool si_clkctl_cc(si_t *sih, uint mode);
178 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
179 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
180 extern void si_btcgpiowar(si_t *sih);
181 extern bool si_deviceremoved(si_t *sih);
182 extern uint32 si_socram_size(si_t *sih);
183 extern uint32 si_socdevram_size(si_t *sih);
184 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect);
185 extern bool si_socdevram_pkg(si_t *sih);
187 extern void si_watchdog(si_t *sih, uint ticks);
188 extern void si_watchdog_ms(si_t *sih, uint32 ms);
189 extern void *si_gpiosetcore(si_t *sih);
190 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
191 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
192 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
193 extern uint32 si_gpioin(si_t *sih);
194 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
195 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
196 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
197 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
198 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
199 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
200 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
201 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
203 /* GPIO event handlers */
204 extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg);
205 extern void si_gpio_handler_unregister(si_t *sih, void* gpioh);
206 extern void si_gpio_handler_process(si_t *sih);
208 /* Wake-on-wireless-LAN (WOWL) */
209 extern bool si_pci_pmecap(si_t *sih);
211 extern bool si_pci_fastpmecap(struct osl_info *osh);
212 extern bool si_pci_pmestat(si_t *sih);
213 extern void si_pci_pmeclr(si_t *sih);
214 extern void si_pci_pmeen(si_t *sih);
215 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
217 extern void si_sdio_init(si_t *sih);
219 extern uint16 si_d11_devid(si_t *sih);
220 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
221 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
223 #define si_eci(sih) 0
224 #define si_eci_init(sih) (0)
225 #define si_eci_notify_bt(sih, type, val) (0)
226 #define si_seci(sih) 0
227 static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;}
228 #define si_seci_down(sih) do { } while (0)
231 extern bool si_is_otp_disabled(si_t *sih);
232 extern bool si_is_otp_powered(si_t *sih);
233 extern void si_otp_power(si_t *sih, bool on);
235 /* SPROM availability */
236 extern bool si_is_sprom_available(si_t *sih);
237 extern bool si_is_sprom_enabled(si_t *sih);
238 extern void si_sprom_enable(si_t *sih, bool enable);
240 /* OTP/SROM CIS stuff */
241 extern int si_cis_source(si_t *sih);
242 #define CIS_DEFAULT 0
246 /* Fab-id information */
247 #define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */
248 #define CSM_FAB7 0x1 /* CSM Fab7 chip */
249 #define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */
250 #define SMIC_FAB4 0x3 /* SMIC Fab4 chip */
251 extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw);
254 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
255 * The returned path is NULL terminated and has trailing '/'.
256 * Return 0 on success, nonzero otherwise.
258 extern int si_devpath(si_t *sih, char *path, int size);
259 /* Read variable with prepending the devpath to the name */
260 extern char *si_getdevpathvar(si_t *sih, const char *name);
261 extern int si_getdevpathintvar(si_t *sih, const char *name);
264 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
265 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
266 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
267 extern void si_pci_sleep(si_t *sih);
268 extern void si_pci_down(si_t *sih);
269 extern void si_pci_up(si_t *sih);
270 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
271 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
272 extern int si_pci_fixcfg(si_t *sih);
273 extern uint si_pll_reset(si_t *sih);
275 /* === debug routines === */
277 extern bool si_taclear(si_t *sih, bool details);
281 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
282 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
284 char *si_getnvramflvar(si_t *sih, const char *name);
286 void si_uartmuxenable(si_t *sih, bool enable);
287 #endif /* _siutils_h_ */