2 * 'Standard' SDIO HOST CONTROLLER driver
4 * Copyright (C) 1999-2011, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
24 * $Id: bcmsdstd.h,v 13.21.2.6 2010-11-15 18:14:01 $
29 /* global msglevel for debug messages - bitvals come from sdiovar.h */
30 #define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
38 #define sd_sync_dma(sd, read, nbytes)
39 #define sd_init_dma(sd)
40 #define sd_ack_intr(sd)
41 #define sd_wakeup(sd);
42 /* Allocate/init/free per-OS private data */
43 extern int sdstd_osinit(sdioh_info_t *sd);
44 extern void sdstd_osfree(sdioh_info_t *sd);
48 #define SDIOH_ASSERT(exp) \
50 printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
53 #define BLOCK_SIZE_4318 64
54 #define BLOCK_SIZE_4328 512
56 /* internal return code */
60 /* private bus modes */
61 #define SDIOH_MODE_SPI 0
62 #define SDIOH_MODE_SD1 1
63 #define SDIOH_MODE_SD4 2
65 #define MAX_SLOTS 6 /* For PCI: Only 6 BAR entries => 6 slots */
66 #define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */
68 #define SDIOH_TYPE_ARASAN_HDK 1
69 #define SDIOH_TYPE_BCM27XX 2
70 #define SDIOH_TYPE_TI_PCIXX21 4 /* TI PCIxx21 Standard Host Controller */
71 #define SDIOH_TYPE_RICOH_R5C822 5 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */
72 #define SDIOH_TYPE_JMICRON 6 /* JMicron Standard SDIO Host Controller */
74 /* For linux, allow yielding for dongle */
77 /* Expected card status value for CMD7 */
78 #define SDIOH_CMD7_EXP_STATUS 0x00001E00
80 #define RETRIES_LARGE 100000
81 #define RETRIES_SMALL 100
84 #define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
85 #define USE_MULTIBLOCK 0x4
87 #define USE_FIFO 0x8 /* Fifo vs non-fifo */
89 #define CLIENT_INTR 0x100 /* Get rid of this! */
92 #define HC_INTR_RETUNING 0x1000
97 uint cfg_bar; /* pci cfg address for bar */
98 uint32 caps; /* cached value of capabilities reg */
99 uint32 curr_caps; /* max current capabilities reg */
101 osl_t *osh; /* osh handler */
102 volatile char *mem_space; /* pci device memory va */
103 uint lockcount; /* nest count of sdstd_lock() calls */
104 bool client_intr_enabled; /* interrupt connnected flag */
105 bool intr_handler_valid; /* client driver interrupt handler valid */
106 sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
107 void *intr_handler_arg; /* argument to call interrupt handler */
108 bool initialized; /* card initialized */
109 uint target_dev; /* Target device ID */
110 uint16 intmask; /* Current active interrupts */
111 void *sdos_info; /* Pointer to per-OS private data */
113 uint32 controller_type; /* Host controller type */
114 uint8 version; /* Host Controller Spec Compliance Version */
115 uint irq; /* Client irq */
116 int intrcount; /* Client interrupts */
117 int local_intrcount; /* Controller interrupts */
118 bool host_init_done; /* Controller initted */
119 bool card_init_done; /* Client SDIO interface initted */
120 bool polled_mode; /* polling for command completion */
122 bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
123 /* Must be on for sd_multiblock to be effective */
124 bool use_client_ints; /* If this is false, make sure to restore */
125 /* polling hack in wl_linux.c:wl_timer() */
126 int adapter_slot; /* Maybe dealing with multiple slots/controllers */
127 int sd_mode; /* SD1/SD4/SPI */
128 int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
129 uint32 data_xfer_count; /* Current transfer */
130 uint16 card_rca; /* Current Address */
131 int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
132 uint8 num_funcs; /* Supported funcs on client */
134 uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
135 void *dma_buf; /* DMA Buffer virtual address */
136 ulong dma_phys; /* DMA Buffer physical address */
137 void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */
138 ulong adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */
140 /* adjustments needed to make the dma align properly */
142 ulong dma_start_phys;
143 uint alloced_dma_size;
144 void *adma2_dscr_start_buf;
145 ulong adma2_dscr_start_phys;
146 uint alloced_adma2_dscr_size;
148 int r_cnt; /* rx count */
149 int t_cnt; /* tx_count */
150 bool got_hcint; /* local interrupt flag */
151 uint16 last_intrstatus; /* to cache intrstatus */
152 int host_UHSISupported; /* whether UHSI is supported for HC. */
153 int card_UHSI_voltage_Supported; /* whether UHSI is supported for
154 * Card in terms of Voltage [1.8 or 3.3].
156 int global_UHSI_Supp; /* type of UHSI support in both host and card.
157 * HOST_SDR_UNSUPP: capabilities not supported/matched
158 * HOST_SDR_12_25: SDR12 and SDR25 supported
159 * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd
161 int sd3_dat_state; /* data transfer state used for retuning check */
162 int sd3_tun_state; /* tuning state used for retuning check */
163 bool sd3_tuning_reqd; /* tuning requirement parameter */
164 uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */
167 #define DMA_MODE_NONE 0
168 #define DMA_MODE_SDMA 1
169 #define DMA_MODE_ADMA1 2
170 #define DMA_MODE_ADMA2 3
171 #define DMA_MODE_ADMA2_64 4
172 #define DMA_MODE_AUTO -1
174 #define USE_DMA(sd) ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE))
176 /* SDIO Host Control Register DMA Mode Definitions */
177 #define SDIOH_SDMA_MODE 0
178 #define SDIOH_ADMA1_MODE 1
179 #define SDIOH_ADMA2_MODE 2
180 #define SDIOH_ADMA2_64_MODE 3
182 #define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */
183 #define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */
184 #define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */
185 #define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */
186 #define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */
187 #define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */
188 #define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */
189 #define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */
192 /* States for Tuning and corr data */
193 #define TUNING_IDLE 0
194 #define TUNING_START 1
195 #define TUNING_START_AFTER_DAT 2
196 #define TUNING_ONGOING 3
198 #define DATA_TRANSFER_IDLE 0
199 #define DATA_TRANSFER_ONGOING 1
202 /* ADMA2 Descriptor Table Entry for 32-bit Address */
203 typedef struct adma2_dscr_32b {
208 /* ADMA1 Descriptor Table Entry */
209 typedef struct adma1_dscr {
210 uint32 phys_addr_attr;
213 /************************************************************
214 * Internal interfaces: per-port references into bcmsdstd.c
217 /* Global message bits */
218 extern uint sd_msglevel;
220 /* OS-independent interrupt handler */
221 extern bool check_client_intr(sdioh_info_t *sd);
223 /* Core interrupt enable/disable of device interrupts */
224 extern void sdstd_devintr_on(sdioh_info_t *sd);
225 extern void sdstd_devintr_off(sdioh_info_t *sd);
227 /* Enable/disable interrupts for local controller events */
228 extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err);
229 extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err);
231 /* Wait for specified interrupt and error bits to be set */
232 extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err);
235 /**************************************************************
236 * Internal interfaces: bcmsdstd.c references to per-port code
239 /* Register mapping routines */
240 extern uint32 *sdstd_reg_map(osl_t *osh, int32 addr, int size);
241 extern void sdstd_reg_unmap(osl_t *osh, int32 addr, int size);
243 /* Interrupt (de)registration routines */
244 extern int sdstd_register_irq(sdioh_info_t *sd, uint irq);
245 extern void sdstd_free_irq(uint irq, sdioh_info_t *sd);
247 /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
248 extern void sdstd_lock(sdioh_info_t *sd);
249 extern void sdstd_unlock(sdioh_info_t *sd);
250 extern void sdstd_waitlockfree(sdioh_info_t *sd);
252 /* OS-specific wait-for-interrupt-or-status */
253 extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits);
256 /* used by bcmsdstd_linux [implemented in sdstd] */
257 extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd);
258 extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd);
259 extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd);
260 extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd);
261 extern int sdstd_3_get_tune_state(sdioh_info_t *sd);
262 extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state);
263 extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd);
264 extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd);
265 extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode);
267 /* used by sdstd [implemented in bcmsdstd_linux/ndis] */
268 extern void sdstd_3_start_tuning(sdioh_info_t *sd);
269 extern void sdstd_3_osinit_tuning(sdioh_info_t *sd);
270 extern void sdstd_3_osclean_tuning(sdioh_info_t *sd);
274 #endif /* _BCM_SD_STD_H */