drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  49
  50 /**
  51  *  ixgbe_identify_phy_generic - Get physical layer module
  52  *  @hw: pointer to hardware structure
  53  *
  54  *  Determines the physical layer module found on the current adapter.
  55  **/
  56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  57 {
  58         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  59         u32 phy_addr;
  60
  61         if (hw->phy.type == ixgbe_phy_unknown) {
  62                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  63                         hw->phy.mdio.prtad = phy_addr;
  64                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  65                                 ixgbe_get_phy_id(hw);
  66                                 hw->phy.type =
  67                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  68                                 status = 0;
  69                                 break;
  70                         }
  71                 }
  72                 /* clear value if nothing found */
  73                 hw->phy.mdio.prtad = 0;
  74         } else {
  75                 status = 0;
  76         }
  77
  78         return status;
  79 }
  80
  81 /**
  82  *  ixgbe_get_phy_id - Get the phy type
  83  *  @hw: pointer to hardware structure
  84  *
  85  **/
  86 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  87 {
  88         u32 status;
  89         u16 phy_id_high = 0;
  90         u16 phy_id_low = 0;
  91
  92         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
  93                                       &phy_id_high);
  94
  95         if (status == 0) {
  96                 hw->phy.id = (u32)(phy_id_high << 16);
  97                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
  98                                               &phy_id_low);
  99                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 100                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 101         }
 102         return status;
 103 }
 104
 105 /**
 106  *  ixgbe_get_phy_type_from_id - Get the phy type
 107  *  @hw: pointer to hardware structure
 108  *
 109  **/
 110 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 111 {
 112         enum ixgbe_phy_type phy_type;
 113
 114         switch (phy_id) {
 115         case TN1010_PHY_ID:
 116                 phy_type = ixgbe_phy_tn;
 117                 break;
 118         case QT2022_PHY_ID:
 119                 phy_type = ixgbe_phy_qt;
 120                 break;
 121         case ATH_PHY_ID:
 122                 phy_type = ixgbe_phy_nl;
 123                 break;
 124         default:
 125                 phy_type = ixgbe_phy_unknown;
 126                 break;
 127         }
 128
 129         return phy_type;
 130 }
 131
 132 /**
 133  *  ixgbe_reset_phy_generic - Performs a PHY reset
 134  *  @hw: pointer to hardware structure
 135  **/
 136 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 137 {
 138         /* Don't reset PHY if it's shut down due to overtemp. */
 139         if (!hw->phy.reset_if_overtemp &&
 140             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 141                 return 0;
 142
 143         /*
 144          * Perform soft PHY reset to the PHY_XS.
 145          * This will cause a soft reset to the PHY
 146          */
 147         return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 148                                      MDIO_CTRL1_RESET);
 149 }
 150
 151 /**
 152  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 153  *  @hw: pointer to hardware structure
 154  *  @reg_addr: 32 bit address of PHY register to read
 155  *  @phy_data: Pointer to read data from PHY register
 156  **/
 157 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 158                                u32 device_type, u16 *phy_data)
 159 {
 160         u32 command;
 161         u32 i;
 162         u32 data;
 163         s32 status = 0;
 164         u16 gssr;
 165
 166         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 167                 gssr = IXGBE_GSSR_PHY1_SM;
 168         else
 169                 gssr = IXGBE_GSSR_PHY0_SM;
 170
 171         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 172                 status = IXGBE_ERR_SWFW_SYNC;
 173
 174         if (status == 0) {
 175                 /* Setup and write the address cycle command */
 176                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 177                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 178                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 179                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 180
 181                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 182
 183                 /*
 184                  * Check every 10 usec to see if the address cycle completed.
 185                  * The MDI Command bit will clear when the operation is
 186                  * complete
 187                  */
 188                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 189                         udelay(10);
 190
 191                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 192
 193                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 194                                 break;
 195                 }
 196
 197                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 198                         hw_dbg(hw, "PHY address command did not complete.\n");
 199                         status = IXGBE_ERR_PHY;
 200                 }
 201
 202                 if (status == 0) {
 203                         /*
 204                          * Address cycle complete, setup and write the read
 205                          * command
 206                          */
 207                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 208                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 209                                    (hw->phy.mdio.prtad <<
 210                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 211                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 212
 213                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 214
 215                         /*
 216                          * Check every 10 usec to see if the address cycle
 217                          * completed. The MDI Command bit will clear when the
 218                          * operation is complete
 219                          */
 220                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 221                                 udelay(10);
 222
 223                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 224
 225                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 226                                         break;
 227                         }
 228
 229                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 230                                 hw_dbg(hw, "PHY read command didn't complete\n");
 231                                 status = IXGBE_ERR_PHY;
 232                         } else {
 233                                 /*
 234                                  * Read operation is complete.  Get the data
 235                                  * from MSRWD
 236                                  */
 237                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 238                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 239                                 *phy_data = (u16)(data);
 240                         }
 241                 }
 242
 243                 ixgbe_release_swfw_sync(hw, gssr);
 244         }
 245
 246         return status;
 247 }
 248
 249 /**
 250  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 251  *  @hw: pointer to hardware structure
 252  *  @reg_addr: 32 bit PHY register to write
 253  *  @device_type: 5 bit device type
 254  *  @phy_data: Data to write to the PHY register
 255  **/
 256 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 257                                 u32 device_type, u16 phy_data)
 258 {
 259         u32 command;
 260         u32 i;
 261         s32 status = 0;
 262         u16 gssr;
 263
 264         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 265                 gssr = IXGBE_GSSR_PHY1_SM;
 266         else
 267                 gssr = IXGBE_GSSR_PHY0_SM;
 268
 269         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 270                 status = IXGBE_ERR_SWFW_SYNC;
 271
 272         if (status == 0) {
 273                 /* Put the data in the MDI single read and write data register*/
 274                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 275
 276                 /* Setup and write the address cycle command */
 277                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 278                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 279                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 280                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 281
 282                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 283
 284                 /*
 285                  * Check every 10 usec to see if the address cycle completed.
 286                  * The MDI Command bit will clear when the operation is
 287                  * complete
 288                  */
 289                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 290                         udelay(10);
 291
 292                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 293
 294                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 295                                 break;
 296                 }
 297
 298                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 299                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 300                         status = IXGBE_ERR_PHY;
 301                 }
 302
 303                 if (status == 0) {
 304                         /*
 305                          * Address cycle complete, setup and write the write
 306                          * command
 307                          */
 308                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 309                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 310                                    (hw->phy.mdio.prtad <<
 311                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 312                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 313
 314                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 315
 316                         /*
 317                          * Check every 10 usec to see if the address cycle
 318                          * completed. The MDI Command bit will clear when the
 319                          * operation is complete
 320                          */
 321                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 322                                 udelay(10);
 323
 324                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 325
 326                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 327                                         break;
 328                         }
 329
 330                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 331                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 332                                 status = IXGBE_ERR_PHY;
 333                         }
 334                 }
 335
 336                 ixgbe_release_swfw_sync(hw, gssr);
 337         }
 338
 339         return status;
 340 }
 341
 342 /**
 343  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 344  *  @hw: pointer to hardware structure
 345  *
 346  *  Restart autonegotiation and PHY and waits for completion.
 347  **/
 348 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 349 {
 350         s32 status = IXGBE_NOT_IMPLEMENTED;
 351         u32 time_out;
 352         u32 max_time_out = 10;
 353         u16 autoneg_reg;
 354
 355         /*
 356          * Set advertisement settings in PHY based on autoneg_advertised
 357          * settings. If autoneg_advertised = 0, then advertise default values
 358          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 359          * for a 1G.
 360          */
 361         hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
 362
 363         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 364                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 365         else
 366                 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 367
 368         hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
 369
 370         /* Restart PHY autonegotiation and wait for completion */
 371         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
 372
 373         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 374
 375         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
 376
 377         /* Wait for autonegotiation to finish */
 378         for (time_out = 0; time_out < max_time_out; time_out++) {
 379                 udelay(10);
 380                 /* Restart PHY autonegotiation and wait for completion */
 381                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
 382                                               &autoneg_reg);
 383
 384                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 385                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 386                         status = 0;
 387                         break;
 388                 }
 389         }
 390
 391         if (time_out == max_time_out)
 392                 status = IXGBE_ERR_LINK_SETUP;
 393
 394         return status;
 395 }
 396
 397 /**
 398  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 399  *  @hw: pointer to hardware structure
 400  *  @speed: new link speed
 401  *  @autoneg: true if autonegotiation enabled
 402  **/
 403 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 404                                        ixgbe_link_speed speed,
 405                                        bool autoneg,
 406                                        bool autoneg_wait_to_complete)
 407 {
 408
 409         /*
 410          * Clear autoneg_advertised and set new values based on input link
 411          * speed.
 412          */
 413         hw->phy.autoneg_advertised = 0;
 414
 415         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 416                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 417
 418         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 419                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 420
 421         /* Setup link based on the new speed settings */
 422         hw->phy.ops.setup_link(hw);
 423
 424         return 0;
 425 }
 426
 427 /**
 428  *  ixgbe_reset_phy_nl - Performs a PHY reset
 429  *  @hw: pointer to hardware structure
 430  **/
 431 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 432 {
 433         u16 phy_offset, control, eword, edata, block_crc;
 434         bool end_data = false;
 435         u16 list_offset, data_offset;
 436         u16 phy_data = 0;
 437         s32 ret_val = 0;
 438         u32 i;
 439
 440         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 441
 442         /* reset the PHY and poll for completion */
 443         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 444                               (phy_data | MDIO_CTRL1_RESET));
 445
 446         for (i = 0; i < 100; i++) {
 447                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 448                                      &phy_data);
 449                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 450                         break;
 451                 msleep(10);
 452         }
 453
 454         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 455                 hw_dbg(hw, "PHY reset did not complete.\n");
 456                 ret_val = IXGBE_ERR_PHY;
 457                 goto out;
 458         }
 459
 460         /* Get init offsets */
 461         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 462                                                       &data_offset);
 463         if (ret_val != 0)
 464                 goto out;
 465
 466         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 467         data_offset++;
 468         while (!end_data) {
 469                 /*
 470                  * Read control word from PHY init contents offset
 471                  */
 472                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 473                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 474                            IXGBE_CONTROL_SHIFT_NL;
 475                 edata = eword & IXGBE_DATA_MASK_NL;
 476                 switch (control) {
 477                 case IXGBE_DELAY_NL:
 478                         data_offset++;
 479                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 480                         msleep(edata);
 481                         break;
 482                 case IXGBE_DATA_NL:
 483                         hw_dbg(hw, "DATA:\n");
 484                         data_offset++;
 485                         hw->eeprom.ops.read(hw, data_offset++,
 486                                             &phy_offset);
 487                         for (i = 0; i < edata; i++) {
 488                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 489                                 hw->phy.ops.write_reg(hw, phy_offset,
 490                                                       MDIO_MMD_PMAPMD, eword);
 491                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 492                                        phy_offset);
 493                                 data_offset++;
 494                                 phy_offset++;
 495                         }
 496                         break;
 497                 case IXGBE_CONTROL_NL:
 498                         data_offset++;
 499                         hw_dbg(hw, "CONTROL:\n");
 500                         if (edata == IXGBE_CONTROL_EOL_NL) {
 501                                 hw_dbg(hw, "EOL\n");
 502                                 end_data = true;
 503                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 504                                 hw_dbg(hw, "SOL\n");
 505                         } else {
 506                                 hw_dbg(hw, "Bad control value\n");
 507                                 ret_val = IXGBE_ERR_PHY;
 508                                 goto out;
 509                         }
 510                         break;
 511                 default:
 512                         hw_dbg(hw, "Bad control type\n");
 513                         ret_val = IXGBE_ERR_PHY;
 514                         goto out;
 515                 }
 516         }
 517
 518 out:
 519         return ret_val;
 520 }
 521
 522 /**
 523  *  ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
 524  *                                      the PHY type.
 525  *  @hw: pointer to hardware structure
 526  *
 527  *  Searches for and indentifies the SFP module.  Assings appropriate PHY type.
 528  **/
 529 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 530 {
 531         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 532         u32 vendor_oui = 0;
 533         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 534         u8 identifier = 0;
 535         u8 comp_codes_1g = 0;
 536         u8 comp_codes_10g = 0;
 537         u8 oui_bytes[3] = {0, 0, 0};
 538         u8 cable_tech = 0;
 539         u8 cable_spec = 0;
 540         u16 enforce_sfp = 0;
 541
 542         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 543                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 544                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 545                 goto out;
 546         }
 547
 548         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
 549                                              &identifier);
 550
 551         if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
 552                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 553                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 554                 if (hw->phy.type != ixgbe_phy_nl) {
 555                         hw->phy.id = 0;
 556                         hw->phy.type = ixgbe_phy_unknown;
 557                 }
 558                 goto out;
 559         }
 560
 561         if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
 562                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
 563                                             &comp_codes_1g);
 564                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
 565                                             &comp_codes_10g);
 566                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
 567                                             &cable_tech);
 568
 569                 /* ID Module
 570                  * =========
 571                  * 0    SFP_DA_CU
 572                  * 1    SFP_SR
 573                  * 2    SFP_LR
 574                  * 3    SFP_DA_CORE0 - 82599-specific
 575                  * 4    SFP_DA_CORE1 - 82599-specific
 576                  * 5    SFP_SR/LR_CORE0 - 82599-specific
 577                  * 6    SFP_SR/LR_CORE1 - 82599-specific
 578                  * 7    SFP_act_lmt_DA_CORE0 - 82599-specific
 579                  * 8    SFP_act_lmt_DA_CORE1 - 82599-specific
 580                  * 9    SFP_1g_cu_CORE0 - 82599-specific
 581                  * 10   SFP_1g_cu_CORE1 - 82599-specific
 582                  */
 583                 if (hw->mac.type == ixgbe_mac_82598EB) {
 584                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 585                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 586                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 587                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 588                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 589                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 590                         else
 591                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 592                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 593                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 594                                 if (hw->bus.lan_id == 0)
 595                                         hw->phy.sfp_type =
 596                                                      ixgbe_sfp_type_da_cu_core0;
 597                                 else
 598                                         hw->phy.sfp_type =
 599                                                      ixgbe_sfp_type_da_cu_core1;
 600                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 601                                 hw->phy.ops.read_i2c_eeprom(
 602                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
 603                                                 &cable_spec);
 604                                 if (cable_spec &
 605                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 606                                         if (hw->bus.lan_id == 0)
 607                                                 hw->phy.sfp_type =
 608                                                 ixgbe_sfp_type_da_act_lmt_core0;
 609                                         else
 610                                                 hw->phy.sfp_type =
 611                                                 ixgbe_sfp_type_da_act_lmt_core1;
 612                                 } else {
 613                                         hw->phy.sfp_type =
 614                                                 ixgbe_sfp_type_unknown;
 615                                 }
 616                         } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 617                                 if (hw->bus.lan_id == 0)
 618                                         hw->phy.sfp_type =
 619                                                       ixgbe_sfp_type_srlr_core0;
 620                                 else
 621                                         hw->phy.sfp_type =
 622                                                       ixgbe_sfp_type_srlr_core1;
 623                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 624                                 if (hw->bus.lan_id == 0)
 625                                         hw->phy.sfp_type =
 626                                                       ixgbe_sfp_type_srlr_core0;
 627                                 else
 628                                         hw->phy.sfp_type =
 629                                                       ixgbe_sfp_type_srlr_core1;
 630                         else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
 631                                 if (hw->bus.lan_id == 0)
 632                                         hw->phy.sfp_type =
 633                                                 ixgbe_sfp_type_1g_cu_core0;
 634                                 else
 635                                         hw->phy.sfp_type =
 636                                                 ixgbe_sfp_type_1g_cu_core1;
 637                         else
 638                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 639                 }
 640
 641                 if (hw->phy.sfp_type != stored_sfp_type)
 642                         hw->phy.sfp_setup_needed = true;
 643
 644                 /* Determine if the SFP+ PHY is dual speed or not. */
 645                 hw->phy.multispeed_fiber = false;
 646                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 647                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 648                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 649                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 650                         hw->phy.multispeed_fiber = true;
 651
 652                 /* Determine PHY vendor */
 653                 if (hw->phy.type != ixgbe_phy_nl) {
 654                         hw->phy.id = identifier;
 655                         hw->phy.ops.read_i2c_eeprom(hw,
 656                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 657                                                     &oui_bytes[0]);
 658                         hw->phy.ops.read_i2c_eeprom(hw,
 659                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 660                                                     &oui_bytes[1]);
 661                         hw->phy.ops.read_i2c_eeprom(hw,
 662                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 663                                                     &oui_bytes[2]);
 664
 665                         vendor_oui =
 666                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
 667                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
 668                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
 669
 670                         switch (vendor_oui) {
 671                         case IXGBE_SFF_VENDOR_OUI_TYCO:
 672                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 673                                         hw->phy.type =
 674                                                 ixgbe_phy_sfp_passive_tyco;
 675                                 break;
 676                         case IXGBE_SFF_VENDOR_OUI_FTL:
 677                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
 678                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
 679                                 else
 680                                         hw->phy.type = ixgbe_phy_sfp_ftl;
 681                                 break;
 682                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
 683                                 hw->phy.type = ixgbe_phy_sfp_avago;
 684                                 break;
 685                         case IXGBE_SFF_VENDOR_OUI_INTEL:
 686                                 hw->phy.type = ixgbe_phy_sfp_intel;
 687                                 break;
 688                         default:
 689                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 690                                         hw->phy.type =
 691                                                 ixgbe_phy_sfp_passive_unknown;
 692                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
 693                                         hw->phy.type =
 694                                                 ixgbe_phy_sfp_active_unknown;
 695                                 else
 696                                         hw->phy.type = ixgbe_phy_sfp_unknown;
 697                                 break;
 698                         }
 699                 }
 700
 701                 /* All passive DA cables are supported */
 702                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
 703                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
 704                         status = 0;
 705                         goto out;
 706                 }
 707
 708                 /* Verify supported 1G SFP modules */
 709                 if (comp_codes_10g == 0 &&
 710                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
 711                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
 712                         hw->phy.type = ixgbe_phy_sfp_unsupported;
 713                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 714                         goto out;
 715                 }
 716
 717                 /* Anything else 82598-based is supported */
 718                 if (hw->mac.type == ixgbe_mac_82598EB) {
 719                         status = 0;
 720                         goto out;
 721                 }
 722
 723                 /* This is guaranteed to be 82599, no need to check for NULL */
 724                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
 725                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
 726                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
 727                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
 728                         /* Make sure we're a supported PHY type */
 729                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
 730                                 status = 0;
 731                         } else {
 732                                 hw_dbg(hw, "SFP+ module not supported\n");
 733                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 734                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 735                         }
 736                 } else {
 737                         status = 0;
 738                 }
 739         }
 740
 741 out:
 742         return status;
 743 }
 744
 745 /**
 746  *  ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
 747  *  if it supports a given SFP+ module type, if so it returns the offsets to the
 748  *  phy init sequence block.
 749  *  @hw: pointer to hardware structure
 750  *  @list_offset: offset to the SFP ID list
 751  *  @data_offset: offset to the SFP data block
 752  **/
 753 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 754                                         u16 *list_offset,
 755                                         u16 *data_offset)
 756 {
 757         u16 sfp_id;
 758         u16 sfp_type = hw->phy.sfp_type;
 759
 760         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
 761                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 762
 763         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 764                 return IXGBE_ERR_SFP_NOT_PRESENT;
 765
 766         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
 767             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
 768                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 769
 770         /*
 771          * Limiting active cables and 1G Phys must be initialized as
 772          * SR modules
 773          */
 774         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
 775             sfp_type == ixgbe_sfp_type_1g_cu_core0)
 776                 sfp_type = ixgbe_sfp_type_srlr_core0;
 777         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
 778                  sfp_type == ixgbe_sfp_type_1g_cu_core1)
 779                 sfp_type = ixgbe_sfp_type_srlr_core1;
 780
 781         /* Read offset to PHY init contents */
 782         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
 783
 784         if ((!*list_offset) || (*list_offset == 0xFFFF))
 785                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
 786
 787         /* Shift offset to first ID word */
 788         (*list_offset)++;
 789
 790         /*
 791          * Find the matching SFP ID in the EEPROM
 792          * and program the init sequence
 793          */
 794         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
 795
 796         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
 797                 if (sfp_id == sfp_type) {
 798                         (*list_offset)++;
 799                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
 800                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
 801                                 hw_dbg(hw, "SFP+ module not supported\n");
 802                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 803                         } else {
 804                                 break;
 805                         }
 806                 } else {
 807                         (*list_offset) += 2;
 808                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
 809                                 return IXGBE_ERR_PHY;
 810                 }
 811         }
 812
 813         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
 814                 hw_dbg(hw, "No matching SFP+ module found\n");
 815                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 816         }
 817
 818         return 0;
 819 }
 820
 821 /**
 822  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
 823  *  @hw: pointer to hardware structure
 824  *  @byte_offset: EEPROM byte offset to read
 825  *  @eeprom_data: value read
 826  *
 827  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 828  **/
 829 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 830                                   u8 *eeprom_data)
 831 {
 832         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
 833                                          IXGBE_I2C_EEPROM_DEV_ADDR,
 834                                          eeprom_data);
 835 }
 836
 837 /**
 838  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
 839  *  @hw: pointer to hardware structure
 840  *  @byte_offset: EEPROM byte offset to write
 841  *  @eeprom_data: value to write
 842  *
 843  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
 844  **/
 845 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 846                                    u8 eeprom_data)
 847 {
 848         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
 849                                           IXGBE_I2C_EEPROM_DEV_ADDR,
 850                                           eeprom_data);
 851 }
 852
 853 /**
 854  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
 855  *  @hw: pointer to hardware structure
 856  *  @byte_offset: byte offset to read
 857  *  @data: value read
 858  *
 859  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
 860  *  a specified deivce address.
 861  **/
 862 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 863                                 u8 dev_addr, u8 *data)
 864 {
 865         s32 status = 0;
 866         u32 max_retry = 1;
 867         u32 retry = 0;
 868         bool nack = 1;
 869
 870         do {
 871                 ixgbe_i2c_start(hw);
 872
 873                 /* Device Address and write indication */
 874                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 875                 if (status != 0)
 876                         goto fail;
 877
 878                 status = ixgbe_get_i2c_ack(hw);
 879                 if (status != 0)
 880                         goto fail;
 881
 882                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 883                 if (status != 0)
 884                         goto fail;
 885
 886                 status = ixgbe_get_i2c_ack(hw);
 887                 if (status != 0)
 888                         goto fail;
 889
 890                 ixgbe_i2c_start(hw);
 891
 892                 /* Device Address and read indication */
 893                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
 894                 if (status != 0)
 895                         goto fail;
 896
 897                 status = ixgbe_get_i2c_ack(hw);
 898                 if (status != 0)
 899                         goto fail;
 900
 901                 status = ixgbe_clock_in_i2c_byte(hw, data);
 902                 if (status != 0)
 903                         goto fail;
 904
 905                 status = ixgbe_clock_out_i2c_bit(hw, nack);
 906                 if (status != 0)
 907                         goto fail;
 908
 909                 ixgbe_i2c_stop(hw);
 910                 break;
 911
 912 fail:
 913                 ixgbe_i2c_bus_clear(hw);
 914                 retry++;
 915                 if (retry < max_retry)
 916                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
 917                 else
 918                         hw_dbg(hw, "I2C byte read error.\n");
 919
 920         } while (retry < max_retry);
 921
 922         return status;
 923 }
 924
 925 /**
 926  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
 927  *  @hw: pointer to hardware structure
 928  *  @byte_offset: byte offset to write
 929  *  @data: value to write
 930  *
 931  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
 932  *  a specified device address.
 933  **/
 934 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 935                                  u8 dev_addr, u8 data)
 936 {
 937         s32 status = 0;
 938         u32 max_retry = 1;
 939         u32 retry = 0;
 940
 941         do {
 942                 ixgbe_i2c_start(hw);
 943
 944                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 945                 if (status != 0)
 946                         goto fail;
 947
 948                 status = ixgbe_get_i2c_ack(hw);
 949                 if (status != 0)
 950                         goto fail;
 951
 952                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 953                 if (status != 0)
 954                         goto fail;
 955
 956                 status = ixgbe_get_i2c_ack(hw);
 957                 if (status != 0)
 958                         goto fail;
 959
 960                 status = ixgbe_clock_out_i2c_byte(hw, data);
 961                 if (status != 0)
 962                         goto fail;
 963
 964                 status = ixgbe_get_i2c_ack(hw);
 965                 if (status != 0)
 966                         goto fail;
 967
 968                 ixgbe_i2c_stop(hw);
 969                 break;
 970
 971 fail:
 972                 ixgbe_i2c_bus_clear(hw);
 973                 retry++;
 974                 if (retry < max_retry)
 975                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
 976                 else
 977                         hw_dbg(hw, "I2C byte write error.\n");
 978         } while (retry < max_retry);
 979
 980         return status;
 981 }
 982
 983 /**
 984  *  ixgbe_i2c_start - Sets I2C start condition
 985  *  @hw: pointer to hardware structure
 986  *
 987  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
 988  **/
 989 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
 990 {
 991         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 992
 993         /* Start condition must begin with data and clock high */
 994         ixgbe_set_i2c_data(hw, &i2cctl, 1);
 995         ixgbe_raise_i2c_clk(hw, &i2cctl);
 996
 997         /* Setup time for start condition (4.7us) */
 998         udelay(IXGBE_I2C_T_SU_STA);
 999
1000         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1001
1002         /* Hold time for start condition (4us) */
1003         udelay(IXGBE_I2C_T_HD_STA);
1004
1005         ixgbe_lower_i2c_clk(hw, &i2cctl);
1006
1007         /* Minimum low period of clock is 4.7 us */
1008         udelay(IXGBE_I2C_T_LOW);
1009
1010 }
1011
1012 /**
1013  *  ixgbe_i2c_stop - Sets I2C stop condition
1014  *  @hw: pointer to hardware structure
1015  *
1016  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1017  **/
1018 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1019 {
1020         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1021
1022         /* Stop condition must begin with data low and clock high */
1023         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1024         ixgbe_raise_i2c_clk(hw, &i2cctl);
1025
1026         /* Setup time for stop condition (4us) */
1027         udelay(IXGBE_I2C_T_SU_STO);
1028
1029         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1030
1031         /* bus free time between stop and start (4.7us)*/
1032         udelay(IXGBE_I2C_T_BUF);
1033 }
1034
1035 /**
1036  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1037  *  @hw: pointer to hardware structure
1038  *  @data: data byte to clock in
1039  *
1040  *  Clocks in one byte data via I2C data/clock
1041  **/
1042 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1043 {
1044         s32 status = 0;
1045         s32 i;
1046         bool bit = 0;
1047
1048         for (i = 7; i >= 0; i--) {
1049                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1050                 *data |= bit << i;
1051
1052                 if (status != 0)
1053                         break;
1054         }
1055
1056         return status;
1057 }
1058
1059 /**
1060  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1061  *  @hw: pointer to hardware structure
1062  *  @data: data byte clocked out
1063  *
1064  *  Clocks out one byte data via I2C data/clock
1065  **/
1066 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1067 {
1068         s32 status = 0;
1069         s32 i;
1070         u32 i2cctl;
1071         bool bit = 0;
1072
1073         for (i = 7; i >= 0; i--) {
1074                 bit = (data >> i) & 0x1;
1075                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1076
1077                 if (status != 0)
1078                         break;
1079         }
1080
1081         /* Release SDA line (set high) */
1082         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1083         i2cctl |= IXGBE_I2C_DATA_OUT;
1084         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1085
1086         return status;
1087 }
1088
1089 /**
1090  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1091  *  @hw: pointer to hardware structure
1092  *
1093  *  Clocks in/out one bit via I2C data/clock
1094  **/
1095 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1096 {
1097         s32 status;
1098         u32 i = 0;
1099         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1100         u32 timeout = 10;
1101         bool ack = 1;
1102
1103         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1104
1105         if (status != 0)
1106                 goto out;
1107
1108         /* Minimum high period of clock is 4us */
1109         udelay(IXGBE_I2C_T_HIGH);
1110
1111         /* Poll for ACK.  Note that ACK in I2C spec is
1112          * transition from 1 to 0 */
1113         for (i = 0; i < timeout; i++) {
1114                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1115                 ack = ixgbe_get_i2c_data(&i2cctl);
1116
1117                 udelay(1);
1118                 if (ack == 0)
1119                         break;
1120         }
1121
1122         if (ack == 1) {
1123                 hw_dbg(hw, "I2C ack was not received.\n");
1124                 status = IXGBE_ERR_I2C;
1125         }
1126
1127         ixgbe_lower_i2c_clk(hw, &i2cctl);
1128
1129         /* Minimum low period of clock is 4.7 us */
1130         udelay(IXGBE_I2C_T_LOW);
1131
1132 out:
1133         return status;
1134 }
1135
1136 /**
1137  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1138  *  @hw: pointer to hardware structure
1139  *  @data: read data value
1140  *
1141  *  Clocks in one bit via I2C data/clock
1142  **/
1143 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1144 {
1145         s32 status;
1146         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1147
1148         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1149
1150         /* Minimum high period of clock is 4us */
1151         udelay(IXGBE_I2C_T_HIGH);
1152
1153         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1154         *data = ixgbe_get_i2c_data(&i2cctl);
1155
1156         ixgbe_lower_i2c_clk(hw, &i2cctl);
1157
1158         /* Minimum low period of clock is 4.7 us */
1159         udelay(IXGBE_I2C_T_LOW);
1160
1161         return status;
1162 }
1163
1164 /**
1165  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1166  *  @hw: pointer to hardware structure
1167  *  @data: data value to write
1168  *
1169  *  Clocks out one bit via I2C data/clock
1170  **/
1171 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1172 {
1173         s32 status;
1174         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1175
1176         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1177         if (status == 0) {
1178                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1179
1180                 /* Minimum high period of clock is 4us */
1181                 udelay(IXGBE_I2C_T_HIGH);
1182
1183                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1184
1185                 /* Minimum low period of clock is 4.7 us.
1186                  * This also takes care of the data hold time.
1187                  */
1188                 udelay(IXGBE_I2C_T_LOW);
1189         } else {
1190                 status = IXGBE_ERR_I2C;
1191                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1192         }
1193
1194         return status;
1195 }
1196 /**
1197  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1198  *  @hw: pointer to hardware structure
1199  *  @i2cctl: Current value of I2CCTL register
1200  *
1201  *  Raises the I2C clock line '0'->'1'
1202  **/
1203 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1204 {
1205         s32 status = 0;
1206
1207         *i2cctl |= IXGBE_I2C_CLK_OUT;
1208
1209         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1210
1211         /* SCL rise time (1000ns) */
1212         udelay(IXGBE_I2C_T_RISE);
1213
1214         return status;
1215 }
1216
1217 /**
1218  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1219  *  @hw: pointer to hardware structure
1220  *  @i2cctl: Current value of I2CCTL register
1221  *
1222  *  Lowers the I2C clock line '1'->'0'
1223  **/
1224 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1225 {
1226
1227         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1228
1229         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1230
1231         /* SCL fall time (300ns) */
1232         udelay(IXGBE_I2C_T_FALL);
1233 }
1234
1235 /**
1236  *  ixgbe_set_i2c_data - Sets the I2C data bit
1237  *  @hw: pointer to hardware structure
1238  *  @i2cctl: Current value of I2CCTL register
1239  *  @data: I2C data value (0 or 1) to set
1240  *
1241  *  Sets the I2C data bit
1242  **/
1243 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1244 {
1245         s32 status = 0;
1246
1247         if (data)
1248                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1249         else
1250                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1251
1252         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1253
1254         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1255         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1256
1257         /* Verify data was set correctly */
1258         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1259         if (data != ixgbe_get_i2c_data(i2cctl)) {
1260                 status = IXGBE_ERR_I2C;
1261                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1262         }
1263
1264         return status;
1265 }
1266
1267 /**
1268  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1269  *  @hw: pointer to hardware structure
1270  *  @i2cctl: Current value of I2CCTL register
1271  *
1272  *  Returns the I2C data bit value
1273  **/
1274 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1275 {
1276         bool data;
1277
1278         if (*i2cctl & IXGBE_I2C_DATA_IN)
1279                 data = 1;
1280         else
1281                 data = 0;
1282
1283         return data;
1284 }
1285
1286 /**
1287  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1288  *  @hw: pointer to hardware structure
1289  *
1290  *  Clears the I2C bus by sending nine clock pulses.
1291  *  Used when data line is stuck low.
1292  **/
1293 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1294 {
1295         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1296         u32 i;
1297
1298         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1299
1300         for (i = 0; i < 9; i++) {
1301                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1302
1303                 /* Min high period of clock is 4us */
1304                 udelay(IXGBE_I2C_T_HIGH);
1305
1306                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1307
1308                 /* Min low period of clock is 4.7us*/
1309                 udelay(IXGBE_I2C_T_LOW);
1310         }
1311
1312         /* Put the i2c bus back to default state */
1313         ixgbe_i2c_stop(hw);
1314 }
1315
1316 /**
1317  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1318  *  @hw: pointer to hardware structure
1319  *
1320  *  Reads the VS1 register to determine if link is up and the current speed for
1321  *  the PHY.
1322  **/
1323 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1324                              bool *link_up)
1325 {
1326         s32 status = 0;
1327         u32 time_out;
1328         u32 max_time_out = 10;
1329         u16 phy_link = 0;
1330         u16 phy_speed = 0;
1331         u16 phy_data = 0;
1332
1333         /* Initialize speed and link to default case */
1334         *link_up = false;
1335         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1336
1337         /*
1338          * Check current speed and link status of the PHY register.
1339          * This is a vendor specific register and may have to
1340          * be changed for other copper PHYs.
1341          */
1342         for (time_out = 0; time_out < max_time_out; time_out++) {
1343                 udelay(10);
1344                 status = hw->phy.ops.read_reg(hw,
1345                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1346                                         MDIO_MMD_VEND1,
1347                                         &phy_data);
1348                 phy_link = phy_data &
1349                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1350                 phy_speed = phy_data &
1351                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1352                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1353                         *link_up = true;
1354                         if (phy_speed ==
1355                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1356                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1357                         break;
1358                 }
1359         }
1360
1361         return status;
1362 }
1363
1364 /**
1365  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1366  *  @hw: pointer to hardware structure
1367  *  @firmware_version: pointer to the PHY Firmware Version
1368  **/
1369 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1370                                        u16 *firmware_version)
1371 {
1372         s32 status = 0;
1373
1374         status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1375                                       firmware_version);
1376
1377         return status;
1378 }
1379
1380 /**
1381  *  ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1382  *  @hw: pointer to hardware structure
1383  *
1384  *  Checks if the LASI temp alarm status was triggered due to overtemp
1385  **/
1386 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1387 {
1388         s32 status = 0;
1389         u16 phy_data = 0;
1390
1391         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1392                 goto out;
1393
1394         /* Check that the LASI temp alarm status was triggered */
1395         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1396                              MDIO_MMD_PMAPMD, &phy_data);
1397
1398         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1399                 goto out;
1400
1401         status = IXGBE_ERR_OVERTEMP;
1402 out:
1403         return status;
1404 }