drivers/media/video/samsung/mfc5x/mfc_shm.h

   1 /*
   2  * linux/drivers/media/video/samsung/mfc5x/mfc_shm.h
   3  *
   4  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com/
   6  *
   7  * Shared memory interface for Samsung MFC (Multi Function Codec - FIMV) driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef __MFC_SHM_H
  15 #define __MFC_SHM_H __FILE__
  16
  17 enum MFC_SHM_OFS
  18 {
  19         EXTENEDED_DECODE_STATUS         = 0x00, /* D */
  20         SET_FRAME_TAG                   = 0x04, /* D */
  21         GET_FRAME_TAG_TOP               = 0x08, /* D */
  22         GET_FRAME_TAG_BOT               = 0x0C, /* D */
  23         PIC_TIME_TOP                    = 0x10, /* D */
  24         PIC_TIME_BOT                    = 0x14, /* D */
  25         START_BYTE_NUM                  = 0x18, /* D */
  26         CROP_INFO1                      = 0x20, /* D, H.264 */
  27         CROP_INFO2                      = 0x24, /* D, H.264 */
  28         EXT_ENC_CONTROL                 = 0x28, /* E */
  29         ENC_PARAM_CHANGE                = 0x2C, /* E */
  30         VOP_TIMING                      = 0x30, /* E, MPEG4 */
  31         HEC_PERIOD                      = 0x34, /* E, MPEG4 */
  32         METADATA_ENABLE                 = 0x38, /* C */
  33         METADATA_STATUS                 = 0x3C, /* C */
  34         METADATA_DISPLAY_INDEX          = 0x40, /* C */
  35         EXT_METADATA_START_ADDR         = 0x44, /* C */
  36         PUT_EXTRADATA                   = 0x48, /* C */
  37         EXTRADATA_ADDR                  = 0x4C, /* C */
  38         ALLOCATED_LUMA_DPB_SIZE         = 0x64, /* D */
  39         ALLOCATED_CHROMA_DPB_SIZE       = 0x68, /* D */
  40         ALLOCATED_MV_SIZE               = 0x6C, /* D */
  41         P_B_FRAME_QP                    = 0x70, /* E */
  42         ASPECT_RATIO_IDC                = 0x74, /* E, H.264, depend on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
  43         EXTENDED_SAR                    = 0x78, /* E, H.264, depned on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
  44         DISP_PIC_PROFILE                = 0x7C, /* D */
  45         FLUSH_CMD_TYPE                  = 0x80, /* C */
  46         FLUSH_CMD_INBUF1                = 0x84, /* C */
  47         FLUSH_CMD_INBUF2                = 0x88, /* C */
  48         FLUSH_CMD_OUTBUF                = 0x8C, /* E */
  49         NEW_RC_BIT_RATE                 = 0x90, /* E, format as RC_BIT_RATE(0xC5A8) depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
  50         NEW_RC_FRAME_RATE               = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0) depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
  51         NEW_I_PERIOD                    = 0x98, /* E, format as I_FRM_CTRL(0xC504) depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
  52         H264_I_PERIOD                   = 0x9C, /* E, H.264, open GOP */
  53         RC_CONTROL_CONFIG               = 0xA0, /* E */
  54         BATCH_INPUT_ADDR                = 0xA4, /* E */
  55         BATCH_OUTPUT_ADDR               = 0xA8, /* E */
  56         BATCH_OUTPUT_SIZE               = 0xAC, /* E */
  57         MIN_LUMA_DPB_SIZE               = 0xB0, /* D */
  58         DEVICE_FORMAT_ID                = 0xB4, /* C */
  59         H264_POC_TYPE                   = 0xB8, /* D */
  60         MIN_CHROMA_DPB_SIZE             = 0xBC, /* D */
  61         DISP_PIC_FRAME_TYPE             = 0xC0, /* D */
  62         FREE_LUMA_DPB                   = 0xC4, /* D, VC1 MPEG4 */
  63         ASPECT_RATIO_INFO               = 0xC8, /* D, MPEG4 */
  64         EXTENDED_PAR                    = 0xCC, /* D, MPEG4 */
  65         DBG_HISTORY_INPUT0              = 0xD0, /* C */
  66         DBG_HISTORY_INPUT1              = 0xD4, /* C */
  67         DBG_HISTORY_OUTPUT              = 0xD8, /* C */
  68         HIERARCHICAL_P_QP               = 0xE0, /* E, H.264 */
  69 };
  70
  71 int init_shm(struct mfc_inst_ctx *ctx);
  72 void write_shm(struct mfc_inst_ctx *ctx, unsigned int data, unsigned int offset);
  73 unsigned int read_shm(struct mfc_inst_ctx *ctx, unsigned int offset);
  74
  75 #endif /* __MFC_SHM_H */