1 /***************************************************************************
5 * SiI9244 - MHL Transmitter Driver
9 * Copyright (C) (2011, Silicon Image Inc)
13 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation version 2.
21 * This program is distributed ¡°as is¡± WITHOUT ANY WARRANTY of any
23 * kind, whether express or implied; without even the implied warranty
25 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
31 *****************************************************************************/
35 #include <linux/types.h>
36 #include <linux/i2c.h>
48 #define MHD_MAX_CHANNELS 1 // Number of MDHI channels
63 #define LOW_BYTE 0x00FF
65 #define LOW_NIBBLE 0x0F
66 #define HI_NIBBLE 0xF0
84 struct i2c_client* get_sii9234_client(u8 device_id);
85 u8 sii9234_i2c_read(struct i2c_client *client, u8 reg);
86 int sii9234_i2c_write(struct i2c_client *client, u8 reg, u8 data);
87 extern void sii9234_interrupt_event(void);
89 extern void sii9234_cfg_power(bool on);
90 extern void MHL_On(bool on);
91 extern byte ReadByteTPI (byte Offset);
92 Bool SiI9234_startTPI(void);
95 #define MHL_DEV_UNPOWERED 0x00
96 #define MHL_DEV_INACTIVE 0x01
97 #define MHL_DEV_QUIET 0x03
98 #define MHL_DEV_ACTIVE 0x04
100 // Version that this chip supports
101 #define MHL_VER_MAJOR (0x01 << 4) // bits 4..7
102 #define MHL_VER_MINOR 0x00 // bits 0..3
103 #define MHL_VERSION (MHL_VER_MAJOR | MHL_VER_MINOR)
106 #define MHL_DEV_CATEGORY_OFFSET 0x02
107 #define MHL_DEV_CATEGORY_POW_BIT (BIT_4)
109 #define MHL_DEV_CAT_SOURCE 0x00
110 #define MHL_DEV_CAT_SINGLE_INPUT_SINK 0x01
111 #define MHL_DEV_CAT_MULTIPLE_INPUT_SINK 0x02
112 #define MHL_DEV_CAT_UNPOWERED_DONGLE 0x03
113 #define MHL_DEV_CAT_SELF_POWERED_DONGLE 0x04
114 #define MHL_DEV_CAT_HDCP_REPEATER 0x05
115 #define MHL_DEV_CAT_NON_DISPLAY_SINK 0x06
116 #define MHL_DEV_CAT_POWER_NEUTRAL_SINK 0x07
117 #define MHL_DEV_CAT_OTHER 0x80
120 #define MHL_DEV_VID_LINK_SUPPRGB444 0x01
121 #define MHL_DEV_VID_LINK_SUPPYCBCR444 0x02
122 #define MHL_DEV_VID_LINK_SUPPYCBCR422 0x04
123 #define MHL_DEV_VID_LINK_PPIXEL 0x08
124 #define MHL_DEV_VID_LINK_SUPP_ISLANDS 0x10
126 //Audio Link Mode Support
127 #define MHL_DEV_AUD_LINK_2CH 0x01
128 #define MHL_DEV_AUD_LINK_8CH 0x02
131 //Feature Flag in the devcap
132 #define MHL_DEV_FEATURE_FLAG_OFFSET 0x0A
133 #define MHL_FEATURE_RCP_SUPPORT BIT_0 // Dongles have freedom to not support RCP
134 #define MHL_FEATURE_RAP_SUPPORT BIT_1 // Dongles have freedom to not support RAP
135 #define MHL_FEATURE_SP_SUPPORT BIT_2 // Dongles have freedom to not support SCRATCHPAD
138 #define MHL_POWER_SUPPLY_CAPACITY 16 // 160 mA current
139 #define MHL_POWER_SUPPLY_PROVIDED 16 // 160mA 0r 0 for Wolverine.
140 #define MHL_HDCP_STATUS 0 // Bits set dynamically
144 #define MHL_VT_GRAPHICS 0x00
145 #define MHL_VT_PHOTO 0x02
146 #define MHL_VT_CINEMA 0x04
147 #define MHL_VT_GAMES 0x08
148 #define MHL_SUPP_VT 0x80
151 #define MHL_DEV_LD_DISPLAY (0x01 << 0)
152 #define MHL_DEV_LD_VIDEO (0x01 << 1)
153 #define MHL_DEV_LD_AUDIO (0x01 << 2)
154 #define MHL_DEV_LD_MEDIA (0x01 << 3)
155 #define MHL_DEV_LD_TUNER (0x01 << 4)
156 #define MHL_DEV_LD_RECORD (0x01 << 5)
157 #define MHL_DEV_LD_SPEAKER (0x01 << 6)
158 #define MHL_DEV_LD_GUI (0x01 << 7)
161 #define MHL_BANDWIDTH_LIMIT 22 // 225 MHz
164 #define MHL_STATUS_DCAP_RDY BIT_0
165 #define MHL_INT_DCAP_CHG BIT_0
167 // On INTR_1 the EDID_CHG is located at BIT 0
168 #define MHL_INT_EDID_CHG BIT_1
170 #define MHL_INT_AND_STATUS_SIZE 0x303 // This contains one nibble each - max offset
171 #define MHL_SCRATCHPAD_SIZE 16
172 #define MHL_MAX_BUFFER_SIZE MHL_SCRATCHPAD_SIZE // manually define highest number
178 MHL_MSC_MSG_RCP = 0x10, // RCP sub-command
179 MHL_MSC_MSG_RCPK = 0x11, // RCP Acknowledge sub-command
180 MHL_MSC_MSG_RCPE = 0x12, // RCP Error sub-command
181 MHL_MSC_MSG_RAP = 0x20, // Mode Change Warning sub-command
182 MHL_MSC_MSG_RAPK = 0x21 // MCW Acknowledge sub-command
186 // MHL spec related defines
190 MHL_ACK = 0x33, // Command or Data byte acknowledge
191 MHL_NACK = 0x34, // Command or Data byte not acknowledge
192 MHL_ABORT = 0x35, // Transaction abort
193 MHL_WRITE_STAT = 0x60 | 0x80, // Write one status register strip top bit
194 MHL_SET_INT = 0x60, // Write one interrupt register
195 MHL_READ_DEVCAP = 0x61, // Read one register
196 MHL_GET_STATE = 0x62, // Read CBUS revision level from follower
197 MHL_GET_VENDOR_ID = 0x63, // Read vendor ID value from follower.
198 MHL_SET_HPD = 0x64, // Set Hot Plug Detect in follower
199 MHL_CLR_HPD = 0x65, // Clear Hot Plug Detect in follower
200 MHL_SET_CAP_ID = 0x66, // Set Capture ID for downstream device.
201 MHL_GET_CAP_ID = 0x67, // Get Capture ID from downstream device.
202 MHL_MSC_MSG = 0x68, // VS command to send RCP sub-commands
203 MHL_GET_SC1_ERRORCODE = 0x69, // Get Vendor-Specific command error code.
204 MHL_GET_DDC_ERRORCODE = 0x6A, // Get DDC channel command error code.
205 MHL_GET_MSC_ERRORCODE = 0x6B, // Get MSC command error code.
206 MHL_WRITE_BURST = 0x6C, // Write 1-16 bytes to responder
\92s scratchpad.
207 MHL_GET_SC3_ERRORCODE = 0x6D // Get channel 3 command error code.
210 #define MHL_RAP_CONTENT_ON 0x10 // Turn content streaming ON.
211 #define MHL_RAP_CONTENT_OFF 0x11 // Turn content streaming OFF.
213 ///////////////////////////////////////////////////////////////////////////////
215 // MHL Timings applicable to this driver.
218 #define T_SRC_VBUS_CBUS_TO_STABLE (200) // 100 - 1000 milliseconds. Per MHL 1.0 Specs
219 #define T_SRC_WAKE_PULSE_WIDTH_1 (20) // 20 milliseconds. Per MHL 1.0 Specs
220 #define T_SRC_WAKE_PULSE_WIDTH_2 (60) // 60 milliseconds. Per MHL 1.0 Specs
222 #define T_SRC_WAKE_TO_DISCOVER (500) // 100 - 1000 milliseconds. Per MHL 1.0 Specs
224 #define T_SRC_VBUS_CBUS_T0_STABLE (500)
226 // Allow RSEN to stay low this much before reacting.
227 // Per specs between 100 to 200 ms
228 #define T_SRC_RSEN_DEGLITCH (150)
230 // Wait this much after connection before reacting to RSEN (300-500ms)
231 // Per specs between 300 to 500 ms
232 #define T_SRC_RXSENSE_CHK (400)