2 * Register definition file for Samsung Camera Interface (FIMC) driver
4 * Copyright (c) 2010 Samsung Electronics
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 /* Input source format */
15 #define S5P_CISRCFMT 0x00
16 #define S5P_CISRCFMT_ITU601_8BIT (1 << 31)
17 #define S5P_CISRCFMT_ITU601_16BIT (1 << 29)
18 #define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14)
19 #define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14)
20 #define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14)
21 #define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14)
22 #define S5P_CISRCFMT_HSIZE(x) ((x) << 16)
23 #define S5P_CISRCFMT_VSIZE(x) ((x) << 0)
26 #define S5P_CIWDOFST 0x04
27 #define S5P_CIWDOFST_OFF_EN (1 << 31)
28 #define S5P_CIWDOFST_CLROVFIY (1 << 30)
29 #define S5P_CIWDOFST_CLROVRLB (1 << 29)
30 #define S5P_CIWDOFST_HOROFF_MASK (0x7ff << 16)
31 #define S5P_CIWDOFST_CLROVFICB (1 << 15)
32 #define S5P_CIWDOFST_CLROVFICR (1 << 14)
33 #define S5P_CIWDOFST_HOROFF(x) ((x) << 16)
34 #define S5P_CIWDOFST_VEROFF(x) ((x) << 0)
35 #define S5P_CIWDOFST_VEROFF_MASK (0xfff << 0)
38 #define S5P_CIGCTRL 0x08
39 #define S5P_CIGCTRL_SWRST (1 << 31)
40 #define S5P_CIGCTRL_CAMRST_A (1 << 30)
41 #define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29)
42 #define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27)
43 #define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
44 #define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
45 #define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27)
46 #define S5P_CIGCTRL_TESTPAT_MASK (3 << 27)
47 #define S5P_CIGCTRL_TESTPAT_SHIFT (27)
48 #define S5P_CIGCTRL_INVPOLPCLK (1 << 26)
49 #define S5P_CIGCTRL_INVPOLVSYNC (1 << 25)
50 #define S5P_CIGCTRL_INVPOLHREF (1 << 24)
51 #define S5P_CIGCTRL_IRQ_OVFEN (1 << 22)
52 #define S5P_CIGCTRL_HREF_MASK (1 << 21)
53 #define S5P_CIGCTRL_IRQ_LEVEL (1 << 20)
54 #define S5P_CIGCTRL_IRQ_CLR (1 << 19)
55 #define S5P_CIGCTRL_IRQ_ENABLE (1 << 16)
56 #define S5P_CIGCTRL_SHDW_DISABLE (1 << 12)
57 #define S5P_CIGCTRL_SELWRITEBACK_A (1 << 10)
58 #define S5P_CIGCTRL_CAM_JPEG (1 << 8)
59 #define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7)
60 #define S5P_CIGCTRL_CAMIF_SELWB (1 << 6)
61 /* 0 - ITU601; 1 - ITU709 */
62 #define S5P_CIGCTRL_CSC_ITU601_709 (1 << 5)
63 #define S5P_CIGCTRL_INVPOLHSYNC (1 << 4)
64 #define S5P_CIGCTRL_SELCAM_MIPI (1 << 3)
65 #define S5P_CIGCTRL_INTERLACE (1 << 0)
68 #define S5P_CIWDOFST2 0x14
69 #define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16)
70 #define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0)
71 #define S5P_CIWDOFST2_HOROFF(x) ((x) << 16)
72 #define S5P_CIWDOFST2_VEROFF(x) ((x) << 0)
74 /* Output DMA Y/Cb/Cr plane start addresses */
75 #define S5P_CIOYSA(n) (0x18 + (n) * 4)
76 #define S5P_CIOCBSA(n) (0x28 + (n) * 4)
77 #define S5P_CIOCRSA(n) (0x38 + (n) * 4)
79 /* Target image format */
80 #define S5P_CITRGFMT 0x48
81 #define S5P_CITRGFMT_INROT90 (1 << 31)
82 #define S5P_CITRGFMT_YCBCR420 (0 << 29)
83 #define S5P_CITRGFMT_YCBCR422 (1 << 29)
84 #define S5P_CITRGFMT_YCBCR422_1P (2 << 29)
85 #define S5P_CITRGFMT_RGB (3 << 29)
86 #define S5P_CITRGFMT_FMT_MASK (3 << 29)
87 #define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16)
88 #define S5P_CITRGFMT_FLIP_SHIFT (14)
89 #define S5P_CITRGFMT_FLIP_NORMAL (0 << 14)
90 #define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14)
91 #define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
92 #define S5P_CITRGFMT_FLIP_180 (3 << 14)
93 #define S5P_CITRGFMT_FLIP_MASK (3 << 14)
94 #define S5P_CITRGFMT_OUTROT90 (1 << 13)
95 #define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0)
96 #define S5P_CITRGFMT_HSIZE(x) ((x) << 16)
97 #define S5P_CITRGFMT_VSIZE(x) ((x) << 0)
99 /* Output DMA control */
100 #define S5P_CIOCTRL 0x4c
101 #define S5P_CIOCTRL_ORDER422_MASK (3 << 0)
102 #define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0)
103 #define S5P_CIOCTRL_ORDER422_CBYCRY (1 << 0)
104 #define S5P_CIOCTRL_ORDER422_YCRYCB (2 << 0)
105 #define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0)
106 #define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
107 #define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3)
108 #define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3)
109 #define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
110 #define S5P_CIOCTRL_ALPHA_OUT_MASK (0xff << 4)
111 #define S5P_CIOCTRL_RGB16FMT_MASK (3 << 16)
112 #define S5P_CIOCTRL_RGB565 (0 << 16)
113 #define S5P_CIOCTRL_ARGB1555 (1 << 16)
114 #define S5P_CIOCTRL_ARGB4444 (2 << 16)
115 #define S5P_CIOCTRL_ORDER2P_SHIFT (24)
116 #define S5P_CIOCTRL_ORDER2P_MASK (3 << 24)
117 #define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
118 #define S5P_CIOCTRL_ORDER422_2P_LSB_CBCR (1 << 24)
120 /* Pre-scaler control 1 */
121 #define S5P_CISCPRERATIO 0x50
122 #define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
123 #define S5P_CISCPRERATIO_HOR(x) ((x) << 16)
124 #define S5P_CISCPRERATIO_VER(x) ((x) << 0)
126 #define S5P_CISCPREDST 0x54
127 #define S5P_CISCPREDST_WIDTH(x) ((x) << 16)
128 #define S5P_CISCPREDST_HEIGHT(x) ((x) << 0)
130 /* Main scaler control */
131 #define S5P_CISCCTRL 0x58
132 #define S5P_CISCCTRL_SCALERBYPASS (1 << 31)
133 #define S5P_CISCCTRL_SCALEUP_H (1 << 30)
134 #define S5P_CISCCTRL_SCALEUP_V (1 << 29)
135 #define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28)
136 #define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27)
137 #define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
138 #define S5P_CISCCTRL_INTERLACE (1 << 25)
139 #define S5P_CISCCTRL_SCALERSTART (1 << 15)
140 #define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
141 #define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
142 #define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
143 #define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13)
144 #define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
145 #define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
146 #define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
147 #define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
148 #define S5P_CISCCTRL_RGB_EXT (1 << 10)
149 #define S5P_CISCCTRL_ONE2ONE (1 << 9)
150 #define S5P_CISCCTRL_MHRATIO(x) ((x) << 16)
151 #define S5P_CISCCTRL_MVRATIO(x) ((x) << 0)
152 #define S5P_CISCCTRL_MHRATIO_MASK (0x1ff << 16)
153 #define S5P_CISCCTRL_MVRATIO_MASK (0x1ff << 0)
154 #define S5P_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16)
155 #define S5P_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0)
158 #define S5P_CITAREA 0x5c
159 #define S5P_CITAREA_MASK 0x0fffffff
162 #define S5P_CISTATUS 0x64
163 #define S5P_CISTATUS_OVFIY (1 << 31)
164 #define S5P_CISTATUS_OVFICB (1 << 30)
165 #define S5P_CISTATUS_OVFICR (1 << 29)
166 #define S5P_CISTATUS_VSYNC (1 << 28)
167 #define S5P_CISTATUS_FRAMECNT_MASK (3 << 26)
168 #define S5P_CISTATUS_FRAMECNT_SHIFT 26
169 #define S5P_CISTATUS_WINOFF_EN (1 << 25)
170 #define S5P_CISTATUS_IMGCPT_EN (1 << 22)
171 #define S5P_CISTATUS_IMGCPT_SCEN (1 << 21)
172 #define S5P_CISTATUS_VSYNC_A (1 << 20)
173 #define S5P_CISTATUS_VSYNC_B (1 << 19)
174 #define S5P_CISTATUS_OVRLB (1 << 18)
175 #define S5P_CISTATUS_FRAME_END (1 << 17)
176 #define S5P_CISTATUS_LASTCAPT_END (1 << 16)
177 #define S5P_CISTATUS_VVALID_A (1 << 15)
178 #define S5P_CISTATUS_VVALID_B (1 << 14)
180 /* Indexes to the last and the currently processed buffer. */
181 #define S5P_CISTATUS2 0x68
183 /* Image capture control */
184 #define S5P_CIIMGCPT 0xc0
185 #define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
186 #define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30)
187 #define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
188 #define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
190 /* Frame capture sequence */
191 #define S5P_CICPTSEQ 0xc4
194 #define S5P_CIIMGEFF 0xd0
195 #define S5P_CIIMGEFF_IE_DISABLE (0 << 30)
196 #define S5P_CIIMGEFF_IE_ENABLE (1 << 30)
197 #define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29)
198 #define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29)
199 #define S5P_CIIMGEFF_FIN_BYPASS (0 << 26)
200 #define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26)
201 #define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26)
202 #define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
203 #define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26)
204 #define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
205 #define S5P_CIIMGEFF_FIN_MASK (7 << 26)
206 #define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
207 #define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13)
208 #define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0)
210 /* Input DMA Y/Cb/Cr plane start address 0/1 */
211 #define S5P_CIIYSA(n) (0xd4 + (n) * 0x70)
212 #define S5P_CIICBSA(n) (0xd8 + (n) * 0x70)
213 #define S5P_CIICRSA(n) (0xdc + (n) * 0x70)
215 /* Real input DMA image size */
216 #define S5P_CIREAL_ISIZE 0xf8
217 #define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
218 #define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
219 #define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
220 #define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
223 /* Input DMA control */
224 #define S5P_MSCTRL 0xfc
225 #define S5P_MSCTRL_IN_BURST_COUNT_MASK (0xF << 24)
226 #define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
227 #define S5P_MSCTRL_2P_IN_YCRCB (1 << 16)
228 #define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16
229 #define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15)
230 #define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15)
231 #define S5P_MSCTRL_C_INT_IN_MASK (1 << 15)
232 #define S5P_MSCTRL_FLIP_SHIFT 13
233 #define S5P_MSCTRL_FLIP_MASK (3 << 13)
234 #define S5P_MSCTRL_FLIP_NORMAL (0 << 13)
235 #define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
236 #define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
237 #define S5P_MSCTRL_FLIP_180 (3 << 13)
238 #define S5P_MSCTRL_FIFO_CTRL_FULL (1 << 12)
239 #define S5P_MSCTRL_ORDER422_SHIFT 4
240 #define S5P_MSCTRL_ORDER422_YCBYCR (0 << 4)
241 #define S5P_MSCTRL_ORDER422_CBYCRY (1 << 4)
242 #define S5P_MSCTRL_ORDER422_YCRYCB (2 << 4)
243 #define S5P_MSCTRL_ORDER422_CRYCBY (3 << 4)
244 #define S5P_MSCTRL_ORDER422_MASK (3 << 4)
245 #define S5P_MSCTRL_INPUT_EXTCAM (0 << 3)
246 #define S5P_MSCTRL_INPUT_MEMORY (1 << 3)
247 #define S5P_MSCTRL_INPUT_MASK (1 << 3)
248 #define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
249 #define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
250 #define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
251 #define S5P_MSCTRL_INFORMAT_RGB (3 << 1)
252 #define S5P_MSCTRL_INFORMAT_MASK (3 << 1)
253 #define S5P_MSCTRL_ENVID (1 << 0)
254 #define S5P_MSCTRL_IN_BURST_COUNT(x) ((x) << 24)
256 /* Output DMA Y/Cb/Cr offset */
257 #define S5P_CIOYOFF 0x168
258 #define S5P_CIOCBOFF 0x16c
259 #define S5P_CIOCROFF 0x170
261 /* Input DMA Y/Cb/Cr offset */
262 #define S5P_CIIYOFF 0x174
263 #define S5P_CIICBOFF 0x178
264 #define S5P_CIICROFF 0x17c
266 #define S5P_CIO_OFFS_VER(x) ((x) << 16)
267 #define S5P_CIO_OFFS_HOR(x) ((x) << 0)
269 /* Input DMA original image size */
270 #define S5P_ORGISIZE 0x180
272 /* Output DMA original image size */
273 #define S5P_ORGOSIZE 0x184
275 #define S5P_ORIG_SIZE_VER(x) ((x) << 16)
276 #define S5P_ORIG_SIZE_HOR(x) ((x) << 0)
278 /* Real output DMA image size (extension register) */
279 #define S5P_CIEXTEN 0x188
280 #define S5P_CIEXTEN_TRGHSIZE_EXT(x) ((((x) >> 13) & 0x1) << 26)
281 #define S5P_CIEXTEN_TRGVSIZE_EXT(x) ((((x) >> 13) & 0x1) << 24)
282 #define S5P_CIEXTEN_TRGHSIZE_EXT_MASK (1 << 26)
283 #define S5P_CIEXTEN_TRGVSIZE_EXT_MASK (1 << 24)
284 #define S5P_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10)
285 #define S5P_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f)
286 #define S5P_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10)
287 #define S5P_CIEXTEN_MVRATIO_EXT_MASK 0x3f
289 #define S5P_CIDMAPARAM 0x18c
290 #define S5P_CIDMAPARAM_R_LINEAR (0 << 29)
291 #define S5P_CIDMAPARAM_R_64X32 (3 << 29)
292 #define S5P_CIDMAPARAM_W_LINEAR (0 << 13)
293 #define S5P_CIDMAPARAM_W_64X32 (3 << 13)
294 #define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
296 /* MIPI CSI image format */
297 #define S5P_CSIIMGFMT 0x194
298 #define S5P_CSIIMGFMT_YCBCR422_8BIT 0x1e
299 #define S5P_CSIIMGFMT_RAW8 0x2a
300 #define S5P_CSIIMGFMT_RAW10 0x2b
301 #define S5P_CSIIMGFMT_RAW12 0x2c
302 /* User defined formats. x = 0...16. */
303 #define S5P_CSIIMGFMT_USER(x) (0x30 + x - 1)
304 #define S5P_CSIIMGFMT_USER1 0x30
305 #define S5P_CSIIMGFMT_USER2 0x31
306 #define S5P_CSIIMGFMT_USER3 0x32
307 #define S5P_CSIIMGFMT_USER4 0x33
309 /* Output frame buffer sequence mask */
310 #define S5P_CIFCNTSEQ 0x1FC
312 /* SYSREG for writeback */
313 #define SYSREG_CAMERA_BLK (S3C_VA_SYS + 0x0218)
314 #define FIMD0_WB_DEST_FIMC0 (0x0 << 14)
315 #define FIMD0_WB_DEST_FIMC1 (0x1 << 14)
316 #define FIMD0_WB_DEST_FIMC2 (0x2 << 14)
317 #define FIMD0_WB_DEST_FIMC3 (0x3 << 14)
318 #define FIMD1_WB_DEST_FIMC0 (0x0 << 10)
319 #define FIMD1_WB_DEST_FIMC1 (0x1 << 10)
320 #define FIMD1_WB_DEST_FIMC2 (0x2 << 10)
321 #define FIMD1_WB_DEST_FIMC3 (0x3 << 10)
323 #endif /* REGS_FIMC_H_ */