2 * Copyright (c) 2010 Samsung Electronics
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
16 #include <linux/sched.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
20 #include <media/videobuf2-core.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-mem2mem.h>
23 #include <media/v4l2-mediabus.h>
24 #include <media/s5p_fimc.h>
25 #include "regs-fimc.h"
27 #ifdef CONFIG_VIDEOBUF2_SDVMM
28 #include <media/videobuf2-sdvmm.h>
29 #include <plat/s5p-vcm.h>
31 #include <media/videobuf2-cma.h>
34 #ifdef CONFIG_PM_RUNTIME
35 #include <linux/pm_runtime.h>
37 #define pm_runtime_enable(x) (void)NULL
38 #define pm_runtime_get_sync(x) (void)NULL
39 #define pm_runtime_put_sync(x) (void)NULL
40 #define pm_runtime_forbid(x) (void)NULL
41 #define pm_runtime_allow(x) (void)NULL
42 #define __pm_runtime_disable(x, y) (void)NULL
45 #define err(fmt, args...) \
46 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
49 #define dbg(fmt, args...) \
50 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
52 #define dbg(fmt, args...)
55 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
56 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
57 #define MAX_FIMC_CLOCKS 3
58 #define MODULE_NAME "s5p-fimc"
59 #define FIMC_MAX_DEVS 4
60 #define FIMC_MAX_OUT_BUFS 4
61 #define SCALER_MAX_HRATIO 64
62 #define SCALER_MAX_VRATIO 64
63 #define DMA_MIN_SIZE 8
65 #define FIMC_SRC_CLOCK "mout_mpll"
67 #define CAM_SRC_CLOCK "xusbxti" /* for SMDK series */
69 #define CAM_SRC_CLOCK "sclk_vpll" /* for Universal */
70 #define FIMC_CMA_NAME "fimc"
71 #define FIMC_CMA_NAME_SIZE 6
72 #define WORKQUEUE_NAME_SIZE 32
75 #define FIMD_MODULE_NAME "s3cfb"
77 #define FIMD_MODULE_NAME "s3c-fb"
80 /* indices to the clocks array */
93 /* for capture node */
103 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
104 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
106 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
107 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
108 #define fimc_capture_opened(dev) (dev->vid_cap.refcnt > 0) ? 1 : 0
109 #define fimc_capture_camera(dev) (dev->vid_cap.sd == NULL) ? 0 : 1
110 #define fimc_capture_writeback(dev) (dev->vid_cap.fb_sd != NULL &&\
111 test_bit(ST_CAPT_PEND, &(dev)->state)) ? 1 : 0
113 #define fimc_capture_active(dev) \
114 (test_bit(ST_CAPT_RUN, &(dev)->state) || \
115 test_bit(ST_CAPT_PEND, &(dev)->state))
117 #define fimc_capture_streaming(dev) \
118 test_bit(ST_CAPT_STREAM, &(dev)->state)
127 enum fimc_color_fmt {
128 S5P_FIMC_RGB565 = 0x10,
133 S5P_FIMC_RGB30_LOCAL,
134 S5P_FIMC_YCBCR420 = 0x20,
141 S5P_FIMC_YCBCR444_LOCAL,
142 S5P_FIMC_JPEG = 0x40,
145 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
146 #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
148 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
149 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
151 /* The embedded image effect selection */
152 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
153 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
154 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
155 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
156 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
157 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
159 /* The hardware context state. */
160 #define FIMC_PARAMS (1 << 0)
161 #define FIMC_SRC_ADDR (1 << 1)
162 #define FIMC_DST_ADDR (1 << 2)
163 #define FIMC_SRC_FMT (1 << 3)
164 #define FIMC_DST_FMT (1 << 4)
165 #define FIMC_CTX_M2M (1 << 5)
166 #define FIMC_CTX_CAP (1 << 6)
168 /* Image conversion flags */
169 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
170 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
171 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
172 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
173 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
174 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
176 * YCbCr data dynamic range for RGB-YUV color conversion.
177 * Y/Cb/Cr: (0 ~ 255) */
178 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
179 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
180 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
183 #define FLIP_X_AXIS 1
184 #define FLIP_Y_AXIS 2
185 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
188 * struct fimc_fmt - the driver's internal color format data
189 * @mbus_code: Media Bus pixel code, -1 if not applicable
190 * @name: format description
191 * @fourcc: the fourcc code for this format, 0 if not applicable
192 * @color: the corresponding fimc_color_fmt
193 * @depth: per plane driver's private 'number of bits per pixel'
194 * @memplanes: number of physically non-contiguous data planes
195 * @colplanes: number of physically contiguous data planes
198 enum v4l2_mbus_pixelcode mbus_code;
204 u8 depth[VIDEO_MAX_PLANES];
206 #define FMT_FLAGS_CAM (1 << 0)
207 #define FMT_FLAGS_M2M (1 << 1)
211 * struct fimc_dma_offset - pixel offset information for DMA
212 * @y_h: y value horizontal offset
213 * @y_v: y value vertical offset
214 * @cb_h: cb value horizontal offset
215 * @cb_v: cb value vertical offset
216 * @cr_h: cr value horizontal offset
217 * @cr_v: cr value vertical offset
219 struct fimc_dma_offset {
229 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
231 * @pat_cb: cr value when type is "arbitrary"
232 * @pat_cr: cr value when type is "arbitrary"
241 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
243 * @scaleup_h: flag indicating scaling up horizontally
244 * @scaleup_v: flag indicating scaling up vertically
245 * @copy_mode: flag indicating transparent DMA transfer (no scaling
246 * and color format conversion)
247 * @enabled: flag indicating if the scaler is used
248 * @hfactor: horizontal shift factor
249 * @vfactor: vertical shift factor
250 * @pre_hratio: horizontal ratio of the prescaler
251 * @pre_vratio: vertical ratio of the prescaler
252 * @pre_dst_width: the prescaler's destination width
253 * @pre_dst_height: the prescaler's destination height
254 * @main_hratio: the main scaler's horizontal ratio
255 * @main_vratio: the main scaler's vertical ratio
256 * @real_width: source pixel (width - offset)
257 * @real_height: source pixel (height - offset)
260 unsigned int scaleup_h:1;
261 unsigned int scaleup_v:1;
262 unsigned int copy_mode:1;
263 unsigned int enabled:1;
277 * struct fimc_addr - the FIMC physical address set for DMA
279 * @y: luminance plane physical address
280 * @cb: Cb plane physical address
281 * @cr: Cr plane physical address
290 * struct fimc_vid_buffer - the driver's video buffer
291 * @vb: v4l videobuf buffer
292 * @paddr: precalculated physical address set
293 * @index: buffer index for the output DMA engine
295 struct fimc_vid_buffer {
296 struct vb2_buffer vb;
297 struct list_head list;
298 struct fimc_addr paddr;
303 * struct fimc_frame - source/target frame properties
304 * @f_width: image full width (virtual screen size)
305 * @f_height: image full height (virtual screen size)
306 * @o_width: original image width as set by S_FMT
307 * @o_height: original image height as set by S_FMT
308 * @offs_h: image horizontal pixel offset
309 * @offs_v: image vertical pixel offset
310 * @width: image pixel width
311 * @height: image pixel weight
312 * @paddr: image frame buffer physical addresses
313 * @buf_cnt: number of buffers depending on a color format
314 * @payload: image size in bytes (w x h x bpp)
315 * @color: color format
316 * @dma_offset: DMA offset in bytes
328 unsigned long payload[VIDEO_MAX_PLANES];
329 struct fimc_addr paddr;
330 struct fimc_dma_offset dma_offset;
331 struct fimc_fmt *fmt;
336 * struct fimc_m2m_device - v4l2 memory-to-memory device data
337 * @vfd: the video device node for v4l2 m2m mode
338 * @v4l2_dev: v4l2 device for m2m mode
339 * @m2m_dev: v4l2 memory-to-memory device data
340 * @ctx: hardware context data
341 * @refcnt: the reference counter
343 struct fimc_m2m_device {
344 struct video_device *vfd;
345 struct v4l2_device v4l2_dev;
346 struct v4l2_m2m_dev *m2m_dev;
347 struct fimc_ctx *ctx;
352 * struct fimc_vid_cap - camera capture device information
353 * @ctx: hardware context data
354 * @vfd: video device node for camera capture mode
355 * @v4l2_dev: v4l2_device struct to manage subdevs
356 * @sd: pointer to camera sensor subdevice currently in use
357 * @fmt: Media Bus format configured at selected image sensor
358 * @pending_buf_q: the pending buffer queue head
359 * @active_buf_q: the queue head of buffers scheduled in hardware
360 * @vbq: the capture am video buffer queue
361 * @active_buf_cnt: number of video buffers scheduled in hardware
362 * @buf_index: index for managing the output DMA buffers
363 * @frame_count: the frame counter for statistics
364 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
365 * @input_index: input (camera sensor) index
366 * @refcnt: driver's private reference counter
368 struct fimc_vid_cap {
369 struct fimc_ctx *ctx;
370 struct vb2_alloc_ctx *alloc_ctx;
371 struct video_device *vfd;
372 struct v4l2_device v4l2_dev;
373 struct v4l2_subdev *sd;
374 struct v4l2_subdev *fb_sd;
375 struct v4l2_subdev *mipi_sd;
376 struct v4l2_mbus_framefmt fmt;
377 struct list_head pending_buf_q;
378 struct list_head active_buf_q;
379 struct vb2_queue vbq;
382 unsigned int frame_count;
383 unsigned int reqbufs_count;
389 * struct fimc_pix_limit - image pixel size limits in various IP configurations
391 * @scaler_en_w: max input pixel width when the scaler is enabled
392 * @scaler_dis_w: max input pixel width when the scaler is disabled
393 * @in_rot_en_h: max input width with the input rotator is on
394 * @in_rot_dis_w: max input width with the input rotator is off
395 * @out_rot_en_w: max output width with the output rotator on
396 * @out_rot_dis_w: max output width with the output rotator off
398 struct fimc_pix_limit {
408 * struct samsung_fimc_variant - camera interface variant information
410 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
411 * @has_inp_rot: set if has input rotator
412 * @has_out_rot: set if has output rotator
413 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
414 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
415 * are present in this IP revision
416 * @pix_limit: pixel size constraints for the scaler
417 * @min_inp_pixsize: minimum input pixel size
418 * @min_out_pixsize: minimum output pixel size
419 * @hor_offs_align: horizontal pixel offset aligment
420 * @out_buf_count: the number of buffers in output DMA sequence
422 struct samsung_fimc_variant {
423 unsigned int pix_hoff:1;
424 unsigned int has_inp_rot:1;
425 unsigned int has_out_rot:1;
426 unsigned int has_cistatus2:1;
427 unsigned int has_mainscaler_ext:1;
428 struct fimc_pix_limit *pix_limit;
436 * struct samsung_fimc_driverdata - per device type driver data for init time.
438 * @variant: the variant information for this driver.
439 * @dev_cnt: number of fimc sub-devices available in SoC
440 * @lclk_frequency: fimc bus clock frequency
442 struct samsung_fimc_driverdata {
443 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
444 unsigned long lclk_frequency;
451 * struct fimc_dev - abstraction for FIMC entity
453 * @slock: the spinlock protecting this data structure
454 * @lock: the mutex protecting this data structure
455 * @pdev: pointer to the FIMC platform device
456 * @pdata: pointer to the device platform data
457 * @id: FIMC device index (0..FIMC_MAX_DEVS)
458 * @num_clocks: the number of clocks managed by this device instance
459 * @clock[]: the clocks required for FIMC operation
460 * @regs: the mapped hardware registers
461 * @regs_res: the resource claimed for IO registers
462 * @irq: interrupt number of the FIMC subdevice
464 * @m2m: memory-to-memory V4L2 device information
465 * @vid_cap: camera capture device information
466 * @state: flags used to synchronize m2m and capture mode operation
471 struct platform_device *pdev;
472 struct s5p_platform_fimc *pdata;
473 struct samsung_fimc_variant *variant;
476 struct clk *clock[MAX_FIMC_CLOCKS];
479 struct resource *regs_res;
481 wait_queue_head_t irq_queue;
482 struct work_struct work_struct;
483 struct workqueue_struct *irq_workqueue;
484 struct fimc_m2m_device m2m;
485 struct fimc_vid_cap vid_cap;
487 struct vb2_alloc_ctx *alloc_ctx;
488 struct fimc_addr paddr[FIMC_MAX_OUT_BUFS];
489 #ifdef CONFIG_VIDEOBUF2_SDVMM
490 enum vcm_dev_id vcm_id;
495 * fimc_ctx - the device context data
497 * @lock: mutex protecting this data structure
498 * @s_frame: source frame properties
499 * @d_frame: destination frame properties
500 * @out_order_1p: output 1-plane YCBCR order
501 * @out_order_2p: output 2-plane YCBCR order
502 * @in_order_1p input 1-plane YCBCR order
503 * @in_order_2p: input 2-plane YCBCR order
504 * @in_path: input mode (DMA or camera)
505 * @out_path: output mode (DMA or FIFO)
506 * @scaler: image scaler properties
507 * @effect: image effect
508 * @rotation: image clockwise rotation in degrees
509 * @flip: image flip mode
510 * @flags: additional flags for image conversion
511 * @state: flags to keep track of user configuration
512 * @fimc_dev: the FIMC device this context applies to
513 * @m2m_ctx: memory-to-memory device context
517 struct fimc_frame s_frame;
518 struct fimc_frame d_frame;
523 enum fimc_datapath in_path;
524 enum fimc_datapath out_path;
525 struct fimc_scaler scaler;
526 struct fimc_effect effect;
532 struct fimc_dev *fimc_dev;
533 struct v4l2_m2m_ctx *m2m_ctx;
537 static inline int tiled_fmt(struct fimc_fmt *fmt)
539 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
542 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
544 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
545 cfg |= S5P_CIGCTRL_IRQ_CLR;
546 writel(cfg, dev->regs + S5P_CIGCTRL);
549 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
551 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
553 cfg |= S5P_CISCCTRL_SCALERSTART;
555 cfg &= ~S5P_CISCCTRL_SCALERSTART;
556 writel(cfg, dev->regs + S5P_CISCCTRL);
559 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
561 u32 cfg = readl(dev->regs + S5P_MSCTRL);
563 cfg |= S5P_MSCTRL_ENVID;
565 cfg &= ~S5P_MSCTRL_ENVID;
566 writel(cfg, dev->regs + S5P_MSCTRL);
569 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
571 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
572 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
573 writel(cfg, dev->regs + S5P_CIIMGCPT);
577 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
578 * @mask: each bit corresponds to one of 32 output buffer registers set
579 * 1 to include buffer in the sequence, 0 to disable
581 * This function mask output DMA ring buffers, i.e. it allows to configure
582 * which of the output buffer address registers will be used by the DMA
585 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
587 writel(mask, dev->regs + S5P_CIFCNTSEQ);
590 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
591 enum v4l2_buf_type type)
593 struct fimc_frame *frame;
595 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
596 if (ctx->state & FIMC_CTX_M2M)
597 frame = &ctx->s_frame;
599 return ERR_PTR(-EINVAL);
600 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
601 frame = &ctx->d_frame;
603 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
604 "Wrong buffer/video queue type (%d)\n", type);
605 return ERR_PTR(-EINVAL);
611 /* Return an index to the buffer actually being written. */
612 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
616 if (dev->variant->has_cistatus2) {
617 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
618 return reg > 0 ? --reg : reg;
620 reg = readl(dev->regs + S5P_CISTATUS);
621 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
622 S5P_CISTATUS_FRAMECNT_SHIFT;
626 /* -----------------------------------------------------*/
628 void fimc_hw_reset(struct fimc_dev *fimc);
629 void fimc_hw_set_irq_level(struct fimc_dev *dev);
630 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
631 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
632 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
633 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
634 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
635 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
636 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
637 void fimc_hw_en_capture(struct fimc_ctx *ctx);
638 void fimc_hw_set_effect(struct fimc_ctx *ctx);
639 void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
640 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
641 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
642 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
643 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
645 int fimc_hw_save_output_addr(struct fimc_dev *fimc);
646 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
647 struct s5p_fimc_isp_info *cam);
648 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
649 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
650 struct s5p_fimc_isp_info *cam);
651 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
652 struct s5p_fimc_isp_info *cam);
653 int fimc_hwset_sysreg_camblk_fimd0_wb(struct fimc_dev *fimc);
654 int fimc_hwset_sysreg_camblk_fimd1_wb(struct fimc_dev *fimc);
655 /* -----------------------------------------------------*/
657 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
658 struct v4l2_fmtdesc *f);
659 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
660 struct v4l2_format *f);
661 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
662 struct v4l2_format *f);
663 int fimc_vidioc_queryctrl(struct file *file, void *priv,
664 struct v4l2_queryctrl *qc);
665 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
666 struct v4l2_control *ctrl);
668 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
669 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
670 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
672 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
673 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
676 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
677 int dw, int dh, int rotation);
678 int fimc_set_scaler_info(struct fimc_ctx *ctx);
679 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
680 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
681 struct fimc_frame *frame, struct fimc_addr *paddr);
683 int fimc_clk_setrate(struct fimc_dev *fimc, int clk_num, void *pdata);
684 /* -----------------------------------------------------*/
686 int fimc_register_capture_device(struct fimc_dev *fimc);
687 void fimc_unregister_capture_device(struct fimc_dev *fimc);
688 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
689 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
690 struct fimc_vid_buffer *fimc_vb);
692 /* Locking: the caller holds fimc->slock */
693 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
695 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
696 fimc_hw_en_capture(ctx);
699 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
701 fimc_hw_en_lastirq(fimc, true);
702 fimc_hw_dis_capture(fimc);
703 fimc_hw_enable_scaler(fimc, false);
704 fimc_hw_en_lastirq(fimc, false);
708 * Add buf to the capture active buffers queue.
709 * Locking: Need to be called with fimc_dev::slock held.
711 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
712 struct fimc_vid_buffer *buf)
714 list_add_tail(&buf->list, &vid_cap->active_buf_q);
715 vid_cap->active_buf_cnt++;
719 * Pop a video buffer from the capture active buffers queue
720 * Locking: Need to be called with fimc_dev::slock held.
722 static inline struct fimc_vid_buffer *
723 active_queue_pop(struct fimc_vid_cap *vid_cap)
725 struct fimc_vid_buffer *buf;
726 buf = list_entry(vid_cap->active_buf_q.next,
727 struct fimc_vid_buffer, list);
728 list_del(&buf->list);
729 vid_cap->active_buf_cnt--;
733 /* Add video buffer to the capture pending buffers queue */
734 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
735 struct fimc_vid_buffer *buf)
737 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
740 /* Add video buffer to the capture pending buffers queue */
741 static inline struct fimc_vid_buffer *
742 pending_queue_pop(struct fimc_vid_cap *vid_cap)
744 struct fimc_vid_buffer *buf;
745 buf = list_entry(vid_cap->pending_buf_q.next,
746 struct fimc_vid_buffer, list);
747 list_del(&buf->list);
751 #endif /* FIMC_CORE_H_ */