drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77
  78         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  80
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  84
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  88
  89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  93         for (i = 0; i < 256; i++) {
  94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  95                        (radeon_crtc->lut_r[i] << 20) |
  96                        (radeon_crtc->lut_g[i] << 10) |
  97                        (radeon_crtc->lut_b[i] << 0));
  98         }
  99 }
 100
 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 102 {
 103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 104         struct drm_device *dev = crtc->dev;
 105         struct radeon_device *rdev = dev->dev_private;
 106         int i;
 107         uint32_t dac2_cntl;
 108
 109         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 110         if (radeon_crtc->crtc_id == 0)
 111                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 112         else
 113                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 114         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 115
 116         WREG8(RADEON_PALETTE_INDEX, 0);
 117         for (i = 0; i < 256; i++) {
 118                 WREG32(RADEON_PALETTE_30_DATA,
 119                              (radeon_crtc->lut_r[i] << 20) |
 120                              (radeon_crtc->lut_g[i] << 10) |
 121                              (radeon_crtc->lut_b[i] << 0));
 122         }
 123 }
 124
 125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129
 130         if (!crtc->enabled)
 131                 return;
 132
 133         if (ASIC_IS_DCE4(rdev))
 134                 evergreen_crtc_load_lut(crtc);
 135         else if (ASIC_IS_AVIVO(rdev))
 136                 avivo_crtc_load_lut(crtc);
 137         else
 138                 legacy_crtc_load_lut(crtc);
 139 }
 140
 141 /** Sets the color ramps on behalf of fbcon */
 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 143                               u16 blue, int regno)
 144 {
 145         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 146
 147         radeon_crtc->lut_r[regno] = red >> 6;
 148         radeon_crtc->lut_g[regno] = green >> 6;
 149         radeon_crtc->lut_b[regno] = blue >> 6;
 150 }
 151
 152 /** Gets the color ramps on behalf of fbcon */
 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 154                               u16 *blue, int regno)
 155 {
 156         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 157
 158         *red = radeon_crtc->lut_r[regno] << 6;
 159         *green = radeon_crtc->lut_g[regno] << 6;
 160         *blue = radeon_crtc->lut_b[regno] << 6;
 161 }
 162
 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 164                                   u16 *blue, uint32_t start, uint32_t size)
 165 {
 166         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 167         int end = (start + size > 256) ? 256 : start + size, i;
 168
 169         /* userspace palettes are always correct as is */
 170         for (i = start; i < end; i++) {
 171                 radeon_crtc->lut_r[i] = red[i] >> 6;
 172                 radeon_crtc->lut_g[i] = green[i] >> 6;
 173                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 174         }
 175         radeon_crtc_load_lut(crtc);
 176 }
 177
 178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 179 {
 180         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 181
 182         drm_crtc_cleanup(crtc);
 183         kfree(radeon_crtc);
 184 }
 185
 186 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 187         .cursor_set = radeon_crtc_cursor_set,
 188         .cursor_move = radeon_crtc_cursor_move,
 189         .gamma_set = radeon_crtc_gamma_set,
 190         .set_config = drm_crtc_helper_set_config,
 191         .destroy = radeon_crtc_destroy,
 192 };
 193
 194 static void radeon_crtc_init(struct drm_device *dev, int index)
 195 {
 196         struct radeon_device *rdev = dev->dev_private;
 197         struct radeon_crtc *radeon_crtc;
 198         int i;
 199
 200         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 201         if (radeon_crtc == NULL)
 202                 return;
 203
 204         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 205
 206         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 207         radeon_crtc->crtc_id = index;
 208         rdev->mode_info.crtcs[index] = radeon_crtc;
 209
 210 #if 0
 211         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 212         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 213         radeon_crtc->mode_set.num_connectors = 0;
 214 #endif
 215
 216         for (i = 0; i < 256; i++) {
 217                 radeon_crtc->lut_r[i] = i << 2;
 218                 radeon_crtc->lut_g[i] = i << 2;
 219                 radeon_crtc->lut_b[i] = i << 2;
 220         }
 221
 222         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 223                 radeon_atombios_init_crtc(dev, radeon_crtc);
 224         else
 225                 radeon_legacy_init_crtc(dev, radeon_crtc);
 226 }
 227
 228 static const char *encoder_names[34] = {
 229         "NONE",
 230         "INTERNAL_LVDS",
 231         "INTERNAL_TMDS1",
 232         "INTERNAL_TMDS2",
 233         "INTERNAL_DAC1",
 234         "INTERNAL_DAC2",
 235         "INTERNAL_SDVOA",
 236         "INTERNAL_SDVOB",
 237         "SI170B",
 238         "CH7303",
 239         "CH7301",
 240         "INTERNAL_DVO1",
 241         "EXTERNAL_SDVOA",
 242         "EXTERNAL_SDVOB",
 243         "TITFP513",
 244         "INTERNAL_LVTM1",
 245         "VT1623",
 246         "HDMI_SI1930",
 247         "HDMI_INTERNAL",
 248         "INTERNAL_KLDSCP_TMDS1",
 249         "INTERNAL_KLDSCP_DVO1",
 250         "INTERNAL_KLDSCP_DAC1",
 251         "INTERNAL_KLDSCP_DAC2",
 252         "SI178",
 253         "MVPU_FPGA",
 254         "INTERNAL_DDI",
 255         "VT1625",
 256         "HDMI_SI1932",
 257         "DP_AN9801",
 258         "DP_DP501",
 259         "INTERNAL_UNIPHY",
 260         "INTERNAL_KLDSCP_LVTMA",
 261         "INTERNAL_UNIPHY1",
 262         "INTERNAL_UNIPHY2",
 263 };
 264
 265 static const char *connector_names[15] = {
 266         "Unknown",
 267         "VGA",
 268         "DVI-I",
 269         "DVI-D",
 270         "DVI-A",
 271         "Composite",
 272         "S-video",
 273         "LVDS",
 274         "Component",
 275         "DIN",
 276         "DisplayPort",
 277         "HDMI-A",
 278         "HDMI-B",
 279         "TV",
 280         "eDP",
 281 };
 282
 283 static const char *hpd_names[6] = {
 284         "HPD1",
 285         "HPD2",
 286         "HPD3",
 287         "HPD4",
 288         "HPD5",
 289         "HPD6",
 290 };
 291
 292 static void radeon_print_display_setup(struct drm_device *dev)
 293 {
 294         struct drm_connector *connector;
 295         struct radeon_connector *radeon_connector;
 296         struct drm_encoder *encoder;
 297         struct radeon_encoder *radeon_encoder;
 298         uint32_t devices;
 299         int i = 0;
 300
 301         DRM_INFO("Radeon Display Connectors\n");
 302         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 303                 radeon_connector = to_radeon_connector(connector);
 304                 DRM_INFO("Connector %d:\n", i);
 305                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 306                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 307                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 308                 if (radeon_connector->ddc_bus) {
 309                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 310                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 311                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 312                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 313                                  radeon_connector->ddc_bus->rec.a_data_reg,
 314                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 315                                  radeon_connector->ddc_bus->rec.en_data_reg,
 316                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 317                                  radeon_connector->ddc_bus->rec.y_data_reg);
 318                         if (radeon_connector->router_bus)
 319                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 320                                          radeon_connector->router.mux_control_pin,
 321                                          radeon_connector->router.mux_state);
 322                 } else {
 323                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 324                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 325                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 326                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 327                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 328                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 329                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 330                 }
 331                 DRM_INFO("  Encoders:\n");
 332                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 333                         radeon_encoder = to_radeon_encoder(encoder);
 334                         devices = radeon_encoder->devices & radeon_connector->devices;
 335                         if (devices) {
 336                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 337                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 338                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 339                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 340                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 341                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 342                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 343                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 344                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 345                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 346                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 347                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 348                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 349                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 350                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 351                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 352                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 353                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 354                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 355                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 356                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 357                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 358                         }
 359                 }
 360                 i++;
 361         }
 362 }
 363
 364 static bool radeon_setup_enc_conn(struct drm_device *dev)
 365 {
 366         struct radeon_device *rdev = dev->dev_private;
 367         struct drm_connector *drm_connector;
 368         bool ret = false;
 369
 370         if (rdev->bios) {
 371                 if (rdev->is_atom_bios) {
 372                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 373                         if (ret == false)
 374                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 375                 } else {
 376                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 377                         if (ret == false)
 378                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 379                 }
 380         } else {
 381                 if (!ASIC_IS_AVIVO(rdev))
 382                         ret = radeon_get_legacy_connector_info_from_table(dev);
 383         }
 384         if (ret) {
 385                 radeon_setup_encoder_clones(dev);
 386                 radeon_print_display_setup(dev);
 387                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 388                         radeon_ddc_dump(drm_connector);
 389         }
 390
 391         return ret;
 392 }
 393
 394 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 395 {
 396         struct drm_device *dev = radeon_connector->base.dev;
 397         struct radeon_device *rdev = dev->dev_private;
 398         int ret = 0;
 399
 400         /* on hw with routers, select right port */
 401         if (radeon_connector->router.valid)
 402                 radeon_router_select_port(radeon_connector);
 403
 404         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 405             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 406                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 407                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 408                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 409                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 410         }
 411         if (!radeon_connector->ddc_bus)
 412                 return -1;
 413         if (!radeon_connector->edid) {
 414                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 415         }
 416         /* some servers provide a hardcoded edid in rom for KVMs */
 417         if (!radeon_connector->edid)
 418                 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
 419         if (radeon_connector->edid) {
 420                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 421                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 422                 return ret;
 423         }
 424         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 425         return 0;
 426 }
 427
 428 static int radeon_ddc_dump(struct drm_connector *connector)
 429 {
 430         struct edid *edid;
 431         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 432         int ret = 0;
 433
 434         /* on hw with routers, select right port */
 435         if (radeon_connector->router.valid)
 436                 radeon_router_select_port(radeon_connector);
 437
 438         if (!radeon_connector->ddc_bus)
 439                 return -1;
 440         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 441         if (edid) {
 442                 kfree(edid);
 443         }
 444         return ret;
 445 }
 446
 447 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 448 {
 449         uint64_t mod;
 450
 451         n += d / 2;
 452
 453         mod = do_div(n, d);
 454         return n;
 455 }
 456
 457 static void radeon_compute_pll_legacy(struct radeon_pll *pll,
 458                                       uint64_t freq,
 459                                       uint32_t *dot_clock_p,
 460                                       uint32_t *fb_div_p,
 461                                       uint32_t *frac_fb_div_p,
 462                                       uint32_t *ref_div_p,
 463                                       uint32_t *post_div_p)
 464 {
 465         uint32_t min_ref_div = pll->min_ref_div;
 466         uint32_t max_ref_div = pll->max_ref_div;
 467         uint32_t min_post_div = pll->min_post_div;
 468         uint32_t max_post_div = pll->max_post_div;
 469         uint32_t min_fractional_feed_div = 0;
 470         uint32_t max_fractional_feed_div = 0;
 471         uint32_t best_vco = pll->best_vco;
 472         uint32_t best_post_div = 1;
 473         uint32_t best_ref_div = 1;
 474         uint32_t best_feedback_div = 1;
 475         uint32_t best_frac_feedback_div = 0;
 476         uint32_t best_freq = -1;
 477         uint32_t best_error = 0xffffffff;
 478         uint32_t best_vco_diff = 1;
 479         uint32_t post_div;
 480         u32 pll_out_min, pll_out_max;
 481
 482         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 483         freq = freq * 1000;
 484
 485         if (pll->flags & RADEON_PLL_IS_LCD) {
 486                 pll_out_min = pll->lcd_pll_out_min;
 487                 pll_out_max = pll->lcd_pll_out_max;
 488         } else {
 489                 pll_out_min = pll->pll_out_min;
 490                 pll_out_max = pll->pll_out_max;
 491         }
 492
 493         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 494                 min_ref_div = max_ref_div = pll->reference_div;
 495         else {
 496                 while (min_ref_div < max_ref_div-1) {
 497                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 498                         uint32_t pll_in = pll->reference_freq / mid;
 499                         if (pll_in < pll->pll_in_min)
 500                                 max_ref_div = mid;
 501                         else if (pll_in > pll->pll_in_max)
 502                                 min_ref_div = mid;
 503                         else
 504                                 break;
 505                 }
 506         }
 507
 508         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 509                 min_post_div = max_post_div = pll->post_div;
 510
 511         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 512                 min_fractional_feed_div = pll->min_frac_feedback_div;
 513                 max_fractional_feed_div = pll->max_frac_feedback_div;
 514         }
 515
 516         for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
 517                 uint32_t ref_div;
 518
 519                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 520                         continue;
 521
 522                 /* legacy radeons only have a few post_divs */
 523                 if (pll->flags & RADEON_PLL_LEGACY) {
 524                         if ((post_div == 5) ||
 525                             (post_div == 7) ||
 526                             (post_div == 9) ||
 527                             (post_div == 10) ||
 528                             (post_div == 11) ||
 529                             (post_div == 13) ||
 530                             (post_div == 14) ||
 531                             (post_div == 15))
 532                                 continue;
 533                 }
 534
 535                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 536                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 537                         uint32_t pll_in = pll->reference_freq / ref_div;
 538                         uint32_t min_feed_div = pll->min_feedback_div;
 539                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 540
 541                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 542                                 continue;
 543
 544                         while (min_feed_div < max_feed_div) {
 545                                 uint32_t vco;
 546                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 547                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 548                                 uint32_t frac_feedback_div;
 549                                 uint64_t tmp;
 550
 551                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 552
 553                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 554                                 vco = radeon_div(tmp, ref_div);
 555
 556                                 if (vco < pll_out_min) {
 557                                         min_feed_div = feedback_div + 1;
 558                                         continue;
 559                                 } else if (vco > pll_out_max) {
 560                                         max_feed_div = feedback_div;
 561                                         continue;
 562                                 }
 563
 564                                 while (min_frac_feed_div < max_frac_feed_div) {
 565                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 566                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 567                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 568                                         current_freq = radeon_div(tmp, ref_div * post_div);
 569
 570                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 571                                                 if (freq < current_freq)
 572                                                         error = 0xffffffff;
 573                                                 else
 574                                                         error = freq - current_freq;
 575                                         } else
 576                                                 error = abs(current_freq - freq);
 577                                         vco_diff = abs(vco - best_vco);
 578
 579                                         if ((best_vco == 0 && error < best_error) ||
 580                                             (best_vco != 0 &&
 581                                              ((best_error > 100 && error < best_error - 100) ||
 582                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 583                                                 best_post_div = post_div;
 584                                                 best_ref_div = ref_div;
 585                                                 best_feedback_div = feedback_div;
 586                                                 best_frac_feedback_div = frac_feedback_div;
 587                                                 best_freq = current_freq;
 588                                                 best_error = error;
 589                                                 best_vco_diff = vco_diff;
 590                                         } else if (current_freq == freq) {
 591                                                 if (best_freq == -1) {
 592                                                         best_post_div = post_div;
 593                                                         best_ref_div = ref_div;
 594                                                         best_feedback_div = feedback_div;
 595                                                         best_frac_feedback_div = frac_feedback_div;
 596                                                         best_freq = current_freq;
 597                                                         best_error = error;
 598                                                         best_vco_diff = vco_diff;
 599                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 600                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 601                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 602                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 603                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 604                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 605                                                         best_post_div = post_div;
 606                                                         best_ref_div = ref_div;
 607                                                         best_feedback_div = feedback_div;
 608                                                         best_frac_feedback_div = frac_feedback_div;
 609                                                         best_freq = current_freq;
 610                                                         best_error = error;
 611                                                         best_vco_diff = vco_diff;
 612                                                 }
 613                                         }
 614                                         if (current_freq < freq)
 615                                                 min_frac_feed_div = frac_feedback_div + 1;
 616                                         else
 617                                                 max_frac_feed_div = frac_feedback_div;
 618                                 }
 619                                 if (current_freq < freq)
 620                                         min_feed_div = feedback_div + 1;
 621                                 else
 622                                         max_feed_div = feedback_div;
 623                         }
 624                 }
 625         }
 626
 627         *dot_clock_p = best_freq / 10000;
 628         *fb_div_p = best_feedback_div;
 629         *frac_fb_div_p = best_frac_feedback_div;
 630         *ref_div_p = best_ref_div;
 631         *post_div_p = best_post_div;
 632         DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 633                       freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
 634                       best_ref_div, best_post_div);
 635
 636 }
 637
 638 static bool
 639 calc_fb_div(struct radeon_pll *pll,
 640             uint32_t freq,
 641             uint32_t post_div,
 642             uint32_t ref_div,
 643             uint32_t *fb_div,
 644             uint32_t *fb_div_frac)
 645 {
 646         fixed20_12 feedback_divider, a, b;
 647         u32 vco_freq;
 648
 649         vco_freq = freq * post_div;
 650         /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
 651         a.full = dfixed_const(pll->reference_freq);
 652         feedback_divider.full = dfixed_const(vco_freq);
 653         feedback_divider.full = dfixed_div(feedback_divider, a);
 654         a.full = dfixed_const(ref_div);
 655         feedback_divider.full = dfixed_mul(feedback_divider, a);
 656
 657         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 658                 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
 659                 a.full = dfixed_const(10);
 660                 feedback_divider.full = dfixed_mul(feedback_divider, a);
 661                 feedback_divider.full += dfixed_const_half(0);
 662                 feedback_divider.full = dfixed_floor(feedback_divider);
 663                 feedback_divider.full = dfixed_div(feedback_divider, a);
 664
 665                 /* *fb_div = floor(feedback_divider); */
 666                 a.full = dfixed_floor(feedback_divider);
 667                 *fb_div = dfixed_trunc(a);
 668                 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
 669                 a.full = dfixed_const(10);
 670                 b.full = dfixed_mul(feedback_divider, a);
 671
 672                 feedback_divider.full = dfixed_floor(feedback_divider);
 673                 feedback_divider.full = dfixed_mul(feedback_divider, a);
 674                 feedback_divider.full = b.full - feedback_divider.full;
 675                 *fb_div_frac = dfixed_trunc(feedback_divider);
 676         } else {
 677                 /* *fb_div = floor(feedback_divider + 0.5); */
 678                 feedback_divider.full += dfixed_const_half(0);
 679                 feedback_divider.full = dfixed_floor(feedback_divider);
 680
 681                 *fb_div = dfixed_trunc(feedback_divider);
 682                 *fb_div_frac = 0;
 683         }
 684
 685         if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
 686                 return false;
 687         else
 688                 return true;
 689 }
 690
 691 static bool
 692 calc_fb_ref_div(struct radeon_pll *pll,
 693                 uint32_t freq,
 694                 uint32_t post_div,
 695                 uint32_t *fb_div,
 696                 uint32_t *fb_div_frac,
 697                 uint32_t *ref_div)
 698 {
 699         fixed20_12 ffreq, max_error, error, pll_out, a;
 700         u32 vco;
 701         u32 pll_out_min, pll_out_max;
 702
 703         if (pll->flags & RADEON_PLL_IS_LCD) {
 704                 pll_out_min = pll->lcd_pll_out_min;
 705                 pll_out_max = pll->lcd_pll_out_max;
 706         } else {
 707                 pll_out_min = pll->pll_out_min;
 708                 pll_out_max = pll->pll_out_max;
 709         }
 710
 711         ffreq.full = dfixed_const(freq);
 712         /* max_error = ffreq * 0.0025; */
 713         a.full = dfixed_const(400);
 714         max_error.full = dfixed_div(ffreq, a);
 715
 716         for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
 717                 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
 718                         vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
 719                         vco = vco / ((*ref_div) * 10);
 720
 721                         if ((vco < pll_out_min) || (vco > pll_out_max))
 722                                 continue;
 723
 724                         /* pll_out = vco / post_div; */
 725                         a.full = dfixed_const(post_div);
 726                         pll_out.full = dfixed_const(vco);
 727                         pll_out.full = dfixed_div(pll_out, a);
 728
 729                         if (pll_out.full >= ffreq.full) {
 730                                 error.full = pll_out.full - ffreq.full;
 731                                 if (error.full <= max_error.full)
 732                                         return true;
 733                         }
 734                 }
 735         }
 736         return false;
 737 }
 738
 739 static void radeon_compute_pll_new(struct radeon_pll *pll,
 740                                    uint64_t freq,
 741                                    uint32_t *dot_clock_p,
 742                                    uint32_t *fb_div_p,
 743                                    uint32_t *frac_fb_div_p,
 744                                    uint32_t *ref_div_p,
 745                                    uint32_t *post_div_p)
 746 {
 747         u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
 748         u32 best_freq = 0, vco_frequency;
 749         u32 pll_out_min, pll_out_max;
 750
 751         if (pll->flags & RADEON_PLL_IS_LCD) {
 752                 pll_out_min = pll->lcd_pll_out_min;
 753                 pll_out_max = pll->lcd_pll_out_max;
 754         } else {
 755                 pll_out_min = pll->pll_out_min;
 756                 pll_out_max = pll->pll_out_max;
 757         }
 758
 759         /* freq = freq / 10; */
 760         do_div(freq, 10);
 761
 762         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 763                 post_div = pll->post_div;
 764                 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
 765                         goto done;
 766
 767                 vco_frequency = freq * post_div;
 768                 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
 769                         goto done;
 770
 771                 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
 772                         ref_div = pll->reference_div;
 773                         if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
 774                                 goto done;
 775                         if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
 776                                 goto done;
 777                 }
 778         } else {
 779                 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
 780                         if (pll->flags & RADEON_PLL_LEGACY) {
 781                                 if ((post_div == 5) ||
 782                                     (post_div == 7) ||
 783                                     (post_div == 9) ||
 784                                     (post_div == 10) ||
 785                                     (post_div == 11))
 786                                         continue;
 787                         }
 788
 789                         if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 790                                 continue;
 791
 792                         vco_frequency = freq * post_div;
 793                         if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
 794                                 continue;
 795                         if (pll->flags & RADEON_PLL_USE_REF_DIV) {
 796                                 ref_div = pll->reference_div;
 797                                 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
 798                                         goto done;
 799                                 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
 800                                         break;
 801                         } else {
 802                                 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
 803                                         break;
 804                         }
 805                 }
 806         }
 807
 808         best_freq = pll->reference_freq * 10 * fb_div;
 809         best_freq += pll->reference_freq * fb_div_frac;
 810         best_freq = best_freq / (ref_div * post_div);
 811
 812 done:
 813         if (best_freq == 0)
 814                 DRM_ERROR("Couldn't find valid PLL dividers\n");
 815
 816         *dot_clock_p = best_freq / 10;
 817         *fb_div_p = fb_div;
 818         *frac_fb_div_p = fb_div_frac;
 819         *ref_div_p = ref_div;
 820         *post_div_p = post_div;
 821
 822         DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 823 }
 824
 825 void radeon_compute_pll(struct radeon_pll *pll,
 826                         uint64_t freq,
 827                         uint32_t *dot_clock_p,
 828                         uint32_t *fb_div_p,
 829                         uint32_t *frac_fb_div_p,
 830                         uint32_t *ref_div_p,
 831                         uint32_t *post_div_p)
 832 {
 833         switch (pll->algo) {
 834         case PLL_ALGO_NEW:
 835                 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
 836                                        frac_fb_div_p, ref_div_p, post_div_p);
 837                 break;
 838         case PLL_ALGO_LEGACY:
 839         default:
 840                 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
 841                                           frac_fb_div_p, ref_div_p, post_div_p);
 842                 break;
 843         }
 844 }
 845
 846 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 847 {
 848         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 849
 850         if (radeon_fb->obj) {
 851                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 852         }
 853         drm_framebuffer_cleanup(fb);
 854         kfree(radeon_fb);
 855 }
 856
 857 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 858                                                   struct drm_file *file_priv,
 859                                                   unsigned int *handle)
 860 {
 861         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 862
 863         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 864 }
 865
 866 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 867         .destroy = radeon_user_framebuffer_destroy,
 868         .create_handle = radeon_user_framebuffer_create_handle,
 869 };
 870
 871 void
 872 radeon_framebuffer_init(struct drm_device *dev,
 873                         struct radeon_framebuffer *rfb,
 874                         struct drm_mode_fb_cmd *mode_cmd,
 875                         struct drm_gem_object *obj)
 876 {
 877         rfb->obj = obj;
 878         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 879         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 880 }
 881
 882 static struct drm_framebuffer *
 883 radeon_user_framebuffer_create(struct drm_device *dev,
 884                                struct drm_file *file_priv,
 885                                struct drm_mode_fb_cmd *mode_cmd)
 886 {
 887         struct drm_gem_object *obj;
 888         struct radeon_framebuffer *radeon_fb;
 889
 890         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 891         if (obj ==  NULL) {
 892                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 893                         "can't create framebuffer\n", mode_cmd->handle);
 894                 return ERR_PTR(-ENOENT);
 895         }
 896
 897         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 898         if (radeon_fb == NULL)
 899                 return ERR_PTR(-ENOMEM);
 900
 901         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 902
 903         return &radeon_fb->base;
 904 }
 905
 906 static void radeon_output_poll_changed(struct drm_device *dev)
 907 {
 908         struct radeon_device *rdev = dev->dev_private;
 909         radeon_fb_output_poll_changed(rdev);
 910 }
 911
 912 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 913         .fb_create = radeon_user_framebuffer_create,
 914         .output_poll_changed = radeon_output_poll_changed
 915 };
 916
 917 struct drm_prop_enum_list {
 918         int type;
 919         char *name;
 920 };
 921
 922 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 923 {       { 0, "driver" },
 924         { 1, "bios" },
 925 };
 926
 927 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 928 {       { TV_STD_NTSC, "ntsc" },
 929         { TV_STD_PAL, "pal" },
 930         { TV_STD_PAL_M, "pal-m" },
 931         { TV_STD_PAL_60, "pal-60" },
 932         { TV_STD_NTSC_J, "ntsc-j" },
 933         { TV_STD_SCART_PAL, "scart-pal" },
 934         { TV_STD_PAL_CN, "pal-cn" },
 935         { TV_STD_SECAM, "secam" },
 936 };
 937
 938 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
 939 {       { UNDERSCAN_OFF, "off" },
 940         { UNDERSCAN_ON, "on" },
 941         { UNDERSCAN_AUTO, "auto" },
 942 };
 943
 944 static int radeon_modeset_create_props(struct radeon_device *rdev)
 945 {
 946         int i, sz;
 947
 948         if (rdev->is_atom_bios) {
 949                 rdev->mode_info.coherent_mode_property =
 950                         drm_property_create(rdev->ddev,
 951                                             DRM_MODE_PROP_RANGE,
 952                                             "coherent", 2);
 953                 if (!rdev->mode_info.coherent_mode_property)
 954                         return -ENOMEM;
 955
 956                 rdev->mode_info.coherent_mode_property->values[0] = 0;
 957                 rdev->mode_info.coherent_mode_property->values[1] = 1;
 958         }
 959
 960         if (!ASIC_IS_AVIVO(rdev)) {
 961                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 962                 rdev->mode_info.tmds_pll_property =
 963                         drm_property_create(rdev->ddev,
 964                                             DRM_MODE_PROP_ENUM,
 965                                             "tmds_pll", sz);
 966                 for (i = 0; i < sz; i++) {
 967                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
 968                                               i,
 969                                               radeon_tmds_pll_enum_list[i].type,
 970                                               radeon_tmds_pll_enum_list[i].name);
 971                 }
 972         }
 973
 974         rdev->mode_info.load_detect_property =
 975                 drm_property_create(rdev->ddev,
 976                                     DRM_MODE_PROP_RANGE,
 977                                     "load detection", 2);
 978         if (!rdev->mode_info.load_detect_property)
 979                 return -ENOMEM;
 980         rdev->mode_info.load_detect_property->values[0] = 0;
 981         rdev->mode_info.load_detect_property->values[1] = 1;
 982
 983         drm_mode_create_scaling_mode_property(rdev->ddev);
 984
 985         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 986         rdev->mode_info.tv_std_property =
 987                 drm_property_create(rdev->ddev,
 988                                     DRM_MODE_PROP_ENUM,
 989                                     "tv standard", sz);
 990         for (i = 0; i < sz; i++) {
 991                 drm_property_add_enum(rdev->mode_info.tv_std_property,
 992                                       i,
 993                                       radeon_tv_std_enum_list[i].type,
 994                                       radeon_tv_std_enum_list[i].name);
 995         }
 996
 997         sz = ARRAY_SIZE(radeon_underscan_enum_list);
 998         rdev->mode_info.underscan_property =
 999                 drm_property_create(rdev->ddev,
1000                                     DRM_MODE_PROP_ENUM,
1001                                     "underscan", sz);
1002         for (i = 0; i < sz; i++) {
1003                 drm_property_add_enum(rdev->mode_info.underscan_property,
1004                                       i,
1005                                       radeon_underscan_enum_list[i].type,
1006                                       radeon_underscan_enum_list[i].name);
1007         }
1008
1009         return 0;
1010 }
1011
1012 void radeon_update_display_priority(struct radeon_device *rdev)
1013 {
1014         /* adjustment options for the display watermarks */
1015         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1016                 /* set display priority to high for r3xx, rv515 chips
1017                  * this avoids flickering due to underflow to the
1018                  * display controllers during heavy acceleration.
1019                  * Don't force high on rs4xx igp chips as it seems to
1020                  * affect the sound card.  See kernel bug 15982.
1021                  */
1022                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1023                     !(rdev->flags & RADEON_IS_IGP))
1024                         rdev->disp_priority = 2;
1025                 else
1026                         rdev->disp_priority = 0;
1027         } else
1028                 rdev->disp_priority = radeon_disp_priority;
1029
1030 }
1031
1032 int radeon_modeset_init(struct radeon_device *rdev)
1033 {
1034         int i;
1035         int ret;
1036
1037         drm_mode_config_init(rdev->ddev);
1038         rdev->mode_info.mode_config_initialized = true;
1039
1040         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1041
1042         if (ASIC_IS_AVIVO(rdev)) {
1043                 rdev->ddev->mode_config.max_width = 8192;
1044                 rdev->ddev->mode_config.max_height = 8192;
1045         } else {
1046                 rdev->ddev->mode_config.max_width = 4096;
1047                 rdev->ddev->mode_config.max_height = 4096;
1048         }
1049
1050         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1051
1052         ret = radeon_modeset_create_props(rdev);
1053         if (ret) {
1054                 return ret;
1055         }
1056
1057         /* init i2c buses */
1058         radeon_i2c_init(rdev);
1059
1060         /* check combios for a valid hardcoded EDID - Sun servers */
1061         if (!rdev->is_atom_bios) {
1062                 /* check for hardcoded EDID in BIOS */
1063                 radeon_combios_check_hardcoded_edid(rdev);
1064         }
1065
1066         /* allocate crtcs */
1067         for (i = 0; i < rdev->num_crtc; i++) {
1068                 radeon_crtc_init(rdev->ddev, i);
1069         }
1070
1071         /* okay we should have all the bios connectors */
1072         ret = radeon_setup_enc_conn(rdev->ddev);
1073         if (!ret) {
1074                 return ret;
1075         }
1076         /* initialize hpd */
1077         radeon_hpd_init(rdev);
1078
1079         /* Initialize power management */
1080         radeon_pm_init(rdev);
1081
1082         radeon_fbdev_init(rdev);
1083         drm_kms_helper_poll_init(rdev->ddev);
1084
1085         return 0;
1086 }
1087
1088 void radeon_modeset_fini(struct radeon_device *rdev)
1089 {
1090         radeon_fbdev_fini(rdev);
1091         kfree(rdev->mode_info.bios_hardcoded_edid);
1092         radeon_pm_fini(rdev);
1093
1094         if (rdev->mode_info.mode_config_initialized) {
1095                 drm_kms_helper_poll_fini(rdev->ddev);
1096                 radeon_hpd_fini(rdev);
1097                 drm_mode_config_cleanup(rdev->ddev);
1098                 rdev->mode_info.mode_config_initialized = false;
1099         }
1100         /* free i2c buses */
1101         radeon_i2c_fini(rdev);
1102 }
1103
1104 static bool is_hdtv_mode(struct drm_display_mode *mode)
1105 {
1106         /* try and guess if this is a tv or a monitor */
1107         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1108             (mode->vdisplay == 576) || /* 576p */
1109             (mode->vdisplay == 720) || /* 720p */
1110             (mode->vdisplay == 1080)) /* 1080p */
1111                 return true;
1112         else
1113                 return false;
1114 }
1115
1116 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1117                                 struct drm_display_mode *mode,
1118                                 struct drm_display_mode *adjusted_mode)
1119 {
1120         struct drm_device *dev = crtc->dev;
1121         struct radeon_device *rdev = dev->dev_private;
1122         struct drm_encoder *encoder;
1123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1124         struct radeon_encoder *radeon_encoder;
1125         struct drm_connector *connector;
1126         struct radeon_connector *radeon_connector;
1127         bool first = true;
1128         u32 src_v = 1, dst_v = 1;
1129         u32 src_h = 1, dst_h = 1;
1130
1131         radeon_crtc->h_border = 0;
1132         radeon_crtc->v_border = 0;
1133
1134         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1135                 if (encoder->crtc != crtc)
1136                         continue;
1137                 radeon_encoder = to_radeon_encoder(encoder);
1138                 connector = radeon_get_connector_for_encoder(encoder);
1139                 radeon_connector = to_radeon_connector(connector);
1140
1141                 if (first) {
1142                         /* set scaling */
1143                         if (radeon_encoder->rmx_type == RMX_OFF)
1144                                 radeon_crtc->rmx_type = RMX_OFF;
1145                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1146                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1147                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1148                         else
1149                                 radeon_crtc->rmx_type = RMX_OFF;
1150                         /* copy native mode */
1151                         memcpy(&radeon_crtc->native_mode,
1152                                &radeon_encoder->native_mode,
1153                                 sizeof(struct drm_display_mode));
1154                         src_v = crtc->mode.vdisplay;
1155                         dst_v = radeon_crtc->native_mode.vdisplay;
1156                         src_h = crtc->mode.hdisplay;
1157                         dst_h = radeon_crtc->native_mode.hdisplay;
1158
1159                         /* fix up for overscan on hdmi */
1160                         if (ASIC_IS_AVIVO(rdev) &&
1161                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1162                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1163                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1164                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1165                               is_hdtv_mode(mode)))) {
1166                                 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1167                                 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1168                                 radeon_crtc->rmx_type = RMX_FULL;
1169                                 src_v = crtc->mode.vdisplay;
1170                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1171                                 src_h = crtc->mode.hdisplay;
1172                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1173                         }
1174                         first = false;
1175                 } else {
1176                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1177                                 /* WARNING: Right now this can't happen but
1178                                  * in the future we need to check that scaling
1179                                  * are consistent across different encoder
1180                                  * (ie all encoder can work with the same
1181                                  *  scaling).
1182                                  */
1183                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1184                                 return false;
1185                         }
1186                 }
1187         }
1188         if (radeon_crtc->rmx_type != RMX_OFF) {
1189                 fixed20_12 a, b;
1190                 a.full = dfixed_const(src_v);
1191                 b.full = dfixed_const(dst_v);
1192                 radeon_crtc->vsc.full = dfixed_div(a, b);
1193                 a.full = dfixed_const(src_h);
1194                 b.full = dfixed_const(dst_h);
1195                 radeon_crtc->hsc.full = dfixed_div(a, b);
1196         } else {
1197                 radeon_crtc->vsc.full = dfixed_const(1);
1198                 radeon_crtc->hsc.full = dfixed_const(1);
1199         }
1200         return true;
1201 }