drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u8 new_delay = dev_priv->cur_delay;
 282
 283         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 284         busy_up = I915_READ(RCPREVBSYTUPAVG);
 285         busy_down = I915_READ(RCPREVBSYTDNAVG);
 286         max_avg = I915_READ(RCBMAXAVG);
 287         min_avg = I915_READ(RCBMINAVG);
 288
 289         /* Handle RCS change request from hw */
 290         if (busy_up > max_avg) {
 291                 if (dev_priv->cur_delay != dev_priv->max_delay)
 292                         new_delay = dev_priv->cur_delay - 1;
 293                 if (new_delay < dev_priv->max_delay)
 294                         new_delay = dev_priv->max_delay;
 295         } else if (busy_down < min_avg) {
 296                 if (dev_priv->cur_delay != dev_priv->min_delay)
 297                         new_delay = dev_priv->cur_delay + 1;
 298                 if (new_delay > dev_priv->min_delay)
 299                         new_delay = dev_priv->min_delay;
 300         }
 301
 302         if (ironlake_set_drps(dev, new_delay))
 303                 dev_priv->cur_delay = new_delay;
 304
 305         return;
 306 }
 307
 308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 309 {
 310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 311         int ret = IRQ_NONE;
 312         u32 de_iir, gt_iir, de_ier, pch_iir;
 313         u32 hotplug_mask;
 314         struct drm_i915_master_private *master_priv;
 315         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 316
 317         /* disable master interrupt before clearing iir  */
 318         de_ier = I915_READ(DEIER);
 319         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 320         (void)I915_READ(DEIER);
 321
 322         de_iir = I915_READ(DEIIR);
 323         gt_iir = I915_READ(GTIIR);
 324         pch_iir = I915_READ(SDEIIR);
 325
 326         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 327                 goto done;
 328
 329         if (HAS_PCH_CPT(dev))
 330                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 331         else
 332                 hotplug_mask = SDE_HOTPLUG_MASK;
 333
 334         ret = IRQ_HANDLED;
 335
 336         if (dev->primary->master) {
 337                 master_priv = dev->primary->master->driver_priv;
 338                 if (master_priv->sarea_priv)
 339                         master_priv->sarea_priv->last_dispatch =
 340                                 READ_BREADCRUMB(dev_priv);
 341         }
 342
 343         if (gt_iir & GT_PIPE_NOTIFY) {
 344                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 345                 render_ring->irq_gem_seqno = seqno;
 346                 trace_i915_gem_request_complete(dev, seqno);
 347                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 348                 dev_priv->hangcheck_count = 0;
 349                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 350         }
 351         if (gt_iir & GT_BSD_USER_INTERRUPT)
 352                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 353
 354
 355         if (de_iir & DE_GSE)
 356                 ironlake_opregion_gse_intr(dev);
 357
 358         if (de_iir & DE_PLANEA_FLIP_DONE) {
 359                 intel_prepare_page_flip(dev, 0);
 360                 intel_finish_page_flip(dev, 0);
 361         }
 362
 363         if (de_iir & DE_PLANEB_FLIP_DONE) {
 364                 intel_prepare_page_flip(dev, 1);
 365                 intel_finish_page_flip(dev, 1);
 366         }
 367
 368         if (de_iir & DE_PIPEA_VBLANK)
 369                 drm_handle_vblank(dev, 0);
 370
 371         if (de_iir & DE_PIPEB_VBLANK)
 372                 drm_handle_vblank(dev, 1);
 373
 374         /* check event from PCH */
 375         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 376                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 377
 378         if (de_iir & DE_PCU_EVENT) {
 379                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 380                 i915_handle_rps_change(dev);
 381         }
 382
 383         /* should clear PCH hotplug event before clear CPU irq */
 384         I915_WRITE(SDEIIR, pch_iir);
 385         I915_WRITE(GTIIR, gt_iir);
 386         I915_WRITE(DEIIR, de_iir);
 387
 388 done:
 389         I915_WRITE(DEIER, de_ier);
 390         (void)I915_READ(DEIER);
 391
 392         return ret;
 393 }
 394
 395 /**
 396  * i915_error_work_func - do process context error handling work
 397  * @work: work struct
 398  *
 399  * Fire an error uevent so userspace can see that a hang or error
 400  * was detected.
 401  */
 402 static void i915_error_work_func(struct work_struct *work)
 403 {
 404         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 405                                                     error_work);
 406         struct drm_device *dev = dev_priv->dev;
 407         char *error_event[] = { "ERROR=1", NULL };
 408         char *reset_event[] = { "RESET=1", NULL };
 409         char *reset_done_event[] = { "ERROR=0", NULL };
 410
 411         DRM_DEBUG_DRIVER("generating error event\n");
 412         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 413
 414         if (atomic_read(&dev_priv->mm.wedged)) {
 415                 if (IS_I965G(dev)) {
 416                         DRM_DEBUG_DRIVER("resetting chip\n");
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 418                         if (!i965_reset(dev, GDRST_RENDER)) {
 419                                 atomic_set(&dev_priv->mm.wedged, 0);
 420                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 421                         }
 422                 } else {
 423                         DRM_DEBUG_DRIVER("reboot required\n");
 424                 }
 425         }
 426 }
 427
 428 static struct drm_i915_error_object *
 429 i915_error_object_create(struct drm_device *dev,
 430                          struct drm_gem_object *src)
 431 {
 432         drm_i915_private_t *dev_priv = dev->dev_private;
 433         struct drm_i915_error_object *dst;
 434         struct drm_i915_gem_object *src_priv;
 435         int page, page_count;
 436         u32 reloc_offset;
 437
 438         if (src == NULL)
 439                 return NULL;
 440
 441         src_priv = to_intel_bo(src);
 442         if (src_priv->pages == NULL)
 443                 return NULL;
 444
 445         page_count = src->size / PAGE_SIZE;
 446
 447         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 448         if (dst == NULL)
 449                 return NULL;
 450
 451         reloc_offset = src_priv->gtt_offset;
 452         for (page = 0; page < page_count; page++) {
 453                 unsigned long flags;
 454                 void __iomem *s;
 455                 void *d;
 456
 457                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 458                 if (d == NULL)
 459                         goto unwind;
 460
 461                 local_irq_save(flags);
 462                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 463                                              reloc_offset,
 464                                              KM_IRQ0);
 465                 memcpy_fromio(d, s, PAGE_SIZE);
 466                 io_mapping_unmap_atomic(s, KM_IRQ0);
 467                 local_irq_restore(flags);
 468
 469                 dst->pages[page] = d;
 470
 471                 reloc_offset += PAGE_SIZE;
 472         }
 473         dst->page_count = page_count;
 474         dst->gtt_offset = src_priv->gtt_offset;
 475
 476         return dst;
 477
 478 unwind:
 479         while (page--)
 480                 kfree(dst->pages[page]);
 481         kfree(dst);
 482         return NULL;
 483 }
 484
 485 static void
 486 i915_error_object_free(struct drm_i915_error_object *obj)
 487 {
 488         int page;
 489
 490         if (obj == NULL)
 491                 return;
 492
 493         for (page = 0; page < obj->page_count; page++)
 494                 kfree(obj->pages[page]);
 495
 496         kfree(obj);
 497 }
 498
 499 static void
 500 i915_error_state_free(struct drm_device *dev,
 501                       struct drm_i915_error_state *error)
 502 {
 503         i915_error_object_free(error->batchbuffer[0]);
 504         i915_error_object_free(error->batchbuffer[1]);
 505         i915_error_object_free(error->ringbuffer);
 506         kfree(error->active_bo);
 507         kfree(error->overlay);
 508         kfree(error);
 509 }
 510
 511 static u32
 512 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 513 {
 514         u32 cmd;
 515
 516         if (IS_I830(dev) || IS_845G(dev))
 517                 cmd = MI_BATCH_BUFFER;
 518         else if (IS_I965G(dev))
 519                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 520                        MI_BATCH_NON_SECURE_I965);
 521         else
 522                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 523
 524         return ring[0] == cmd ? ring[1] : 0;
 525 }
 526
 527 static u32
 528 i915_ringbuffer_last_batch(struct drm_device *dev)
 529 {
 530         struct drm_i915_private *dev_priv = dev->dev_private;
 531         u32 head, bbaddr;
 532         u32 *ring;
 533
 534         /* Locate the current position in the ringbuffer and walk back
 535          * to find the most recently dispatched batch buffer.
 536          */
 537         bbaddr = 0;
 538         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 539         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 540
 541         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 542                 bbaddr = i915_get_bbaddr(dev, ring);
 543                 if (bbaddr)
 544                         break;
 545         }
 546
 547         if (bbaddr == 0) {
 548                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 549                                 + dev_priv->render_ring.size);
 550                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 551                         bbaddr = i915_get_bbaddr(dev, ring);
 552                         if (bbaddr)
 553                                 break;
 554                 }
 555         }
 556
 557         return bbaddr;
 558 }
 559
 560 /**
 561  * i915_capture_error_state - capture an error record for later analysis
 562  * @dev: drm device
 563  *
 564  * Should be called when an error is detected (either a hang or an error
 565  * interrupt) to capture error state from the time of the error.  Fills
 566  * out a structure which becomes available in debugfs for user level tools
 567  * to pick up.
 568  */
 569 static void i915_capture_error_state(struct drm_device *dev)
 570 {
 571         struct drm_i915_private *dev_priv = dev->dev_private;
 572         struct drm_i915_gem_object *obj_priv;
 573         struct drm_i915_error_state *error;
 574         struct drm_gem_object *batchbuffer[2];
 575         unsigned long flags;
 576         u32 bbaddr;
 577         int count;
 578
 579         spin_lock_irqsave(&dev_priv->error_lock, flags);
 580         error = dev_priv->first_error;
 581         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 582         if (error)
 583                 return;
 584
 585         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 586         if (!error) {
 587                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 588                 return;
 589         }
 590
 591         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 592         error->eir = I915_READ(EIR);
 593         error->pgtbl_er = I915_READ(PGTBL_ER);
 594         error->pipeastat = I915_READ(PIPEASTAT);
 595         error->pipebstat = I915_READ(PIPEBSTAT);
 596         error->instpm = I915_READ(INSTPM);
 597         if (!IS_I965G(dev)) {
 598                 error->ipeir = I915_READ(IPEIR);
 599                 error->ipehr = I915_READ(IPEHR);
 600                 error->instdone = I915_READ(INSTDONE);
 601                 error->acthd = I915_READ(ACTHD);
 602                 error->bbaddr = 0;
 603         } else {
 604                 error->ipeir = I915_READ(IPEIR_I965);
 605                 error->ipehr = I915_READ(IPEHR_I965);
 606                 error->instdone = I915_READ(INSTDONE_I965);
 607                 error->instps = I915_READ(INSTPS);
 608                 error->instdone1 = I915_READ(INSTDONE1);
 609                 error->acthd = I915_READ(ACTHD_I965);
 610                 error->bbaddr = I915_READ64(BB_ADDR);
 611         }
 612
 613         bbaddr = i915_ringbuffer_last_batch(dev);
 614
 615         /* Grab the current batchbuffer, most likely to have crashed. */
 616         batchbuffer[0] = NULL;
 617         batchbuffer[1] = NULL;
 618         count = 0;
 619         list_for_each_entry(obj_priv,
 620                         &dev_priv->render_ring.active_list, list) {
 621
 622                 struct drm_gem_object *obj = &obj_priv->base;
 623
 624                 if (batchbuffer[0] == NULL &&
 625                     bbaddr >= obj_priv->gtt_offset &&
 626                     bbaddr < obj_priv->gtt_offset + obj->size)
 627                         batchbuffer[0] = obj;
 628
 629                 if (batchbuffer[1] == NULL &&
 630                     error->acthd >= obj_priv->gtt_offset &&
 631                     error->acthd < obj_priv->gtt_offset + obj->size)
 632                         batchbuffer[1] = obj;
 633
 634                 count++;
 635         }
 636         /* Scan the other lists for completeness for those bizarre errors. */
 637         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 638                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 639                         struct drm_gem_object *obj = &obj_priv->base;
 640
 641                         if (batchbuffer[0] == NULL &&
 642                             bbaddr >= obj_priv->gtt_offset &&
 643                             bbaddr < obj_priv->gtt_offset + obj->size)
 644                                 batchbuffer[0] = obj;
 645
 646                         if (batchbuffer[1] == NULL &&
 647                             error->acthd >= obj_priv->gtt_offset &&
 648                             error->acthd < obj_priv->gtt_offset + obj->size)
 649                                 batchbuffer[1] = obj;
 650
 651                         if (batchbuffer[0] && batchbuffer[1])
 652                                 break;
 653                 }
 654         }
 655         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 656                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 657                         struct drm_gem_object *obj = &obj_priv->base;
 658
 659                         if (batchbuffer[0] == NULL &&
 660                             bbaddr >= obj_priv->gtt_offset &&
 661                             bbaddr < obj_priv->gtt_offset + obj->size)
 662                                 batchbuffer[0] = obj;
 663
 664                         if (batchbuffer[1] == NULL &&
 665                             error->acthd >= obj_priv->gtt_offset &&
 666                             error->acthd < obj_priv->gtt_offset + obj->size)
 667                                 batchbuffer[1] = obj;
 668
 669                         if (batchbuffer[0] && batchbuffer[1])
 670                                 break;
 671                 }
 672         }
 673
 674         /* We need to copy these to an anonymous buffer as the simplest
 675          * method to avoid being overwritten by userpace.
 676          */
 677         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 678         if (batchbuffer[1] != batchbuffer[0])
 679                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 680         else
 681                 error->batchbuffer[1] = NULL;
 682
 683         /* Record the ringbuffer */
 684         error->ringbuffer = i915_error_object_create(dev,
 685                         dev_priv->render_ring.gem_object);
 686
 687         /* Record buffers on the active list. */
 688         error->active_bo = NULL;
 689         error->active_bo_count = 0;
 690
 691         if (count)
 692                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 693                                            GFP_ATOMIC);
 694
 695         if (error->active_bo) {
 696                 int i = 0;
 697                 list_for_each_entry(obj_priv,
 698                                 &dev_priv->render_ring.active_list, list) {
 699                         struct drm_gem_object *obj = &obj_priv->base;
 700
 701                         error->active_bo[i].size = obj->size;
 702                         error->active_bo[i].name = obj->name;
 703                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 704                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 705                         error->active_bo[i].read_domains = obj->read_domains;
 706                         error->active_bo[i].write_domain = obj->write_domain;
 707                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 708                         error->active_bo[i].pinned = 0;
 709                         if (obj_priv->pin_count > 0)
 710                                 error->active_bo[i].pinned = 1;
 711                         if (obj_priv->user_pin_count > 0)
 712                                 error->active_bo[i].pinned = -1;
 713                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 714                         error->active_bo[i].dirty = obj_priv->dirty;
 715                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 716
 717                         if (++i == count)
 718                                 break;
 719                 }
 720                 error->active_bo_count = i;
 721         }
 722
 723         do_gettimeofday(&error->time);
 724
 725         error->overlay = intel_overlay_capture_error_state(dev);
 726
 727         spin_lock_irqsave(&dev_priv->error_lock, flags);
 728         if (dev_priv->first_error == NULL) {
 729                 dev_priv->first_error = error;
 730                 error = NULL;
 731         }
 732         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 733
 734         if (error)
 735                 i915_error_state_free(dev, error);
 736 }
 737
 738 void i915_destroy_error_state(struct drm_device *dev)
 739 {
 740         struct drm_i915_private *dev_priv = dev->dev_private;
 741         struct drm_i915_error_state *error;
 742
 743         spin_lock(&dev_priv->error_lock);
 744         error = dev_priv->first_error;
 745         dev_priv->first_error = NULL;
 746         spin_unlock(&dev_priv->error_lock);
 747
 748         if (error)
 749                 i915_error_state_free(dev, error);
 750 }
 751
 752 static void i915_report_and_clear_eir(struct drm_device *dev)
 753 {
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         u32 eir = I915_READ(EIR);
 756
 757         if (!eir)
 758                 return;
 759
 760         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 761                eir);
 762
 763         if (IS_G4X(dev)) {
 764                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 765                         u32 ipeir = I915_READ(IPEIR_I965);
 766
 767                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 768                                I915_READ(IPEIR_I965));
 769                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 770                                I915_READ(IPEHR_I965));
 771                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 772                                I915_READ(INSTDONE_I965));
 773                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 774                                I915_READ(INSTPS));
 775                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 776                                I915_READ(INSTDONE1));
 777                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 778                                I915_READ(ACTHD_I965));
 779                         I915_WRITE(IPEIR_I965, ipeir);
 780                         (void)I915_READ(IPEIR_I965);
 781                 }
 782                 if (eir & GM45_ERROR_PAGE_TABLE) {
 783                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 784                         printk(KERN_ERR "page table error\n");
 785                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 786                                pgtbl_err);
 787                         I915_WRITE(PGTBL_ER, pgtbl_err);
 788                         (void)I915_READ(PGTBL_ER);
 789                 }
 790         }
 791
 792         if (IS_I9XX(dev)) {
 793                 if (eir & I915_ERROR_PAGE_TABLE) {
 794                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 795                         printk(KERN_ERR "page table error\n");
 796                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 797                                pgtbl_err);
 798                         I915_WRITE(PGTBL_ER, pgtbl_err);
 799                         (void)I915_READ(PGTBL_ER);
 800                 }
 801         }
 802
 803         if (eir & I915_ERROR_MEMORY_REFRESH) {
 804                 u32 pipea_stats = I915_READ(PIPEASTAT);
 805                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 806
 807                 printk(KERN_ERR "memory refresh error\n");
 808                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 809                        pipea_stats);
 810                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 811                        pipeb_stats);
 812                 /* pipestat has already been acked */
 813         }
 814         if (eir & I915_ERROR_INSTRUCTION) {
 815                 printk(KERN_ERR "instruction error\n");
 816                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 817                        I915_READ(INSTPM));
 818                 if (!IS_I965G(dev)) {
 819                         u32 ipeir = I915_READ(IPEIR);
 820
 821                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 822                                I915_READ(IPEIR));
 823                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 824                                I915_READ(IPEHR));
 825                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 826                                I915_READ(INSTDONE));
 827                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 828                                I915_READ(ACTHD));
 829                         I915_WRITE(IPEIR, ipeir);
 830                         (void)I915_READ(IPEIR);
 831                 } else {
 832                         u32 ipeir = I915_READ(IPEIR_I965);
 833
 834                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 835                                I915_READ(IPEIR_I965));
 836                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 837                                I915_READ(IPEHR_I965));
 838                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 839                                I915_READ(INSTDONE_I965));
 840                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 841                                I915_READ(INSTPS));
 842                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 843                                I915_READ(INSTDONE1));
 844                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 845                                I915_READ(ACTHD_I965));
 846                         I915_WRITE(IPEIR_I965, ipeir);
 847                         (void)I915_READ(IPEIR_I965);
 848                 }
 849         }
 850
 851         I915_WRITE(EIR, eir);
 852         (void)I915_READ(EIR);
 853         eir = I915_READ(EIR);
 854         if (eir) {
 855                 /*
 856                  * some errors might have become stuck,
 857                  * mask them.
 858                  */
 859                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 860                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 861                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 862         }
 863 }
 864
 865 /**
 866  * i915_handle_error - handle an error interrupt
 867  * @dev: drm device
 868  *
 869  * Do some basic checking of regsiter state at error interrupt time and
 870  * dump it to the syslog.  Also call i915_capture_error_state() to make
 871  * sure we get a record and make it available in debugfs.  Fire a uevent
 872  * so userspace knows something bad happened (should trigger collection
 873  * of a ring dump etc.).
 874  */
 875 static void i915_handle_error(struct drm_device *dev, bool wedged)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878
 879         i915_capture_error_state(dev);
 880         i915_report_and_clear_eir(dev);
 881
 882         if (wedged) {
 883                 atomic_set(&dev_priv->mm.wedged, 1);
 884
 885                 /*
 886                  * Wakeup waiting processes so they don't hang
 887                  */
 888                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 889         }
 890
 891         queue_work(dev_priv->wq, &dev_priv->error_work);
 892 }
 893
 894 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 895 {
 896         struct drm_device *dev = (struct drm_device *) arg;
 897         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 898         struct drm_i915_master_private *master_priv;
 899         u32 iir, new_iir;
 900         u32 pipea_stats, pipeb_stats;
 901         u32 vblank_status;
 902         int vblank = 0;
 903         unsigned long irqflags;
 904         int irq_received;
 905         int ret = IRQ_NONE;
 906         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 907
 908         atomic_inc(&dev_priv->irq_received);
 909
 910         if (HAS_PCH_SPLIT(dev))
 911                 return ironlake_irq_handler(dev);
 912
 913         iir = I915_READ(IIR);
 914
 915         if (IS_I965G(dev))
 916                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 917         else
 918                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 919
 920         for (;;) {
 921                 irq_received = iir != 0;
 922
 923                 /* Can't rely on pipestat interrupt bit in iir as it might
 924                  * have been cleared after the pipestat interrupt was received.
 925                  * It doesn't set the bit in iir again, but it still produces
 926                  * interrupts (for non-MSI).
 927                  */
 928                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 929                 pipea_stats = I915_READ(PIPEASTAT);
 930                 pipeb_stats = I915_READ(PIPEBSTAT);
 931
 932                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 933                         i915_handle_error(dev, false);
 934
 935                 /*
 936                  * Clear the PIPE(A|B)STAT regs before the IIR
 937                  */
 938                 if (pipea_stats & 0x8000ffff) {
 939                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 940                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 941                         I915_WRITE(PIPEASTAT, pipea_stats);
 942                         irq_received = 1;
 943                 }
 944
 945                 if (pipeb_stats & 0x8000ffff) {
 946                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 947                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 948                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 949                         irq_received = 1;
 950                 }
 951                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 952
 953                 if (!irq_received)
 954                         break;
 955
 956                 ret = IRQ_HANDLED;
 957
 958                 /* Consume port.  Then clear IIR or we'll miss events */
 959                 if ((I915_HAS_HOTPLUG(dev)) &&
 960                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 961                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 962
 963                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 964                                   hotplug_status);
 965                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 966                                 queue_work(dev_priv->wq,
 967                                            &dev_priv->hotplug_work);
 968
 969                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 970                         I915_READ(PORT_HOTPLUG_STAT);
 971                 }
 972
 973                 I915_WRITE(IIR, iir);
 974                 new_iir = I915_READ(IIR); /* Flush posted writes */
 975
 976                 if (dev->primary->master) {
 977                         master_priv = dev->primary->master->driver_priv;
 978                         if (master_priv->sarea_priv)
 979                                 master_priv->sarea_priv->last_dispatch =
 980                                         READ_BREADCRUMB(dev_priv);
 981                 }
 982
 983                 if (iir & I915_USER_INTERRUPT) {
 984                         u32 seqno =
 985                                 render_ring->get_gem_seqno(dev, render_ring);
 986                         render_ring->irq_gem_seqno = seqno;
 987                         trace_i915_gem_request_complete(dev, seqno);
 988                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 989                         dev_priv->hangcheck_count = 0;
 990                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 991                 }
 992
 993                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
 994                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 995
 996                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
 997                         intel_prepare_page_flip(dev, 0);
 998                         if (dev_priv->flip_pending_is_done)
 999                                 intel_finish_page_flip_plane(dev, 0);
1000                 }
1001
1002                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1003                         intel_prepare_page_flip(dev, 1);
1004                         if (dev_priv->flip_pending_is_done)
1005                                 intel_finish_page_flip_plane(dev, 1);
1006                 }
1007
1008                 if (pipea_stats & vblank_status) {
1009                         vblank++;
1010                         drm_handle_vblank(dev, 0);
1011                         if (!dev_priv->flip_pending_is_done)
1012                                 intel_finish_page_flip(dev, 0);
1013                 }
1014
1015                 if (pipeb_stats & vblank_status) {
1016                         vblank++;
1017                         drm_handle_vblank(dev, 1);
1018                         if (!dev_priv->flip_pending_is_done)
1019                                 intel_finish_page_flip(dev, 1);
1020                 }
1021
1022                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1023                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1024                     (iir & I915_ASLE_INTERRUPT))
1025                         opregion_asle_intr(dev);
1026
1027                 /* With MSI, interrupts are only generated when iir
1028                  * transitions from zero to nonzero.  If another bit got
1029                  * set while we were handling the existing iir bits, then
1030                  * we would never get another interrupt.
1031                  *
1032                  * This is fine on non-MSI as well, as if we hit this path
1033                  * we avoid exiting the interrupt handler only to generate
1034                  * another one.
1035                  *
1036                  * Note that for MSI this could cause a stray interrupt report
1037                  * if an interrupt landed in the time between writing IIR and
1038                  * the posting read.  This should be rare enough to never
1039                  * trigger the 99% of 100,000 interrupts test for disabling
1040                  * stray interrupts.
1041                  */
1042                 iir = new_iir;
1043         }
1044
1045         return ret;
1046 }
1047
1048 static int i915_emit_irq(struct drm_device * dev)
1049 {
1050         drm_i915_private_t *dev_priv = dev->dev_private;
1051         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1052
1053         i915_kernel_lost_context(dev);
1054
1055         DRM_DEBUG_DRIVER("\n");
1056
1057         dev_priv->counter++;
1058         if (dev_priv->counter > 0x7FFFFFFFUL)
1059                 dev_priv->counter = 1;
1060         if (master_priv->sarea_priv)
1061                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1062
1063         BEGIN_LP_RING(4);
1064         OUT_RING(MI_STORE_DWORD_INDEX);
1065         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1066         OUT_RING(dev_priv->counter);
1067         OUT_RING(MI_USER_INTERRUPT);
1068         ADVANCE_LP_RING();
1069
1070         return dev_priv->counter;
1071 }
1072
1073 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1074 {
1075         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1076         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1077
1078         if (dev_priv->trace_irq_seqno == 0)
1079                 render_ring->user_irq_get(dev, render_ring);
1080
1081         dev_priv->trace_irq_seqno = seqno;
1082 }
1083
1084 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1085 {
1086         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1087         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1088         int ret = 0;
1089         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1090
1091         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1092                   READ_BREADCRUMB(dev_priv));
1093
1094         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1095                 if (master_priv->sarea_priv)
1096                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1097                 return 0;
1098         }
1099
1100         if (master_priv->sarea_priv)
1101                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1102
1103         render_ring->user_irq_get(dev, render_ring);
1104         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1105                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1106         render_ring->user_irq_put(dev, render_ring);
1107
1108         if (ret == -EBUSY) {
1109                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1110                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1111         }
1112
1113         return ret;
1114 }
1115
1116 /* Needs the lock as it touches the ring.
1117  */
1118 int i915_irq_emit(struct drm_device *dev, void *data,
1119                          struct drm_file *file_priv)
1120 {
1121         drm_i915_private_t *dev_priv = dev->dev_private;
1122         drm_i915_irq_emit_t *emit = data;
1123         int result;
1124
1125         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1126                 DRM_ERROR("called with no initialization\n");
1127                 return -EINVAL;
1128         }
1129
1130         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1131
1132         mutex_lock(&dev->struct_mutex);
1133         result = i915_emit_irq(dev);
1134         mutex_unlock(&dev->struct_mutex);
1135
1136         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1137                 DRM_ERROR("copy_to_user\n");
1138                 return -EFAULT;
1139         }
1140
1141         return 0;
1142 }
1143
1144 /* Doesn't need the hardware lock.
1145  */
1146 int i915_irq_wait(struct drm_device *dev, void *data,
1147                          struct drm_file *file_priv)
1148 {
1149         drm_i915_private_t *dev_priv = dev->dev_private;
1150         drm_i915_irq_wait_t *irqwait = data;
1151
1152         if (!dev_priv) {
1153                 DRM_ERROR("called with no initialization\n");
1154                 return -EINVAL;
1155         }
1156
1157         return i915_wait_irq(dev, irqwait->irq_seq);
1158 }
1159
1160 /* Called from drm generic code, passed 'crtc' which
1161  * we use as a pipe index
1162  */
1163 int i915_enable_vblank(struct drm_device *dev, int pipe)
1164 {
1165         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1166         unsigned long irqflags;
1167         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1168         u32 pipeconf;
1169
1170         pipeconf = I915_READ(pipeconf_reg);
1171         if (!(pipeconf & PIPEACONF_ENABLE))
1172                 return -EINVAL;
1173
1174         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1175         if (HAS_PCH_SPLIT(dev))
1176                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1177                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1178         else if (IS_I965G(dev))
1179                 i915_enable_pipestat(dev_priv, pipe,
1180                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1181         else
1182                 i915_enable_pipestat(dev_priv, pipe,
1183                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1184         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1185         return 0;
1186 }
1187
1188 /* Called from drm generic code, passed 'crtc' which
1189  * we use as a pipe index
1190  */
1191 void i915_disable_vblank(struct drm_device *dev, int pipe)
1192 {
1193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1194         unsigned long irqflags;
1195
1196         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1197         if (HAS_PCH_SPLIT(dev))
1198                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1199                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1200         else
1201                 i915_disable_pipestat(dev_priv, pipe,
1202                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1203                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1204         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1205 }
1206
1207 void i915_enable_interrupt (struct drm_device *dev)
1208 {
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210
1211         if (!HAS_PCH_SPLIT(dev))
1212                 opregion_enable_asle(dev);
1213         dev_priv->irq_enabled = 1;
1214 }
1215
1216
1217 /* Set the vblank monitor pipe
1218  */
1219 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1220                          struct drm_file *file_priv)
1221 {
1222         drm_i915_private_t *dev_priv = dev->dev_private;
1223
1224         if (!dev_priv) {
1225                 DRM_ERROR("called with no initialization\n");
1226                 return -EINVAL;
1227         }
1228
1229         return 0;
1230 }
1231
1232 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1233                          struct drm_file *file_priv)
1234 {
1235         drm_i915_private_t *dev_priv = dev->dev_private;
1236         drm_i915_vblank_pipe_t *pipe = data;
1237
1238         if (!dev_priv) {
1239                 DRM_ERROR("called with no initialization\n");
1240                 return -EINVAL;
1241         }
1242
1243         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1244
1245         return 0;
1246 }
1247
1248 /**
1249  * Schedule buffer swap at given vertical blank.
1250  */
1251 int i915_vblank_swap(struct drm_device *dev, void *data,
1252                      struct drm_file *file_priv)
1253 {
1254         /* The delayed swap mechanism was fundamentally racy, and has been
1255          * removed.  The model was that the client requested a delayed flip/swap
1256          * from the kernel, then waited for vblank before continuing to perform
1257          * rendering.  The problem was that the kernel might wake the client
1258          * up before it dispatched the vblank swap (since the lock has to be
1259          * held while touching the ringbuffer), in which case the client would
1260          * clear and start the next frame before the swap occurred, and
1261          * flicker would occur in addition to likely missing the vblank.
1262          *
1263          * In the absence of this ioctl, userland falls back to a correct path
1264          * of waiting for a vblank, then dispatching the swap on its own.
1265          * Context switching to userland and back is plenty fast enough for
1266          * meeting the requirements of vblank swapping.
1267          */
1268         return -EINVAL;
1269 }
1270
1271 struct drm_i915_gem_request *
1272 i915_get_tail_request(struct drm_device *dev)
1273 {
1274         drm_i915_private_t *dev_priv = dev->dev_private;
1275         return list_entry(dev_priv->render_ring.request_list.prev,
1276                         struct drm_i915_gem_request, list);
1277 }
1278
1279 /**
1280  * This is called when the chip hasn't reported back with completed
1281  * batchbuffers in a long time. The first time this is called we simply record
1282  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1283  * again, we assume the chip is wedged and try to fix it.
1284  */
1285 void i915_hangcheck_elapsed(unsigned long data)
1286 {
1287         struct drm_device *dev = (struct drm_device *)data;
1288         drm_i915_private_t *dev_priv = dev->dev_private;
1289         uint32_t acthd, instdone, instdone1;
1290
1291         /* No reset support on this chip yet. */
1292         if (IS_GEN6(dev))
1293                 return;
1294
1295         if (!IS_I965G(dev)) {
1296                 acthd = I915_READ(ACTHD);
1297                 instdone = I915_READ(INSTDONE);
1298                 instdone1 = 0;
1299         } else {
1300                 acthd = I915_READ(ACTHD_I965);
1301                 instdone = I915_READ(INSTDONE_I965);
1302                 instdone1 = I915_READ(INSTDONE1);
1303         }
1304
1305         /* If all work is done then ACTHD clearly hasn't advanced. */
1306         if (list_empty(&dev_priv->render_ring.request_list) ||
1307                 i915_seqno_passed(i915_get_gem_seqno(dev,
1308                                 &dev_priv->render_ring),
1309                         i915_get_tail_request(dev)->seqno)) {
1310                 dev_priv->hangcheck_count = 0;
1311
1312                 /* Issue a wake-up to catch stuck h/w. */
1313                 if (dev_priv->render_ring.waiting_gem_seqno |
1314                     dev_priv->bsd_ring.waiting_gem_seqno) {
1315                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1316                         if (dev_priv->render_ring.waiting_gem_seqno)
1317                                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1318                         if (dev_priv->bsd_ring.waiting_gem_seqno)
1319                                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1320                 }
1321                 return;
1322         }
1323
1324         if (dev_priv->last_acthd == acthd &&
1325             dev_priv->last_instdone == instdone &&
1326             dev_priv->last_instdone1 == instdone1) {
1327                 if (dev_priv->hangcheck_count++ > 1) {
1328                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1329                         i915_handle_error(dev, true);
1330                         return;
1331                 }
1332         } else {
1333                 dev_priv->hangcheck_count = 0;
1334
1335                 dev_priv->last_acthd = acthd;
1336                 dev_priv->last_instdone = instdone;
1337                 dev_priv->last_instdone1 = instdone1;
1338         }
1339
1340         /* Reset timer case chip hangs without another request being added */
1341         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1342 }
1343
1344 /* drm_dma.h hooks
1345 */
1346 static void ironlake_irq_preinstall(struct drm_device *dev)
1347 {
1348         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1349
1350         I915_WRITE(HWSTAM, 0xeffe);
1351
1352         /* XXX hotplug from PCH */
1353
1354         I915_WRITE(DEIMR, 0xffffffff);
1355         I915_WRITE(DEIER, 0x0);
1356         (void) I915_READ(DEIER);
1357
1358         /* and GT */
1359         I915_WRITE(GTIMR, 0xffffffff);
1360         I915_WRITE(GTIER, 0x0);
1361         (void) I915_READ(GTIER);
1362
1363         /* south display irq */
1364         I915_WRITE(SDEIMR, 0xffffffff);
1365         I915_WRITE(SDEIER, 0x0);
1366         (void) I915_READ(SDEIER);
1367 }
1368
1369 static int ironlake_irq_postinstall(struct drm_device *dev)
1370 {
1371         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1372         /* enable kind of interrupts always enabled */
1373         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1374                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1375         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1376         u32 hotplug_mask;
1377
1378         dev_priv->irq_mask_reg = ~display_mask;
1379         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1380
1381         /* should always can generate irq */
1382         I915_WRITE(DEIIR, I915_READ(DEIIR));
1383         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1384         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1385         (void) I915_READ(DEIER);
1386
1387         /* Gen6 only needs render pipe_control now */
1388         if (IS_GEN6(dev))
1389                 render_mask = GT_PIPE_NOTIFY;
1390
1391         dev_priv->gt_irq_mask_reg = ~render_mask;
1392         dev_priv->gt_irq_enable_reg = render_mask;
1393
1394         I915_WRITE(GTIIR, I915_READ(GTIIR));
1395         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1396         if (IS_GEN6(dev))
1397                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1398         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1399         (void) I915_READ(GTIER);
1400
1401         if (HAS_PCH_CPT(dev)) {
1402                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1403                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1404         } else {
1405                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1406                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1407         }
1408
1409         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1410         dev_priv->pch_irq_enable_reg = hotplug_mask;
1411
1412         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1413         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1414         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1415         (void) I915_READ(SDEIER);
1416
1417         if (IS_IRONLAKE_M(dev)) {
1418                 /* Clear & enable PCU event interrupts */
1419                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1420                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1421                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1422         }
1423
1424         return 0;
1425 }
1426
1427 void i915_driver_irq_preinstall(struct drm_device * dev)
1428 {
1429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1430
1431         atomic_set(&dev_priv->irq_received, 0);
1432
1433         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1434         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1435
1436         if (HAS_PCH_SPLIT(dev)) {
1437                 ironlake_irq_preinstall(dev);
1438                 return;
1439         }
1440
1441         if (I915_HAS_HOTPLUG(dev)) {
1442                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1443                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1444         }
1445
1446         I915_WRITE(HWSTAM, 0xeffe);
1447         I915_WRITE(PIPEASTAT, 0);
1448         I915_WRITE(PIPEBSTAT, 0);
1449         I915_WRITE(IMR, 0xffffffff);
1450         I915_WRITE(IER, 0x0);
1451         (void) I915_READ(IER);
1452 }
1453
1454 /*
1455  * Must be called after intel_modeset_init or hotplug interrupts won't be
1456  * enabled correctly.
1457  */
1458 int i915_driver_irq_postinstall(struct drm_device *dev)
1459 {
1460         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1461         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1462         u32 error_mask;
1463
1464         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1465
1466         if (HAS_BSD(dev))
1467                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1468
1469         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1470
1471         if (HAS_PCH_SPLIT(dev))
1472                 return ironlake_irq_postinstall(dev);
1473
1474         /* Unmask the interrupts that we always want on. */
1475         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1476
1477         dev_priv->pipestat[0] = 0;
1478         dev_priv->pipestat[1] = 0;
1479
1480         if (I915_HAS_HOTPLUG(dev)) {
1481                 /* Enable in IER... */
1482                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1483                 /* and unmask in IMR */
1484                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1485         }
1486
1487         /*
1488          * Enable some error detection, note the instruction error mask
1489          * bit is reserved, so we leave it masked.
1490          */
1491         if (IS_G4X(dev)) {
1492                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1493                                GM45_ERROR_MEM_PRIV |
1494                                GM45_ERROR_CP_PRIV |
1495                                I915_ERROR_MEMORY_REFRESH);
1496         } else {
1497                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1498                                I915_ERROR_MEMORY_REFRESH);
1499         }
1500         I915_WRITE(EMR, error_mask);
1501
1502         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1503         I915_WRITE(IER, enable_mask);
1504         (void) I915_READ(IER);
1505
1506         if (I915_HAS_HOTPLUG(dev)) {
1507                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1508
1509                 /* Note HDMI and DP share bits */
1510                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1511                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1512                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1513                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1514                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1515                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1516                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1517                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1518                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1519                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1520                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1521                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1522
1523                         /* Programming the CRT detection parameters tends
1524                            to generate a spurious hotplug event about three
1525                            seconds later.  So just do it once.
1526                         */
1527                         if (IS_G4X(dev))
1528                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1529                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1530                 }
1531
1532                 /* Ignore TV since it's buggy */
1533
1534                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1535         }
1536
1537         opregion_enable_asle(dev);
1538
1539         return 0;
1540 }
1541
1542 static void ironlake_irq_uninstall(struct drm_device *dev)
1543 {
1544         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1545         I915_WRITE(HWSTAM, 0xffffffff);
1546
1547         I915_WRITE(DEIMR, 0xffffffff);
1548         I915_WRITE(DEIER, 0x0);
1549         I915_WRITE(DEIIR, I915_READ(DEIIR));
1550
1551         I915_WRITE(GTIMR, 0xffffffff);
1552         I915_WRITE(GTIER, 0x0);
1553         I915_WRITE(GTIIR, I915_READ(GTIIR));
1554 }
1555
1556 void i915_driver_irq_uninstall(struct drm_device * dev)
1557 {
1558         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1559
1560         if (!dev_priv)
1561                 return;
1562
1563         dev_priv->vblank_pipe = 0;
1564
1565         if (HAS_PCH_SPLIT(dev)) {
1566                 ironlake_irq_uninstall(dev);
1567                 return;
1568         }
1569
1570         if (I915_HAS_HOTPLUG(dev)) {
1571                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1572                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1573         }
1574
1575         I915_WRITE(HWSTAM, 0xffffffff);
1576         I915_WRITE(PIPEASTAT, 0);
1577         I915_WRITE(PIPEBSTAT, 0);
1578         I915_WRITE(IMR, 0xffffffff);
1579         I915_WRITE(IER, 0x0);
1580
1581         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1582         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1583         I915_WRITE(IIR, I915_READ(IIR));
1584 }