arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  73         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  74 #define KVM_GUEST_CR0_MASK                                              \
  75         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  77         (X86_CR0_WP | X86_CR0_NE)
  78 #define KVM_VM_CR0_ALWAYS_ON                                            \
  79         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  80 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  81         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  82          | X86_CR4_OSXMMEXCPT)
  83
  84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  86
  87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  88
  89 /*
  90  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  91  * ple_gap:    upper bound on the amount of time between two successive
  92  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  93  *             According to test, this time is usually small than 41 cycles.
  94  * ple_window: upper bound on the amount of time a guest is allowed to execute
  95  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  96  *             less than 2^12 cycles
  97  * Time is measured based on a counter that runs at the same rate as the TSC,
  98  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  99  */
 100 #define KVM_VMX_DEFAULT_PLE_GAP    41
 101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 103 module_param(ple_gap, int, S_IRUGO);
 104
 105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 106 module_param(ple_window, int, S_IRUGO);
 107
 108 #define NR_AUTOLOAD_MSRS 1
 109
 110 struct vmcs {
 111         u32 revision_id;
 112         u32 abort;
 113         char data[0];
 114 };
 115
 116 struct shared_msr_entry {
 117         unsigned index;
 118         u64 data;
 119         u64 mask;
 120 };
 121
 122 struct vcpu_vmx {
 123         struct kvm_vcpu       vcpu;
 124         struct list_head      local_vcpus_link;
 125         unsigned long         host_rsp;
 126         int                   launched;
 127         u8                    fail;
 128         u32                   idt_vectoring_info;
 129         struct shared_msr_entry *guest_msrs;
 130         int                   nmsrs;
 131         int                   save_nmsrs;
 132 #ifdef CONFIG_X86_64
 133         u64                   msr_host_kernel_gs_base;
 134         u64                   msr_guest_kernel_gs_base;
 135 #endif
 136         struct vmcs          *vmcs;
 137         struct msr_autoload {
 138                 unsigned nr;
 139                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 140                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 141         } msr_autoload;
 142         struct {
 143                 int           loaded;
 144                 u16           fs_sel, gs_sel, ldt_sel;
 145                 int           gs_ldt_reload_needed;
 146                 int           fs_reload_needed;
 147         } host_state;
 148         struct {
 149                 int vm86_active;
 150                 ulong save_rflags;
 151                 struct kvm_save_segment {
 152                         u16 selector;
 153                         unsigned long base;
 154                         u32 limit;
 155                         u32 ar;
 156                 } tr, es, ds, fs, gs;
 157                 struct {
 158                         bool pending;
 159                         u8 vector;
 160                         unsigned rip;
 161                 } irq;
 162         } rmode;
 163         int vpid;
 164         bool emulation_required;
 165
 166         /* Support for vnmi-less CPUs */
 167         int soft_vnmi_blocked;
 168         ktime_t entry_time;
 169         s64 vnmi_blocked_time;
 170         u32 exit_reason;
 171
 172         bool rdtscp_enabled;
 173 };
 174
 175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 176 {
 177         return container_of(vcpu, struct vcpu_vmx, vcpu);
 178 }
 179
 180 static int init_rmode(struct kvm *kvm);
 181 static u64 construct_eptp(unsigned long root_hpa);
 182 static void kvm_cpu_vmxon(u64 addr);
 183 static void kvm_cpu_vmxoff(void);
 184
 185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 189
 190 static unsigned long *vmx_io_bitmap_a;
 191 static unsigned long *vmx_io_bitmap_b;
 192 static unsigned long *vmx_msr_bitmap_legacy;
 193 static unsigned long *vmx_msr_bitmap_longmode;
 194
 195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 196 static DEFINE_SPINLOCK(vmx_vpid_lock);
 197
 198 static struct vmcs_config {
 199         int size;
 200         int order;
 201         u32 revision_id;
 202         u32 pin_based_exec_ctrl;
 203         u32 cpu_based_exec_ctrl;
 204         u32 cpu_based_2nd_exec_ctrl;
 205         u32 vmexit_ctrl;
 206         u32 vmentry_ctrl;
 207 } vmcs_config;
 208
 209 static struct vmx_capability {
 210         u32 ept;
 211         u32 vpid;
 212 } vmx_capability;
 213
 214 #define VMX_SEGMENT_FIELD(seg)                                  \
 215         [VCPU_SREG_##seg] = {                                   \
 216                 .selector = GUEST_##seg##_SELECTOR,             \
 217                 .base = GUEST_##seg##_BASE,                     \
 218                 .limit = GUEST_##seg##_LIMIT,                   \
 219                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 220         }
 221
 222 static struct kvm_vmx_segment_field {
 223         unsigned selector;
 224         unsigned base;
 225         unsigned limit;
 226         unsigned ar_bytes;
 227 } kvm_vmx_segment_fields[] = {
 228         VMX_SEGMENT_FIELD(CS),
 229         VMX_SEGMENT_FIELD(DS),
 230         VMX_SEGMENT_FIELD(ES),
 231         VMX_SEGMENT_FIELD(FS),
 232         VMX_SEGMENT_FIELD(GS),
 233         VMX_SEGMENT_FIELD(SS),
 234         VMX_SEGMENT_FIELD(TR),
 235         VMX_SEGMENT_FIELD(LDTR),
 236 };
 237
 238 static u64 host_efer;
 239
 240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 241
 242 /*
 243  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 244  * away by decrementing the array size.
 245  */
 246 static const u32 vmx_msr_index[] = {
 247 #ifdef CONFIG_X86_64
 248         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 249 #endif
 250         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 251 };
 252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 253
 254 static inline bool is_page_fault(u32 intr_info)
 255 {
 256         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 257                              INTR_INFO_VALID_MASK)) ==
 258                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline bool is_no_device(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline bool is_invalid_opcode(u32 intr_info)
 269 {
 270         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 271                              INTR_INFO_VALID_MASK)) ==
 272                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 273 }
 274
 275 static inline bool is_external_interrupt(u32 intr_info)
 276 {
 277         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 278                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 279 }
 280
 281 static inline bool is_machine_check(u32 intr_info)
 282 {
 283         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 284                              INTR_INFO_VALID_MASK)) ==
 285                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 286 }
 287
 288 static inline bool cpu_has_vmx_msr_bitmap(void)
 289 {
 290         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 291 }
 292
 293 static inline bool cpu_has_vmx_tpr_shadow(void)
 294 {
 295         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 296 }
 297
 298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 299 {
 300         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 301 }
 302
 303 static inline bool cpu_has_secondary_exec_ctrls(void)
 304 {
 305         return vmcs_config.cpu_based_exec_ctrl &
 306                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 307 }
 308
 309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 310 {
 311         return vmcs_config.cpu_based_2nd_exec_ctrl &
 312                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 313 }
 314
 315 static inline bool cpu_has_vmx_flexpriority(void)
 316 {
 317         return cpu_has_vmx_tpr_shadow() &&
 318                 cpu_has_vmx_virtualize_apic_accesses();
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_execute_only(void)
 322 {
 323         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 324 }
 325
 326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 327 {
 328         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 329 }
 330
 331 static inline bool cpu_has_vmx_eptp_writeback(void)
 332 {
 333         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 334 }
 335
 336 static inline bool cpu_has_vmx_ept_2m_page(void)
 337 {
 338         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 339 }
 340
 341 static inline bool cpu_has_vmx_ept_1g_page(void)
 342 {
 343         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 344 }
 345
 346 static inline bool cpu_has_vmx_ept_4levels(void)
 347 {
 348         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 349 }
 350
 351 static inline bool cpu_has_vmx_invept_individual_addr(void)
 352 {
 353         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 354 }
 355
 356 static inline bool cpu_has_vmx_invept_context(void)
 357 {
 358         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 359 }
 360
 361 static inline bool cpu_has_vmx_invept_global(void)
 362 {
 363         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 364 }
 365
 366 static inline bool cpu_has_vmx_invvpid_single(void)
 367 {
 368         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 369 }
 370
 371 static inline bool cpu_has_vmx_invvpid_global(void)
 372 {
 373         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 374 }
 375
 376 static inline bool cpu_has_vmx_ept(void)
 377 {
 378         return vmcs_config.cpu_based_2nd_exec_ctrl &
 379                 SECONDARY_EXEC_ENABLE_EPT;
 380 }
 381
 382 static inline bool cpu_has_vmx_unrestricted_guest(void)
 383 {
 384         return vmcs_config.cpu_based_2nd_exec_ctrl &
 385                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 386 }
 387
 388 static inline bool cpu_has_vmx_ple(void)
 389 {
 390         return vmcs_config.cpu_based_2nd_exec_ctrl &
 391                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 392 }
 393
 394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 395 {
 396         return flexpriority_enabled && irqchip_in_kernel(kvm);
 397 }
 398
 399 static inline bool cpu_has_vmx_vpid(void)
 400 {
 401         return vmcs_config.cpu_based_2nd_exec_ctrl &
 402                 SECONDARY_EXEC_ENABLE_VPID;
 403 }
 404
 405 static inline bool cpu_has_vmx_rdtscp(void)
 406 {
 407         return vmcs_config.cpu_based_2nd_exec_ctrl &
 408                 SECONDARY_EXEC_RDTSCP;
 409 }
 410
 411 static inline bool cpu_has_virtual_nmis(void)
 412 {
 413         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 414 }
 415
 416 static inline bool cpu_has_vmx_wbinvd_exit(void)
 417 {
 418         return vmcs_config.cpu_based_2nd_exec_ctrl &
 419                 SECONDARY_EXEC_WBINVD_EXITING;
 420 }
 421
 422 static inline bool report_flexpriority(void)
 423 {
 424         return flexpriority_enabled;
 425 }
 426
 427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 428 {
 429         int i;
 430
 431         for (i = 0; i < vmx->nmsrs; ++i)
 432                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 433                         return i;
 434         return -1;
 435 }
 436
 437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 438 {
 439     struct {
 440         u64 vpid : 16;
 441         u64 rsvd : 48;
 442         u64 gva;
 443     } operand = { vpid, 0, gva };
 444
 445     asm volatile (__ex(ASM_VMX_INVVPID)
 446                   /* CF==1 or ZF==1 --> rc = -1 */
 447                   "; ja 1f ; ud2 ; 1:"
 448                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 449 }
 450
 451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 452 {
 453         struct {
 454                 u64 eptp, gpa;
 455         } operand = {eptp, gpa};
 456
 457         asm volatile (__ex(ASM_VMX_INVEPT)
 458                         /* CF==1 or ZF==1 --> rc = -1 */
 459                         "; ja 1f ; ud2 ; 1:\n"
 460                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 461 }
 462
 463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 464 {
 465         int i;
 466
 467         i = __find_msr_index(vmx, msr);
 468         if (i >= 0)
 469                 return &vmx->guest_msrs[i];
 470         return NULL;
 471 }
 472
 473 static void vmcs_clear(struct vmcs *vmcs)
 474 {
 475         u64 phys_addr = __pa(vmcs);
 476         u8 error;
 477
 478         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 479                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 480                       : "cc", "memory");
 481         if (error)
 482                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 483                        vmcs, phys_addr);
 484 }
 485
 486 static void vmcs_load(struct vmcs *vmcs)
 487 {
 488         u64 phys_addr = __pa(vmcs);
 489         u8 error;
 490
 491         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 492                         : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 493                         : "cc", "memory");
 494         if (error)
 495                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 496                        vmcs, phys_addr);
 497 }
 498
 499 static void __vcpu_clear(void *arg)
 500 {
 501         struct vcpu_vmx *vmx = arg;
 502         int cpu = raw_smp_processor_id();
 503
 504         if (vmx->vcpu.cpu == cpu)
 505                 vmcs_clear(vmx->vmcs);
 506         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 507                 per_cpu(current_vmcs, cpu) = NULL;
 508         rdtscll(vmx->vcpu.arch.host_tsc);
 509         list_del(&vmx->local_vcpus_link);
 510         vmx->vcpu.cpu = -1;
 511         vmx->launched = 0;
 512 }
 513
 514 static void vcpu_clear(struct vcpu_vmx *vmx)
 515 {
 516         if (vmx->vcpu.cpu == -1)
 517                 return;
 518         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 519 }
 520
 521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 522 {
 523         if (vmx->vpid == 0)
 524                 return;
 525
 526         if (cpu_has_vmx_invvpid_single())
 527                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 528 }
 529
 530 static inline void vpid_sync_vcpu_global(void)
 531 {
 532         if (cpu_has_vmx_invvpid_global())
 533                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 534 }
 535
 536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 537 {
 538         if (cpu_has_vmx_invvpid_single())
 539                 vpid_sync_vcpu_single(vmx);
 540         else
 541                 vpid_sync_vcpu_global();
 542 }
 543
 544 static inline void ept_sync_global(void)
 545 {
 546         if (cpu_has_vmx_invept_global())
 547                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 548 }
 549
 550 static inline void ept_sync_context(u64 eptp)
 551 {
 552         if (enable_ept) {
 553                 if (cpu_has_vmx_invept_context())
 554                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 555                 else
 556                         ept_sync_global();
 557         }
 558 }
 559
 560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 561 {
 562         if (enable_ept) {
 563                 if (cpu_has_vmx_invept_individual_addr())
 564                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 565                                         eptp, gpa);
 566                 else
 567                         ept_sync_context(eptp);
 568         }
 569 }
 570
 571 static unsigned long vmcs_readl(unsigned long field)
 572 {
 573         unsigned long value;
 574
 575         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 576                       : "=a"(value) : "d"(field) : "cc");
 577         return value;
 578 }
 579
 580 static u16 vmcs_read16(unsigned long field)
 581 {
 582         return vmcs_readl(field);
 583 }
 584
 585 static u32 vmcs_read32(unsigned long field)
 586 {
 587         return vmcs_readl(field);
 588 }
 589
 590 static u64 vmcs_read64(unsigned long field)
 591 {
 592 #ifdef CONFIG_X86_64
 593         return vmcs_readl(field);
 594 #else
 595         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 596 #endif
 597 }
 598
 599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 600 {
 601         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 602                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 603         dump_stack();
 604 }
 605
 606 static void vmcs_writel(unsigned long field, unsigned long value)
 607 {
 608         u8 error;
 609
 610         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 611                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 612         if (unlikely(error))
 613                 vmwrite_error(field, value);
 614 }
 615
 616 static void vmcs_write16(unsigned long field, u16 value)
 617 {
 618         vmcs_writel(field, value);
 619 }
 620
 621 static void vmcs_write32(unsigned long field, u32 value)
 622 {
 623         vmcs_writel(field, value);
 624 }
 625
 626 static void vmcs_write64(unsigned long field, u64 value)
 627 {
 628         vmcs_writel(field, value);
 629 #ifndef CONFIG_X86_64
 630         asm volatile ("");
 631         vmcs_writel(field+1, value >> 32);
 632 #endif
 633 }
 634
 635 static void vmcs_clear_bits(unsigned long field, u32 mask)
 636 {
 637         vmcs_writel(field, vmcs_readl(field) & ~mask);
 638 }
 639
 640 static void vmcs_set_bits(unsigned long field, u32 mask)
 641 {
 642         vmcs_writel(field, vmcs_readl(field) | mask);
 643 }
 644
 645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 646 {
 647         u32 eb;
 648
 649         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 650              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 651         if ((vcpu->guest_debug &
 652              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 653             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 654                 eb |= 1u << BP_VECTOR;
 655         if (to_vmx(vcpu)->rmode.vm86_active)
 656                 eb = ~0;
 657         if (enable_ept)
 658                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 659         if (vcpu->fpu_active)
 660                 eb &= ~(1u << NM_VECTOR);
 661         vmcs_write32(EXCEPTION_BITMAP, eb);
 662 }
 663
 664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 665 {
 666         unsigned i;
 667         struct msr_autoload *m = &vmx->msr_autoload;
 668
 669         for (i = 0; i < m->nr; ++i)
 670                 if (m->guest[i].index == msr)
 671                         break;
 672
 673         if (i == m->nr)
 674                 return;
 675         --m->nr;
 676         m->guest[i] = m->guest[m->nr];
 677         m->host[i] = m->host[m->nr];
 678         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 679         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 680 }
 681
 682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 683                                   u64 guest_val, u64 host_val)
 684 {
 685         unsigned i;
 686         struct msr_autoload *m = &vmx->msr_autoload;
 687
 688         for (i = 0; i < m->nr; ++i)
 689                 if (m->guest[i].index == msr)
 690                         break;
 691
 692         if (i == m->nr) {
 693                 ++m->nr;
 694                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 695                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 696         }
 697
 698         m->guest[i].index = msr;
 699         m->guest[i].value = guest_val;
 700         m->host[i].index = msr;
 701         m->host[i].value = host_val;
 702 }
 703
 704 static void reload_tss(void)
 705 {
 706         /*
 707          * VT restores TR but not its size.  Useless.
 708          */
 709         struct desc_ptr gdt;
 710         struct desc_struct *descs;
 711
 712         native_store_gdt(&gdt);
 713         descs = (void *)gdt.address;
 714         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 715         load_TR_desc();
 716 }
 717
 718 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 719 {
 720         u64 guest_efer;
 721         u64 ignore_bits;
 722
 723         guest_efer = vmx->vcpu.arch.efer;
 724
 725         /*
 726          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 727          * outside long mode
 728          */
 729         ignore_bits = EFER_NX | EFER_SCE;
 730 #ifdef CONFIG_X86_64
 731         ignore_bits |= EFER_LMA | EFER_LME;
 732         /* SCE is meaningful only in long mode on Intel */
 733         if (guest_efer & EFER_LMA)
 734                 ignore_bits &= ~(u64)EFER_SCE;
 735 #endif
 736         guest_efer &= ~ignore_bits;
 737         guest_efer |= host_efer & ignore_bits;
 738         vmx->guest_msrs[efer_offset].data = guest_efer;
 739         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 740
 741         clear_atomic_switch_msr(vmx, MSR_EFER);
 742         /* On ept, can't emulate nx, and must switch nx atomically */
 743         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 744                 guest_efer = vmx->vcpu.arch.efer;
 745                 if (!(guest_efer & EFER_LMA))
 746                         guest_efer &= ~EFER_LME;
 747                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 748                 return false;
 749         }
 750
 751         return true;
 752 }
 753
 754 static unsigned long segment_base(u16 selector)
 755 {
 756         struct desc_ptr gdt;
 757         struct desc_struct *d;
 758         unsigned long table_base;
 759         unsigned long v;
 760
 761         if (!(selector & ~3))
 762                 return 0;
 763
 764         native_store_gdt(&gdt);
 765         table_base = gdt.address;
 766
 767         if (selector & 4) {           /* from ldt */
 768                 u16 ldt_selector = kvm_read_ldt();
 769
 770                 if (!(ldt_selector & ~3))
 771                         return 0;
 772
 773                 table_base = segment_base(ldt_selector);
 774         }
 775         d = (struct desc_struct *)(table_base + (selector & ~7));
 776         v = get_desc_base(d);
 777 #ifdef CONFIG_X86_64
 778        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 779                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 780 #endif
 781         return v;
 782 }
 783
 784 static inline unsigned long kvm_read_tr_base(void)
 785 {
 786         u16 tr;
 787         asm("str %0" : "=g"(tr));
 788         return segment_base(tr);
 789 }
 790
 791 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 792 {
 793         struct vcpu_vmx *vmx = to_vmx(vcpu);
 794         int i;
 795
 796         if (vmx->host_state.loaded)
 797                 return;
 798
 799         vmx->host_state.loaded = 1;
 800         /*
 801          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 802          * allow segment selectors with cpl > 0 or ti == 1.
 803          */
 804         vmx->host_state.ldt_sel = kvm_read_ldt();
 805         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 806         savesegment(fs, vmx->host_state.fs_sel);
 807         if (!(vmx->host_state.fs_sel & 7)) {
 808                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 809                 vmx->host_state.fs_reload_needed = 0;
 810         } else {
 811                 vmcs_write16(HOST_FS_SELECTOR, 0);
 812                 vmx->host_state.fs_reload_needed = 1;
 813         }
 814         savesegment(gs, vmx->host_state.gs_sel);
 815         if (!(vmx->host_state.gs_sel & 7))
 816                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 817         else {
 818                 vmcs_write16(HOST_GS_SELECTOR, 0);
 819                 vmx->host_state.gs_ldt_reload_needed = 1;
 820         }
 821
 822 #ifdef CONFIG_X86_64
 823         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 824         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 825 #else
 826         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 827         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 828 #endif
 829
 830 #ifdef CONFIG_X86_64
 831         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 832         if (is_long_mode(&vmx->vcpu))
 833                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 834 #endif
 835         for (i = 0; i < vmx->save_nmsrs; ++i)
 836                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 837                                    vmx->guest_msrs[i].data,
 838                                    vmx->guest_msrs[i].mask);
 839 }
 840
 841 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 842 {
 843         if (!vmx->host_state.loaded)
 844                 return;
 845
 846         ++vmx->vcpu.stat.host_state_reload;
 847         vmx->host_state.loaded = 0;
 848 #ifdef CONFIG_X86_64
 849         if (is_long_mode(&vmx->vcpu))
 850                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 851 #endif
 852         if (vmx->host_state.gs_ldt_reload_needed) {
 853                 kvm_load_ldt(vmx->host_state.ldt_sel);
 854 #ifdef CONFIG_X86_64
 855                 load_gs_index(vmx->host_state.gs_sel);
 856 #else
 857                 loadsegment(gs, vmx->host_state.gs_sel);
 858 #endif
 859         }
 860         if (vmx->host_state.fs_reload_needed)
 861                 loadsegment(fs, vmx->host_state.fs_sel);
 862         reload_tss();
 863 #ifdef CONFIG_X86_64
 864         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 865 #endif
 866         if (current_thread_info()->status & TS_USEDFPU)
 867                 clts();
 868         load_gdt(&__get_cpu_var(host_gdt));
 869 }
 870
 871 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 872 {
 873         preempt_disable();
 874         __vmx_load_host_state(vmx);
 875         preempt_enable();
 876 }
 877
 878 /*
 879  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 880  * vcpu mutex is already taken.
 881  */
 882 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 883 {
 884         struct vcpu_vmx *vmx = to_vmx(vcpu);
 885         u64 tsc_this, delta, new_offset;
 886         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 887
 888         if (!vmm_exclusive)
 889                 kvm_cpu_vmxon(phys_addr);
 890         else if (vcpu->cpu != cpu)
 891                 vcpu_clear(vmx);
 892
 893         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 894                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 895                 vmcs_load(vmx->vmcs);
 896         }
 897
 898         if (vcpu->cpu != cpu) {
 899                 struct desc_ptr dt;
 900                 unsigned long sysenter_esp;
 901
 902                 kvm_migrate_timers(vcpu);
 903                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 904                 local_irq_disable();
 905                 list_add(&vmx->local_vcpus_link,
 906                          &per_cpu(vcpus_on_cpu, cpu));
 907                 local_irq_enable();
 908
 909                 vcpu->cpu = cpu;
 910                 /*
 911                  * Linux uses per-cpu TSS and GDT, so set these when switching
 912                  * processors.
 913                  */
 914                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 915                 native_store_gdt(&dt);
 916                 vmcs_writel(HOST_GDTR_BASE, dt.address);   /* 22.2.4 */
 917
 918                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 919                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 920
 921                 /*
 922                  * Make sure the time stamp counter is monotonous.
 923                  */
 924                 rdtscll(tsc_this);
 925                 if (tsc_this < vcpu->arch.host_tsc) {
 926                         delta = vcpu->arch.host_tsc - tsc_this;
 927                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 928                         vmcs_write64(TSC_OFFSET, new_offset);
 929                 }
 930         }
 931 }
 932
 933 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 934 {
 935         __vmx_load_host_state(to_vmx(vcpu));
 936         if (!vmm_exclusive) {
 937                 __vcpu_clear(to_vmx(vcpu));
 938                 kvm_cpu_vmxoff();
 939         }
 940 }
 941
 942 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 943 {
 944         ulong cr0;
 945
 946         if (vcpu->fpu_active)
 947                 return;
 948         vcpu->fpu_active = 1;
 949         cr0 = vmcs_readl(GUEST_CR0);
 950         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 951         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 952         vmcs_writel(GUEST_CR0, cr0);
 953         update_exception_bitmap(vcpu);
 954         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 955         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 956 }
 957
 958 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 959
 960 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 961 {
 962         vmx_decache_cr0_guest_bits(vcpu);
 963         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 964         update_exception_bitmap(vcpu);
 965         vcpu->arch.cr0_guest_owned_bits = 0;
 966         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 967         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 968 }
 969
 970 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 971 {
 972         unsigned long rflags, save_rflags;
 973
 974         rflags = vmcs_readl(GUEST_RFLAGS);
 975         if (to_vmx(vcpu)->rmode.vm86_active) {
 976                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 977                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 978                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 979         }
 980         return rflags;
 981 }
 982
 983 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 984 {
 985         if (to_vmx(vcpu)->rmode.vm86_active) {
 986                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 987                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 988         }
 989         vmcs_writel(GUEST_RFLAGS, rflags);
 990 }
 991
 992 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 993 {
 994         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 995         int ret = 0;
 996
 997         if (interruptibility & GUEST_INTR_STATE_STI)
 998                 ret |= KVM_X86_SHADOW_INT_STI;
 999         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1000                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1001
1002         return ret & mask;
1003 }
1004
1005 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1006 {
1007         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1008         u32 interruptibility = interruptibility_old;
1009
1010         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1011
1012         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1013                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1014         else if (mask & KVM_X86_SHADOW_INT_STI)
1015                 interruptibility |= GUEST_INTR_STATE_STI;
1016
1017         if ((interruptibility != interruptibility_old))
1018                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1019 }
1020
1021 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1022 {
1023         unsigned long rip;
1024
1025         rip = kvm_rip_read(vcpu);
1026         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1027         kvm_rip_write(vcpu, rip);
1028
1029         /* skipping an emulated instruction also counts */
1030         vmx_set_interrupt_shadow(vcpu, 0);
1031 }
1032
1033 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1034                                 bool has_error_code, u32 error_code,
1035                                 bool reinject)
1036 {
1037         struct vcpu_vmx *vmx = to_vmx(vcpu);
1038         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1039
1040         if (has_error_code) {
1041                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1042                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1043         }
1044
1045         if (vmx->rmode.vm86_active) {
1046                 vmx->rmode.irq.pending = true;
1047                 vmx->rmode.irq.vector = nr;
1048                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1049                 if (kvm_exception_is_soft(nr))
1050                         vmx->rmode.irq.rip +=
1051                                 vmx->vcpu.arch.event_exit_inst_len;
1052                 intr_info |= INTR_TYPE_SOFT_INTR;
1053                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1054                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1055                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1056                 return;
1057         }
1058
1059         if (kvm_exception_is_soft(nr)) {
1060                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1061                              vmx->vcpu.arch.event_exit_inst_len);
1062                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1063         } else
1064                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1065
1066         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1067 }
1068
1069 static bool vmx_rdtscp_supported(void)
1070 {
1071         return cpu_has_vmx_rdtscp();
1072 }
1073
1074 /*
1075  * Swap MSR entry in host/guest MSR entry array.
1076  */
1077 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1078 {
1079         struct shared_msr_entry tmp;
1080
1081         tmp = vmx->guest_msrs[to];
1082         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1083         vmx->guest_msrs[from] = tmp;
1084 }
1085
1086 /*
1087  * Set up the vmcs to automatically save and restore system
1088  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1089  * mode, as fiddling with msrs is very expensive.
1090  */
1091 static void setup_msrs(struct vcpu_vmx *vmx)
1092 {
1093         int save_nmsrs, index;
1094         unsigned long *msr_bitmap;
1095
1096         vmx_load_host_state(vmx);
1097         save_nmsrs = 0;
1098 #ifdef CONFIG_X86_64
1099         if (is_long_mode(&vmx->vcpu)) {
1100                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1101                 if (index >= 0)
1102                         move_msr_up(vmx, index, save_nmsrs++);
1103                 index = __find_msr_index(vmx, MSR_LSTAR);
1104                 if (index >= 0)
1105                         move_msr_up(vmx, index, save_nmsrs++);
1106                 index = __find_msr_index(vmx, MSR_CSTAR);
1107                 if (index >= 0)
1108                         move_msr_up(vmx, index, save_nmsrs++);
1109                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1110                 if (index >= 0 && vmx->rdtscp_enabled)
1111                         move_msr_up(vmx, index, save_nmsrs++);
1112                 /*
1113                  * MSR_STAR is only needed on long mode guests, and only
1114                  * if efer.sce is enabled.
1115                  */
1116                 index = __find_msr_index(vmx, MSR_STAR);
1117                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1118                         move_msr_up(vmx, index, save_nmsrs++);
1119         }
1120 #endif
1121         index = __find_msr_index(vmx, MSR_EFER);
1122         if (index >= 0 && update_transition_efer(vmx, index))
1123                 move_msr_up(vmx, index, save_nmsrs++);
1124
1125         vmx->save_nmsrs = save_nmsrs;
1126
1127         if (cpu_has_vmx_msr_bitmap()) {
1128                 if (is_long_mode(&vmx->vcpu))
1129                         msr_bitmap = vmx_msr_bitmap_longmode;
1130                 else
1131                         msr_bitmap = vmx_msr_bitmap_legacy;
1132
1133                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1134         }
1135 }
1136
1137 /*
1138  * reads and returns guest's timestamp counter "register"
1139  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1140  */
1141 static u64 guest_read_tsc(void)
1142 {
1143         u64 host_tsc, tsc_offset;
1144
1145         rdtscll(host_tsc);
1146         tsc_offset = vmcs_read64(TSC_OFFSET);
1147         return host_tsc + tsc_offset;
1148 }
1149
1150 /*
1151  * writes 'guest_tsc' into guest's timestamp counter "register"
1152  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1153  */
1154 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1155 {
1156         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1157 }
1158
1159 /*
1160  * Reads an msr value (of 'msr_index') into 'pdata'.
1161  * Returns 0 on success, non-0 otherwise.
1162  * Assumes vcpu_load() was already called.
1163  */
1164 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1165 {
1166         u64 data;
1167         struct shared_msr_entry *msr;
1168
1169         if (!pdata) {
1170                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1171                 return -EINVAL;
1172         }
1173
1174         switch (msr_index) {
1175 #ifdef CONFIG_X86_64
1176         case MSR_FS_BASE:
1177                 data = vmcs_readl(GUEST_FS_BASE);
1178                 break;
1179         case MSR_GS_BASE:
1180                 data = vmcs_readl(GUEST_GS_BASE);
1181                 break;
1182         case MSR_KERNEL_GS_BASE:
1183                 vmx_load_host_state(to_vmx(vcpu));
1184                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1185                 break;
1186 #endif
1187         case MSR_EFER:
1188                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1189         case MSR_IA32_TSC:
1190                 data = guest_read_tsc();
1191                 break;
1192         case MSR_IA32_SYSENTER_CS:
1193                 data = vmcs_read32(GUEST_SYSENTER_CS);
1194                 break;
1195         case MSR_IA32_SYSENTER_EIP:
1196                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1197                 break;
1198         case MSR_IA32_SYSENTER_ESP:
1199                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1200                 break;
1201         case MSR_TSC_AUX:
1202                 if (!to_vmx(vcpu)->rdtscp_enabled)
1203                         return 1;
1204                 /* Otherwise falls through */
1205         default:
1206                 vmx_load_host_state(to_vmx(vcpu));
1207                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1208                 if (msr) {
1209                         vmx_load_host_state(to_vmx(vcpu));
1210                         data = msr->data;
1211                         break;
1212                 }
1213                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1214         }
1215
1216         *pdata = data;
1217         return 0;
1218 }
1219
1220 /*
1221  * Writes msr value into into the appropriate "register".
1222  * Returns 0 on success, non-0 otherwise.
1223  * Assumes vcpu_load() was already called.
1224  */
1225 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1226 {
1227         struct vcpu_vmx *vmx = to_vmx(vcpu);
1228         struct shared_msr_entry *msr;
1229         u64 host_tsc;
1230         int ret = 0;
1231
1232         switch (msr_index) {
1233         case MSR_EFER:
1234                 vmx_load_host_state(vmx);
1235                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1236                 break;
1237 #ifdef CONFIG_X86_64
1238         case MSR_FS_BASE:
1239                 vmcs_writel(GUEST_FS_BASE, data);
1240                 break;
1241         case MSR_GS_BASE:
1242                 vmcs_writel(GUEST_GS_BASE, data);
1243                 break;
1244         case MSR_KERNEL_GS_BASE:
1245                 vmx_load_host_state(vmx);
1246                 vmx->msr_guest_kernel_gs_base = data;
1247                 break;
1248 #endif
1249         case MSR_IA32_SYSENTER_CS:
1250                 vmcs_write32(GUEST_SYSENTER_CS, data);
1251                 break;
1252         case MSR_IA32_SYSENTER_EIP:
1253                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1254                 break;
1255         case MSR_IA32_SYSENTER_ESP:
1256                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1257                 break;
1258         case MSR_IA32_TSC:
1259                 rdtscll(host_tsc);
1260                 guest_write_tsc(data, host_tsc);
1261                 break;
1262         case MSR_IA32_CR_PAT:
1263                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1264                         vmcs_write64(GUEST_IA32_PAT, data);
1265                         vcpu->arch.pat = data;
1266                         break;
1267                 }
1268                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1269                 break;
1270         case MSR_TSC_AUX:
1271                 if (!vmx->rdtscp_enabled)
1272                         return 1;
1273                 /* Check reserved bit, higher 32 bits should be zero */
1274                 if ((data >> 32) != 0)
1275                         return 1;
1276                 /* Otherwise falls through */
1277         default:
1278                 msr = find_msr_entry(vmx, msr_index);
1279                 if (msr) {
1280                         vmx_load_host_state(vmx);
1281                         msr->data = data;
1282                         break;
1283                 }
1284                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1285         }
1286
1287         return ret;
1288 }
1289
1290 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1291 {
1292         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1293         switch (reg) {
1294         case VCPU_REGS_RSP:
1295                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1296                 break;
1297         case VCPU_REGS_RIP:
1298                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1299                 break;
1300         case VCPU_EXREG_PDPTR:
1301                 if (enable_ept)
1302                         ept_save_pdptrs(vcpu);
1303                 break;
1304         default:
1305                 break;
1306         }
1307 }
1308
1309 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1310 {
1311         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1312                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1313         else
1314                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1315
1316         update_exception_bitmap(vcpu);
1317 }
1318
1319 static __init int cpu_has_kvm_support(void)
1320 {
1321         return cpu_has_vmx();
1322 }
1323
1324 static __init int vmx_disabled_by_bios(void)
1325 {
1326         u64 msr;
1327
1328         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1329         if (msr & FEATURE_CONTROL_LOCKED) {
1330                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1331                         && tboot_enabled())
1332                         return 1;
1333                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1334                         && !tboot_enabled())
1335                         return 1;
1336         }
1337
1338         return 0;
1339         /* locked but not enabled */
1340 }
1341
1342 static void kvm_cpu_vmxon(u64 addr)
1343 {
1344         asm volatile (ASM_VMX_VMXON_RAX
1345                         : : "a"(&addr), "m"(addr)
1346                         : "memory", "cc");
1347 }
1348
1349 static int hardware_enable(void *garbage)
1350 {
1351         int cpu = raw_smp_processor_id();
1352         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1353         u64 old, test_bits;
1354
1355         if (read_cr4() & X86_CR4_VMXE)
1356                 return -EBUSY;
1357
1358         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1359         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1360
1361         test_bits = FEATURE_CONTROL_LOCKED;
1362         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1363         if (tboot_enabled())
1364                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1365
1366         if ((old & test_bits) != test_bits) {
1367                 /* enable and lock */
1368                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1369         }
1370         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1371
1372         if (vmm_exclusive) {
1373                 kvm_cpu_vmxon(phys_addr);
1374                 ept_sync_global();
1375         }
1376
1377         store_gdt(&__get_cpu_var(host_gdt));
1378
1379         return 0;
1380 }
1381
1382 static void vmclear_local_vcpus(void)
1383 {
1384         int cpu = raw_smp_processor_id();
1385         struct vcpu_vmx *vmx, *n;
1386
1387         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1388                                  local_vcpus_link)
1389                 __vcpu_clear(vmx);
1390 }
1391
1392
1393 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1394  * tricks.
1395  */
1396 static void kvm_cpu_vmxoff(void)
1397 {
1398         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1399 }
1400
1401 static void hardware_disable(void *garbage)
1402 {
1403         if (vmm_exclusive) {
1404                 vmclear_local_vcpus();
1405                 kvm_cpu_vmxoff();
1406         }
1407         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1408 }
1409
1410 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1411                                       u32 msr, u32 *result)
1412 {
1413         u32 vmx_msr_low, vmx_msr_high;
1414         u32 ctl = ctl_min | ctl_opt;
1415
1416         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1417
1418         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1419         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1420
1421         /* Ensure minimum (required) set of control bits are supported. */
1422         if (ctl_min & ~ctl)
1423                 return -EIO;
1424
1425         *result = ctl;
1426         return 0;
1427 }
1428
1429 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1430 {
1431         u32 vmx_msr_low, vmx_msr_high;
1432         u32 min, opt, min2, opt2;
1433         u32 _pin_based_exec_control = 0;
1434         u32 _cpu_based_exec_control = 0;
1435         u32 _cpu_based_2nd_exec_control = 0;
1436         u32 _vmexit_control = 0;
1437         u32 _vmentry_control = 0;
1438
1439         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1440         opt = PIN_BASED_VIRTUAL_NMIS;
1441         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1442                                 &_pin_based_exec_control) < 0)
1443                 return -EIO;
1444
1445         min = CPU_BASED_HLT_EXITING |
1446 #ifdef CONFIG_X86_64
1447               CPU_BASED_CR8_LOAD_EXITING |
1448               CPU_BASED_CR8_STORE_EXITING |
1449 #endif
1450               CPU_BASED_CR3_LOAD_EXITING |
1451               CPU_BASED_CR3_STORE_EXITING |
1452               CPU_BASED_USE_IO_BITMAPS |
1453               CPU_BASED_MOV_DR_EXITING |
1454               CPU_BASED_USE_TSC_OFFSETING |
1455               CPU_BASED_MWAIT_EXITING |
1456               CPU_BASED_MONITOR_EXITING |
1457               CPU_BASED_INVLPG_EXITING;
1458         opt = CPU_BASED_TPR_SHADOW |
1459               CPU_BASED_USE_MSR_BITMAPS |
1460               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1461         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1462                                 &_cpu_based_exec_control) < 0)
1463                 return -EIO;
1464 #ifdef CONFIG_X86_64
1465         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1466                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1467                                            ~CPU_BASED_CR8_STORE_EXITING;
1468 #endif
1469         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1470                 min2 = 0;
1471                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1472                         SECONDARY_EXEC_WBINVD_EXITING |
1473                         SECONDARY_EXEC_ENABLE_VPID |
1474                         SECONDARY_EXEC_ENABLE_EPT |
1475                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1476                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1477                         SECONDARY_EXEC_RDTSCP;
1478                 if (adjust_vmx_controls(min2, opt2,
1479                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1480                                         &_cpu_based_2nd_exec_control) < 0)
1481                         return -EIO;
1482         }
1483 #ifndef CONFIG_X86_64
1484         if (!(_cpu_based_2nd_exec_control &
1485                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1486                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1487 #endif
1488         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1489                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1490                    enabled */
1491                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1492                                              CPU_BASED_CR3_STORE_EXITING |
1493                                              CPU_BASED_INVLPG_EXITING);
1494                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1495                       vmx_capability.ept, vmx_capability.vpid);
1496         }
1497
1498         min = 0;
1499 #ifdef CONFIG_X86_64
1500         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1501 #endif
1502         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1503         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1504                                 &_vmexit_control) < 0)
1505                 return -EIO;
1506
1507         min = 0;
1508         opt = VM_ENTRY_LOAD_IA32_PAT;
1509         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1510                                 &_vmentry_control) < 0)
1511                 return -EIO;
1512
1513         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1514
1515         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1516         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1517                 return -EIO;
1518
1519 #ifdef CONFIG_X86_64
1520         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1521         if (vmx_msr_high & (1u<<16))
1522                 return -EIO;
1523 #endif
1524
1525         /* Require Write-Back (WB) memory type for VMCS accesses. */
1526         if (((vmx_msr_high >> 18) & 15) != 6)
1527                 return -EIO;
1528
1529         vmcs_conf->size = vmx_msr_high & 0x1fff;
1530         vmcs_conf->order = get_order(vmcs_config.size);
1531         vmcs_conf->revision_id = vmx_msr_low;
1532
1533         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1534         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1535         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1536         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1537         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1538
1539         return 0;
1540 }
1541
1542 static struct vmcs *alloc_vmcs_cpu(int cpu)
1543 {
1544         int node = cpu_to_node(cpu);
1545         struct page *pages;
1546         struct vmcs *vmcs;
1547
1548         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1549         if (!pages)
1550                 return NULL;
1551         vmcs = page_address(pages);
1552         memset(vmcs, 0, vmcs_config.size);
1553         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1554         return vmcs;
1555 }
1556
1557 static struct vmcs *alloc_vmcs(void)
1558 {
1559         return alloc_vmcs_cpu(raw_smp_processor_id());
1560 }
1561
1562 static void free_vmcs(struct vmcs *vmcs)
1563 {
1564         free_pages((unsigned long)vmcs, vmcs_config.order);
1565 }
1566
1567 static void free_kvm_area(void)
1568 {
1569         int cpu;
1570
1571         for_each_possible_cpu(cpu) {
1572                 free_vmcs(per_cpu(vmxarea, cpu));
1573                 per_cpu(vmxarea, cpu) = NULL;
1574         }
1575 }
1576
1577 static __init int alloc_kvm_area(void)
1578 {
1579         int cpu;
1580
1581         for_each_possible_cpu(cpu) {
1582                 struct vmcs *vmcs;
1583
1584                 vmcs = alloc_vmcs_cpu(cpu);
1585                 if (!vmcs) {
1586                         free_kvm_area();
1587                         return -ENOMEM;
1588                 }
1589
1590                 per_cpu(vmxarea, cpu) = vmcs;
1591         }
1592         return 0;
1593 }
1594
1595 static __init int hardware_setup(void)
1596 {
1597         if (setup_vmcs_config(&vmcs_config) < 0)
1598                 return -EIO;
1599
1600         if (boot_cpu_has(X86_FEATURE_NX))
1601                 kvm_enable_efer_bits(EFER_NX);
1602
1603         if (!cpu_has_vmx_vpid())
1604                 enable_vpid = 0;
1605
1606         if (!cpu_has_vmx_ept() ||
1607             !cpu_has_vmx_ept_4levels()) {
1608                 enable_ept = 0;
1609                 enable_unrestricted_guest = 0;
1610         }
1611
1612         if (!cpu_has_vmx_unrestricted_guest())
1613                 enable_unrestricted_guest = 0;
1614
1615         if (!cpu_has_vmx_flexpriority())
1616                 flexpriority_enabled = 0;
1617
1618         if (!cpu_has_vmx_tpr_shadow())
1619                 kvm_x86_ops->update_cr8_intercept = NULL;
1620
1621         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1622                 kvm_disable_largepages();
1623
1624         if (!cpu_has_vmx_ple())
1625                 ple_gap = 0;
1626
1627         return alloc_kvm_area();
1628 }
1629
1630 static __exit void hardware_unsetup(void)
1631 {
1632         free_kvm_area();
1633 }
1634
1635 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1636 {
1637         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1638
1639         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1640                 vmcs_write16(sf->selector, save->selector);
1641                 vmcs_writel(sf->base, save->base);
1642                 vmcs_write32(sf->limit, save->limit);
1643                 vmcs_write32(sf->ar_bytes, save->ar);
1644         } else {
1645                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1646                         << AR_DPL_SHIFT;
1647                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1648         }
1649 }
1650
1651 static void enter_pmode(struct kvm_vcpu *vcpu)
1652 {
1653         unsigned long flags;
1654         struct vcpu_vmx *vmx = to_vmx(vcpu);
1655
1656         vmx->emulation_required = 1;
1657         vmx->rmode.vm86_active = 0;
1658
1659         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1660         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1661         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1662
1663         flags = vmcs_readl(GUEST_RFLAGS);
1664         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1665         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1666         vmcs_writel(GUEST_RFLAGS, flags);
1667
1668         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1669                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1670
1671         update_exception_bitmap(vcpu);
1672
1673         if (emulate_invalid_guest_state)
1674                 return;
1675
1676         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1677         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1678         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1679         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1680
1681         vmcs_write16(GUEST_SS_SELECTOR, 0);
1682         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1683
1684         vmcs_write16(GUEST_CS_SELECTOR,
1685                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1686         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1687 }
1688
1689 static gva_t rmode_tss_base(struct kvm *kvm)
1690 {
1691         if (!kvm->arch.tss_addr) {
1692                 struct kvm_memslots *slots;
1693                 gfn_t base_gfn;
1694
1695                 slots = kvm_memslots(kvm);
1696                 base_gfn = slots->memslots[0].base_gfn +
1697                                  kvm->memslots->memslots[0].npages - 3;
1698                 return base_gfn << PAGE_SHIFT;
1699         }
1700         return kvm->arch.tss_addr;
1701 }
1702
1703 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1704 {
1705         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1706
1707         save->selector = vmcs_read16(sf->selector);
1708         save->base = vmcs_readl(sf->base);
1709         save->limit = vmcs_read32(sf->limit);
1710         save->ar = vmcs_read32(sf->ar_bytes);
1711         vmcs_write16(sf->selector, save->base >> 4);
1712         vmcs_write32(sf->base, save->base & 0xfffff);
1713         vmcs_write32(sf->limit, 0xffff);
1714         vmcs_write32(sf->ar_bytes, 0xf3);
1715 }
1716
1717 static void enter_rmode(struct kvm_vcpu *vcpu)
1718 {
1719         unsigned long flags;
1720         struct vcpu_vmx *vmx = to_vmx(vcpu);
1721
1722         if (enable_unrestricted_guest)
1723                 return;
1724
1725         vmx->emulation_required = 1;
1726         vmx->rmode.vm86_active = 1;
1727
1728         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1729         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1730
1731         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1732         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1733
1734         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1735         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1736
1737         flags = vmcs_readl(GUEST_RFLAGS);
1738         vmx->rmode.save_rflags = flags;
1739
1740         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1741
1742         vmcs_writel(GUEST_RFLAGS, flags);
1743         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1744         update_exception_bitmap(vcpu);
1745
1746         if (emulate_invalid_guest_state)
1747                 goto continue_rmode;
1748
1749         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1750         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1751         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1752
1753         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1754         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1755         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1756                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1757         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1758
1759         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1760         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1761         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1762         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1763
1764 continue_rmode:
1765         kvm_mmu_reset_context(vcpu);
1766         init_rmode(vcpu->kvm);
1767 }
1768
1769 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1770 {
1771         struct vcpu_vmx *vmx = to_vmx(vcpu);
1772         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1773
1774         if (!msr)
1775                 return;
1776
1777         /*
1778          * Force kernel_gs_base reloading before EFER changes, as control
1779          * of this msr depends on is_long_mode().
1780          */
1781         vmx_load_host_state(to_vmx(vcpu));
1782         vcpu->arch.efer = efer;
1783         if (efer & EFER_LMA) {
1784                 vmcs_write32(VM_ENTRY_CONTROLS,
1785                              vmcs_read32(VM_ENTRY_CONTROLS) |
1786                              VM_ENTRY_IA32E_MODE);
1787                 msr->data = efer;
1788         } else {
1789                 vmcs_write32(VM_ENTRY_CONTROLS,
1790                              vmcs_read32(VM_ENTRY_CONTROLS) &
1791                              ~VM_ENTRY_IA32E_MODE);
1792
1793                 msr->data = efer & ~EFER_LME;
1794         }
1795         setup_msrs(vmx);
1796 }
1797
1798 #ifdef CONFIG_X86_64
1799
1800 static void enter_lmode(struct kvm_vcpu *vcpu)
1801 {
1802         u32 guest_tr_ar;
1803
1804         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1805         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1806                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1807                        __func__);
1808                 vmcs_write32(GUEST_TR_AR_BYTES,
1809                              (guest_tr_ar & ~AR_TYPE_MASK)
1810                              | AR_TYPE_BUSY_64_TSS);
1811         }
1812         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1813 }
1814
1815 static void exit_lmode(struct kvm_vcpu *vcpu)
1816 {
1817         vmcs_write32(VM_ENTRY_CONTROLS,
1818                      vmcs_read32(VM_ENTRY_CONTROLS)
1819                      & ~VM_ENTRY_IA32E_MODE);
1820         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1821 }
1822
1823 #endif
1824
1825 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1826 {
1827         vpid_sync_context(to_vmx(vcpu));
1828         if (enable_ept) {
1829                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1830                         return;
1831                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1832         }
1833 }
1834
1835 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1836 {
1837         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1838
1839         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1840         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1841 }
1842
1843 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1844 {
1845         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1846
1847         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1848         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1849 }
1850
1851 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1852 {
1853         if (!test_bit(VCPU_EXREG_PDPTR,
1854                       (unsigned long *)&vcpu->arch.regs_dirty))
1855                 return;
1856
1857         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1858                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1859                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1860                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1861                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1862         }
1863 }
1864
1865 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1866 {
1867         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1868                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1869                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1870                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1871                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1872         }
1873
1874         __set_bit(VCPU_EXREG_PDPTR,
1875                   (unsigned long *)&vcpu->arch.regs_avail);
1876         __set_bit(VCPU_EXREG_PDPTR,
1877                   (unsigned long *)&vcpu->arch.regs_dirty);
1878 }
1879
1880 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1881
1882 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1883                                         unsigned long cr0,
1884                                         struct kvm_vcpu *vcpu)
1885 {
1886         if (!(cr0 & X86_CR0_PG)) {
1887                 /* From paging/starting to nonpaging */
1888                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1889                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1890                              (CPU_BASED_CR3_LOAD_EXITING |
1891                               CPU_BASED_CR3_STORE_EXITING));
1892                 vcpu->arch.cr0 = cr0;
1893                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1894         } else if (!is_paging(vcpu)) {
1895                 /* From nonpaging to paging */
1896                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1897                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1898                              ~(CPU_BASED_CR3_LOAD_EXITING |
1899                                CPU_BASED_CR3_STORE_EXITING));
1900                 vcpu->arch.cr0 = cr0;
1901                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1902         }
1903
1904         if (!(cr0 & X86_CR0_WP))
1905                 *hw_cr0 &= ~X86_CR0_WP;
1906 }
1907
1908 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1909 {
1910         struct vcpu_vmx *vmx = to_vmx(vcpu);
1911         unsigned long hw_cr0;
1912
1913         if (enable_unrestricted_guest)
1914                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1915                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1916         else
1917                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1918
1919         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1920                 enter_pmode(vcpu);
1921
1922         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1923                 enter_rmode(vcpu);
1924
1925 #ifdef CONFIG_X86_64
1926         if (vcpu->arch.efer & EFER_LME) {
1927                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1928                         enter_lmode(vcpu);
1929                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1930                         exit_lmode(vcpu);
1931         }
1932 #endif
1933
1934         if (enable_ept)
1935                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1936
1937         if (!vcpu->fpu_active)
1938                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1939
1940         vmcs_writel(CR0_READ_SHADOW, cr0);
1941         vmcs_writel(GUEST_CR0, hw_cr0);
1942         vcpu->arch.cr0 = cr0;
1943 }
1944
1945 static u64 construct_eptp(unsigned long root_hpa)
1946 {
1947         u64 eptp;
1948
1949         /* TODO write the value reading from MSR */
1950         eptp = VMX_EPT_DEFAULT_MT |
1951                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1952         eptp |= (root_hpa & PAGE_MASK);
1953
1954         return eptp;
1955 }
1956
1957 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1958 {
1959         unsigned long guest_cr3;
1960         u64 eptp;
1961
1962         guest_cr3 = cr3;
1963         if (enable_ept) {
1964                 eptp = construct_eptp(cr3);
1965                 vmcs_write64(EPT_POINTER, eptp);
1966                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1967                         vcpu->kvm->arch.ept_identity_map_addr;
1968                 ept_load_pdptrs(vcpu);
1969         }
1970
1971         vmx_flush_tlb(vcpu);
1972         vmcs_writel(GUEST_CR3, guest_cr3);
1973 }
1974
1975 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1976 {
1977         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1978                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1979
1980         vcpu->arch.cr4 = cr4;
1981         if (enable_ept) {
1982                 if (!is_paging(vcpu)) {
1983                         hw_cr4 &= ~X86_CR4_PAE;
1984                         hw_cr4 |= X86_CR4_PSE;
1985                 } else if (!(cr4 & X86_CR4_PAE)) {
1986                         hw_cr4 &= ~X86_CR4_PAE;
1987                 }
1988         }
1989
1990         vmcs_writel(CR4_READ_SHADOW, cr4);
1991         vmcs_writel(GUEST_CR4, hw_cr4);
1992 }
1993
1994 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1995 {
1996         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1997
1998         return vmcs_readl(sf->base);
1999 }
2000
2001 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2002                             struct kvm_segment *var, int seg)
2003 {
2004         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2005         u32 ar;
2006
2007         var->base = vmcs_readl(sf->base);
2008         var->limit = vmcs_read32(sf->limit);
2009         var->selector = vmcs_read16(sf->selector);
2010         ar = vmcs_read32(sf->ar_bytes);
2011         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2012                 ar = 0;
2013         var->type = ar & 15;
2014         var->s = (ar >> 4) & 1;
2015         var->dpl = (ar >> 5) & 3;
2016         var->present = (ar >> 7) & 1;
2017         var->avl = (ar >> 12) & 1;
2018         var->l = (ar >> 13) & 1;
2019         var->db = (ar >> 14) & 1;
2020         var->g = (ar >> 15) & 1;
2021         var->unusable = (ar >> 16) & 1;
2022 }
2023
2024 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2025 {
2026         if (!is_protmode(vcpu))
2027                 return 0;
2028
2029         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2030                 return 3;
2031
2032         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2033 }
2034
2035 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2036 {
2037         u32 ar;
2038
2039         if (var->unusable)
2040                 ar = 1 << 16;
2041         else {
2042                 ar = var->type & 15;
2043                 ar |= (var->s & 1) << 4;
2044                 ar |= (var->dpl & 3) << 5;
2045                 ar |= (var->present & 1) << 7;
2046                 ar |= (var->avl & 1) << 12;
2047                 ar |= (var->l & 1) << 13;
2048                 ar |= (var->db & 1) << 14;
2049                 ar |= (var->g & 1) << 15;
2050         }
2051         if (ar == 0) /* a 0 value means unusable */
2052                 ar = AR_UNUSABLE_MASK;
2053
2054         return ar;
2055 }
2056
2057 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2058                             struct kvm_segment *var, int seg)
2059 {
2060         struct vcpu_vmx *vmx = to_vmx(vcpu);
2061         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2062         u32 ar;
2063
2064         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2065                 vmx->rmode.tr.selector = var->selector;
2066                 vmx->rmode.tr.base = var->base;
2067                 vmx->rmode.tr.limit = var->limit;
2068                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2069                 return;
2070         }
2071         vmcs_writel(sf->base, var->base);
2072         vmcs_write32(sf->limit, var->limit);
2073         vmcs_write16(sf->selector, var->selector);
2074         if (vmx->rmode.vm86_active && var->s) {
2075                 /*
2076                  * Hack real-mode segments into vm86 compatibility.
2077                  */
2078                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2079                         vmcs_writel(sf->base, 0xf0000);
2080                 ar = 0xf3;
2081         } else
2082                 ar = vmx_segment_access_rights(var);
2083
2084         /*
2085          *   Fix the "Accessed" bit in AR field of segment registers for older
2086          * qemu binaries.
2087          *   IA32 arch specifies that at the time of processor reset the
2088          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2089          * is setting it to 0 in the usedland code. This causes invalid guest
2090          * state vmexit when "unrestricted guest" mode is turned on.
2091          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2092          * tree. Newer qemu binaries with that qemu fix would not need this
2093          * kvm hack.
2094          */
2095         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2096                 ar |= 0x1; /* Accessed */
2097
2098         vmcs_write32(sf->ar_bytes, ar);
2099 }
2100
2101 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2102 {
2103         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2104
2105         *db = (ar >> 14) & 1;
2106         *l = (ar >> 13) & 1;
2107 }
2108
2109 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2110 {
2111         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2112         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2113 }
2114
2115 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2116 {
2117         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2118         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2119 }
2120
2121 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2122 {
2123         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2124         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2125 }
2126
2127 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2128 {
2129         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2130         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2131 }
2132
2133 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2134 {
2135         struct kvm_segment var;
2136         u32 ar;
2137
2138         vmx_get_segment(vcpu, &var, seg);
2139         ar = vmx_segment_access_rights(&var);
2140
2141         if (var.base != (var.selector << 4))
2142                 return false;
2143         if (var.limit != 0xffff)
2144                 return false;
2145         if (ar != 0xf3)
2146                 return false;
2147
2148         return true;
2149 }
2150
2151 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2152 {
2153         struct kvm_segment cs;
2154         unsigned int cs_rpl;
2155
2156         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2157         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2158
2159         if (cs.unusable)
2160                 return false;
2161         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2162                 return false;
2163         if (!cs.s)
2164                 return false;
2165         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2166                 if (cs.dpl > cs_rpl)
2167                         return false;
2168         } else {
2169                 if (cs.dpl != cs_rpl)
2170                         return false;
2171         }
2172         if (!cs.present)
2173                 return false;
2174
2175         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2176         return true;
2177 }
2178
2179 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2180 {
2181         struct kvm_segment ss;
2182         unsigned int ss_rpl;
2183
2184         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2185         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2186
2187         if (ss.unusable)
2188                 return true;
2189         if (ss.type != 3 && ss.type != 7)
2190                 return false;
2191         if (!ss.s)
2192                 return false;
2193         if (ss.dpl != ss_rpl) /* DPL != RPL */
2194                 return false;
2195         if (!ss.present)
2196                 return false;
2197
2198         return true;
2199 }
2200
2201 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2202 {
2203         struct kvm_segment var;
2204         unsigned int rpl;
2205
2206         vmx_get_segment(vcpu, &var, seg);
2207         rpl = var.selector & SELECTOR_RPL_MASK;
2208
2209         if (var.unusable)
2210                 return true;
2211         if (!var.s)
2212                 return false;
2213         if (!var.present)
2214                 return false;
2215         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2216                 if (var.dpl < rpl) /* DPL < RPL */
2217                         return false;
2218         }
2219
2220         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2221          * rights flags
2222          */
2223         return true;
2224 }
2225
2226 static bool tr_valid(struct kvm_vcpu *vcpu)
2227 {
2228         struct kvm_segment tr;
2229
2230         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2231
2232         if (tr.unusable)
2233                 return false;
2234         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2235                 return false;
2236         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2237                 return false;
2238         if (!tr.present)
2239                 return false;
2240
2241         return true;
2242 }
2243
2244 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2245 {
2246         struct kvm_segment ldtr;
2247
2248         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2249
2250         if (ldtr.unusable)
2251                 return true;
2252         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2253                 return false;
2254         if (ldtr.type != 2)
2255                 return false;
2256         if (!ldtr.present)
2257                 return false;
2258
2259         return true;
2260 }
2261
2262 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2263 {
2264         struct kvm_segment cs, ss;
2265
2266         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2267         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2268
2269         return ((cs.selector & SELECTOR_RPL_MASK) ==
2270                  (ss.selector & SELECTOR_RPL_MASK));
2271 }
2272
2273 /*
2274  * Check if guest state is valid. Returns true if valid, false if
2275  * not.
2276  * We assume that registers are always usable
2277  */
2278 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2279 {
2280         /* real mode guest state checks */
2281         if (!is_protmode(vcpu)) {
2282                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2283                         return false;
2284                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2285                         return false;
2286                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2287                         return false;
2288                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2289                         return false;
2290                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2291                         return false;
2292                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2293                         return false;
2294         } else {
2295         /* protected mode guest state checks */
2296                 if (!cs_ss_rpl_check(vcpu))
2297                         return false;
2298                 if (!code_segment_valid(vcpu))
2299                         return false;
2300                 if (!stack_segment_valid(vcpu))
2301                         return false;
2302                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2303                         return false;
2304                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2305                         return false;
2306                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2307                         return false;
2308                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2309                         return false;
2310                 if (!tr_valid(vcpu))
2311                         return false;
2312                 if (!ldtr_valid(vcpu))
2313                         return false;
2314         }
2315         /* TODO:
2316          * - Add checks on RIP
2317          * - Add checks on RFLAGS
2318          */
2319
2320         return true;
2321 }
2322
2323 static int init_rmode_tss(struct kvm *kvm)
2324 {
2325         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2326         u16 data = 0;
2327         int ret = 0;
2328         int r;
2329
2330         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2331         if (r < 0)
2332                 goto out;
2333         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2334         r = kvm_write_guest_page(kvm, fn++, &data,
2335                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2336         if (r < 0)
2337                 goto out;
2338         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2339         if (r < 0)
2340                 goto out;
2341         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2342         if (r < 0)
2343                 goto out;
2344         data = ~0;
2345         r = kvm_write_guest_page(kvm, fn, &data,
2346                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2347                                  sizeof(u8));
2348         if (r < 0)
2349                 goto out;
2350
2351         ret = 1;
2352 out:
2353         return ret;
2354 }
2355
2356 static int init_rmode_identity_map(struct kvm *kvm)
2357 {
2358         int i, r, ret;
2359         pfn_t identity_map_pfn;
2360         u32 tmp;
2361
2362         if (!enable_ept)
2363                 return 1;
2364         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2365                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2366                         "haven't been allocated!\n");
2367                 return 0;
2368         }
2369         if (likely(kvm->arch.ept_identity_pagetable_done))
2370                 return 1;
2371         ret = 0;
2372         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2373         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2374         if (r < 0)
2375                 goto out;
2376         /* Set up identity-mapping pagetable for EPT in real mode */
2377         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2378                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2379                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2380                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2381                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2382                 if (r < 0)
2383                         goto out;
2384         }
2385         kvm->arch.ept_identity_pagetable_done = true;
2386         ret = 1;
2387 out:
2388         return ret;
2389 }
2390
2391 static void seg_setup(int seg)
2392 {
2393         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2394         unsigned int ar;
2395
2396         vmcs_write16(sf->selector, 0);
2397         vmcs_writel(sf->base, 0);
2398         vmcs_write32(sf->limit, 0xffff);
2399         if (enable_unrestricted_guest) {
2400                 ar = 0x93;
2401                 if (seg == VCPU_SREG_CS)
2402                         ar |= 0x08; /* code segment */
2403         } else
2404                 ar = 0xf3;
2405
2406         vmcs_write32(sf->ar_bytes, ar);
2407 }
2408
2409 static int alloc_apic_access_page(struct kvm *kvm)
2410 {
2411         struct kvm_userspace_memory_region kvm_userspace_mem;
2412         int r = 0;
2413
2414         mutex_lock(&kvm->slots_lock);
2415         if (kvm->arch.apic_access_page)
2416                 goto out;
2417         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2418         kvm_userspace_mem.flags = 0;
2419         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2420         kvm_userspace_mem.memory_size = PAGE_SIZE;
2421         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2422         if (r)
2423                 goto out;
2424
2425         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2426 out:
2427         mutex_unlock(&kvm->slots_lock);
2428         return r;
2429 }
2430
2431 static int alloc_identity_pagetable(struct kvm *kvm)
2432 {
2433         struct kvm_userspace_memory_region kvm_userspace_mem;
2434         int r = 0;
2435
2436         mutex_lock(&kvm->slots_lock);
2437         if (kvm->arch.ept_identity_pagetable)
2438                 goto out;
2439         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2440         kvm_userspace_mem.flags = 0;
2441         kvm_userspace_mem.guest_phys_addr =
2442                 kvm->arch.ept_identity_map_addr;
2443         kvm_userspace_mem.memory_size = PAGE_SIZE;
2444         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2445         if (r)
2446                 goto out;
2447
2448         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2449                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2450 out:
2451         mutex_unlock(&kvm->slots_lock);
2452         return r;
2453 }
2454
2455 static void allocate_vpid(struct vcpu_vmx *vmx)
2456 {
2457         int vpid;
2458
2459         vmx->vpid = 0;
2460         if (!enable_vpid)
2461                 return;
2462         spin_lock(&vmx_vpid_lock);
2463         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2464         if (vpid < VMX_NR_VPIDS) {
2465                 vmx->vpid = vpid;
2466                 __set_bit(vpid, vmx_vpid_bitmap);
2467         }
2468         spin_unlock(&vmx_vpid_lock);
2469 }
2470
2471 static void free_vpid(struct vcpu_vmx *vmx)
2472 {
2473         if (!enable_vpid)
2474                 return;
2475         spin_lock(&vmx_vpid_lock);
2476         if (vmx->vpid != 0)
2477                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2478         spin_unlock(&vmx_vpid_lock);
2479 }
2480
2481 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2482 {
2483         int f = sizeof(unsigned long);
2484
2485         if (!cpu_has_vmx_msr_bitmap())
2486                 return;
2487
2488         /*
2489          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2490          * have the write-low and read-high bitmap offsets the wrong way round.
2491          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2492          */
2493         if (msr <= 0x1fff) {
2494                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2495                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2496         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2497                 msr &= 0x1fff;
2498                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2499                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2500         }
2501 }
2502
2503 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2504 {
2505         if (!longmode_only)
2506                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2507         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2508 }
2509
2510 /*
2511  * Sets up the vmcs for emulated real mode.
2512  */
2513 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2514 {
2515         u32 host_sysenter_cs, msr_low, msr_high;
2516         u32 junk;
2517         u64 host_pat, tsc_this, tsc_base;
2518         unsigned long a;
2519         struct desc_ptr dt;
2520         int i;
2521         unsigned long kvm_vmx_return;
2522         u32 exec_control;
2523
2524         /* I/O */
2525         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2526         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2527
2528         if (cpu_has_vmx_msr_bitmap())
2529                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2530
2531         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2532
2533         /* Control */
2534         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2535                 vmcs_config.pin_based_exec_ctrl);
2536
2537         exec_control = vmcs_config.cpu_based_exec_ctrl;
2538         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2539                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2540 #ifdef CONFIG_X86_64
2541                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2542                                 CPU_BASED_CR8_LOAD_EXITING;
2543 #endif
2544         }
2545         if (!enable_ept)
2546                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2547                                 CPU_BASED_CR3_LOAD_EXITING  |
2548                                 CPU_BASED_INVLPG_EXITING;
2549         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2550
2551         if (cpu_has_secondary_exec_ctrls()) {
2552                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2553                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2554                         exec_control &=
2555                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2556                 if (vmx->vpid == 0)
2557                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2558                 if (!enable_ept) {
2559                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2560                         enable_unrestricted_guest = 0;
2561                 }
2562                 if (!enable_unrestricted_guest)
2563                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2564                 if (!ple_gap)
2565                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2566                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2567         }
2568
2569         if (ple_gap) {
2570                 vmcs_write32(PLE_GAP, ple_gap);
2571                 vmcs_write32(PLE_WINDOW, ple_window);
2572         }
2573
2574         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2575         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2576         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2577
2578         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2579         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2580         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2581
2582         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2583         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2584         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2585         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2586         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2587         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2588 #ifdef CONFIG_X86_64
2589         rdmsrl(MSR_FS_BASE, a);
2590         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2591         rdmsrl(MSR_GS_BASE, a);
2592         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2593 #else
2594         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2595         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2596 #endif
2597
2598         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2599
2600         native_store_idt(&dt);
2601         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2602
2603         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2604         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2605         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2606         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2607         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2608         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2609         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2610
2611         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2612         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2613         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2614         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2615         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2616         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2617
2618         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2619                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2620                 host_pat = msr_low | ((u64) msr_high << 32);
2621                 vmcs_write64(HOST_IA32_PAT, host_pat);
2622         }
2623         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2624                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2625                 host_pat = msr_low | ((u64) msr_high << 32);
2626                 /* Write the default value follow host pat */
2627                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2628                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2629                 vmx->vcpu.arch.pat = host_pat;
2630         }
2631
2632         for (i = 0; i < NR_VMX_MSR; ++i) {
2633                 u32 index = vmx_msr_index[i];
2634                 u32 data_low, data_high;
2635                 int j = vmx->nmsrs;
2636
2637                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2638                         continue;
2639                 if (wrmsr_safe(index, data_low, data_high) < 0)
2640                         continue;
2641                 vmx->guest_msrs[j].index = i;
2642                 vmx->guest_msrs[j].data = 0;
2643                 vmx->guest_msrs[j].mask = -1ull;
2644                 ++vmx->nmsrs;
2645         }
2646
2647         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2648
2649         /* 22.2.1, 20.8.1 */
2650         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2651
2652         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2653         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2654         if (enable_ept)
2655                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2656         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2657
2658         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2659         rdtscll(tsc_this);
2660         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2661                 tsc_base = tsc_this;
2662
2663         guest_write_tsc(0, tsc_base);
2664
2665         return 0;
2666 }
2667
2668 static int init_rmode(struct kvm *kvm)
2669 {
2670         int idx, ret = 0;
2671
2672         idx = srcu_read_lock(&kvm->srcu);
2673         if (!init_rmode_tss(kvm))
2674                 goto exit;
2675         if (!init_rmode_identity_map(kvm))
2676                 goto exit;
2677
2678         ret = 1;
2679 exit:
2680         srcu_read_unlock(&kvm->srcu, idx);
2681         return ret;
2682 }
2683
2684 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2685 {
2686         struct vcpu_vmx *vmx = to_vmx(vcpu);
2687         u64 msr;
2688         int ret;
2689
2690         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2691         if (!init_rmode(vmx->vcpu.kvm)) {
2692                 ret = -ENOMEM;
2693                 goto out;
2694         }
2695
2696         vmx->rmode.vm86_active = 0;
2697
2698         vmx->soft_vnmi_blocked = 0;
2699
2700         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2701         kvm_set_cr8(&vmx->vcpu, 0);
2702         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2703         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2704                 msr |= MSR_IA32_APICBASE_BSP;
2705         kvm_set_apic_base(&vmx->vcpu, msr);
2706
2707         ret = fx_init(&vmx->vcpu);
2708         if (ret != 0)
2709                 goto out;
2710
2711         seg_setup(VCPU_SREG_CS);
2712         /*
2713          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2714          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2715          */
2716         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2717                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2718                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2719         } else {
2720                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2721                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2722         }
2723
2724         seg_setup(VCPU_SREG_DS);
2725         seg_setup(VCPU_SREG_ES);
2726         seg_setup(VCPU_SREG_FS);
2727         seg_setup(VCPU_SREG_GS);
2728         seg_setup(VCPU_SREG_SS);
2729
2730         vmcs_write16(GUEST_TR_SELECTOR, 0);
2731         vmcs_writel(GUEST_TR_BASE, 0);
2732         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2733         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2734
2735         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2736         vmcs_writel(GUEST_LDTR_BASE, 0);
2737         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2738         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2739
2740         vmcs_write32(GUEST_SYSENTER_CS, 0);
2741         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2742         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2743
2744         vmcs_writel(GUEST_RFLAGS, 0x02);
2745         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2746                 kvm_rip_write(vcpu, 0xfff0);
2747         else
2748                 kvm_rip_write(vcpu, 0);
2749         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2750
2751         vmcs_writel(GUEST_DR7, 0x400);
2752
2753         vmcs_writel(GUEST_GDTR_BASE, 0);
2754         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2755
2756         vmcs_writel(GUEST_IDTR_BASE, 0);
2757         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2758
2759         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2760         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2761         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2762
2763         /* Special registers */
2764         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2765
2766         setup_msrs(vmx);
2767
2768         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2769
2770         if (cpu_has_vmx_tpr_shadow()) {
2771                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2772                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2773                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2774                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2775                 vmcs_write32(TPR_THRESHOLD, 0);
2776         }
2777
2778         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2779                 vmcs_write64(APIC_ACCESS_ADDR,
2780                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2781
2782         if (vmx->vpid != 0)
2783                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2784
2785         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2786         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2787         vmx_set_cr4(&vmx->vcpu, 0);
2788         vmx_set_efer(&vmx->vcpu, 0);
2789         vmx_fpu_activate(&vmx->vcpu);
2790         update_exception_bitmap(&vmx->vcpu);
2791
2792         vpid_sync_context(vmx);
2793
2794         ret = 0;
2795
2796         /* HACK: Don't enable emulation on guest boot/reset */
2797         vmx->emulation_required = 0;
2798
2799 out:
2800         return ret;
2801 }
2802
2803 static void enable_irq_window(struct kvm_vcpu *vcpu)
2804 {
2805         u32 cpu_based_vm_exec_control;
2806
2807         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2808         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2809         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2810 }
2811
2812 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2813 {
2814         u32 cpu_based_vm_exec_control;
2815
2816         if (!cpu_has_virtual_nmis()) {
2817                 enable_irq_window(vcpu);
2818                 return;
2819         }
2820
2821         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2822         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2823         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2824 }
2825
2826 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2827 {
2828         struct vcpu_vmx *vmx = to_vmx(vcpu);
2829         uint32_t intr;
2830         int irq = vcpu->arch.interrupt.nr;
2831
2832         trace_kvm_inj_virq(irq);
2833
2834         ++vcpu->stat.irq_injections;
2835         if (vmx->rmode.vm86_active) {
2836                 vmx->rmode.irq.pending = true;
2837                 vmx->rmode.irq.vector = irq;
2838                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2839                 if (vcpu->arch.interrupt.soft)
2840                         vmx->rmode.irq.rip +=
2841                                 vmx->vcpu.arch.event_exit_inst_len;
2842                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2843                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2844                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2845                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2846                 return;
2847         }
2848         intr = irq | INTR_INFO_VALID_MASK;
2849         if (vcpu->arch.interrupt.soft) {
2850                 intr |= INTR_TYPE_SOFT_INTR;
2851                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2852                              vmx->vcpu.arch.event_exit_inst_len);
2853         } else
2854                 intr |= INTR_TYPE_EXT_INTR;
2855         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2856 }
2857
2858 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2859 {
2860         struct vcpu_vmx *vmx = to_vmx(vcpu);
2861
2862         if (!cpu_has_virtual_nmis()) {
2863                 /*
2864                  * Tracking the NMI-blocked state in software is built upon
2865                  * finding the next open IRQ window. This, in turn, depends on
2866                  * well-behaving guests: They have to keep IRQs disabled at
2867                  * least as long as the NMI handler runs. Otherwise we may
2868                  * cause NMI nesting, maybe breaking the guest. But as this is
2869                  * highly unlikely, we can live with the residual risk.
2870                  */
2871                 vmx->soft_vnmi_blocked = 1;
2872                 vmx->vnmi_blocked_time = 0;
2873         }
2874
2875         ++vcpu->stat.nmi_injections;
2876         if (vmx->rmode.vm86_active) {
2877                 vmx->rmode.irq.pending = true;
2878                 vmx->rmode.irq.vector = NMI_VECTOR;
2879                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2880                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2881                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2882                              INTR_INFO_VALID_MASK);
2883                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2884                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2885                 return;
2886         }
2887         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2888                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2889 }
2890
2891 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2892 {
2893         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2894                 return 0;
2895
2896         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2897                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2898 }
2899
2900 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2901 {
2902         if (!cpu_has_virtual_nmis())
2903                 return to_vmx(vcpu)->soft_vnmi_blocked;
2904         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2905 }
2906
2907 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2908 {
2909         struct vcpu_vmx *vmx = to_vmx(vcpu);
2910
2911         if (!cpu_has_virtual_nmis()) {
2912                 if (vmx->soft_vnmi_blocked != masked) {
2913                         vmx->soft_vnmi_blocked = masked;
2914                         vmx->vnmi_blocked_time = 0;
2915                 }
2916         } else {
2917                 if (masked)
2918                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2919                                       GUEST_INTR_STATE_NMI);
2920                 else
2921                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2922                                         GUEST_INTR_STATE_NMI);
2923         }
2924 }
2925
2926 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2927 {
2928         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2929                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2930                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2931 }
2932
2933 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2934 {
2935         int ret;
2936         struct kvm_userspace_memory_region tss_mem = {
2937                 .slot = TSS_PRIVATE_MEMSLOT,
2938                 .guest_phys_addr = addr,
2939                 .memory_size = PAGE_SIZE * 3,
2940                 .flags = 0,
2941         };
2942
2943         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2944         if (ret)
2945                 return ret;
2946         kvm->arch.tss_addr = addr;
2947         return 0;
2948 }
2949
2950 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2951                                   int vec, u32 err_code)
2952 {
2953         /*
2954          * Instruction with address size override prefix opcode 0x67
2955          * Cause the #SS fault with 0 error code in VM86 mode.
2956          */
2957         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2958                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2959                         return 1;
2960         /*
2961          * Forward all other exceptions that are valid in real mode.
2962          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2963          *        the required debugging infrastructure rework.
2964          */
2965         switch (vec) {
2966         case DB_VECTOR:
2967                 if (vcpu->guest_debug &
2968                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2969                         return 0;
2970                 kvm_queue_exception(vcpu, vec);
2971                 return 1;
2972         case BP_VECTOR:
2973                 /*
2974                  * Update instruction length as we may reinject the exception
2975                  * from user space while in guest debugging mode.
2976                  */
2977                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2978                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2979                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2980                         return 0;
2981                 /* fall through */
2982         case DE_VECTOR:
2983         case OF_VECTOR:
2984         case BR_VECTOR:
2985         case UD_VECTOR:
2986         case DF_VECTOR:
2987         case SS_VECTOR:
2988         case GP_VECTOR:
2989         case MF_VECTOR:
2990                 kvm_queue_exception(vcpu, vec);
2991                 return 1;
2992         }
2993         return 0;
2994 }
2995
2996 /*
2997  * Trigger machine check on the host. We assume all the MSRs are already set up
2998  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2999  * We pass a fake environment to the machine check handler because we want
3000  * the guest to be always treated like user space, no matter what context
3001  * it used internally.
3002  */
3003 static void kvm_machine_check(void)
3004 {
3005 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3006         struct pt_regs regs = {
3007                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3008                 .flags = X86_EFLAGS_IF,
3009         };
3010
3011         do_machine_check(&regs, 0);
3012 #endif
3013 }
3014
3015 static int handle_machine_check(struct kvm_vcpu *vcpu)
3016 {
3017         /* already handled by vcpu_run */
3018         return 1;
3019 }
3020
3021 static int handle_exception(struct kvm_vcpu *vcpu)
3022 {
3023         struct vcpu_vmx *vmx = to_vmx(vcpu);
3024         struct kvm_run *kvm_run = vcpu->run;
3025         u32 intr_info, ex_no, error_code;
3026         unsigned long cr2, rip, dr6;
3027         u32 vect_info;
3028         enum emulation_result er;
3029
3030         vect_info = vmx->idt_vectoring_info;
3031         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3032
3033         if (is_machine_check(intr_info))
3034                 return handle_machine_check(vcpu);
3035
3036         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3037             !is_page_fault(intr_info)) {
3038                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3039                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3040                 vcpu->run->internal.ndata = 2;
3041                 vcpu->run->internal.data[0] = vect_info;
3042                 vcpu->run->internal.data[1] = intr_info;
3043                 return 0;
3044         }
3045
3046         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3047                 return 1;  /* already handled by vmx_vcpu_run() */
3048
3049         if (is_no_device(intr_info)) {
3050                 vmx_fpu_activate(vcpu);
3051                 return 1;
3052         }
3053
3054         if (is_invalid_opcode(intr_info)) {
3055                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3056                 if (er != EMULATE_DONE)
3057                         kvm_queue_exception(vcpu, UD_VECTOR);
3058                 return 1;
3059         }
3060
3061         error_code = 0;
3062         rip = kvm_rip_read(vcpu);
3063         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3064                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3065         if (is_page_fault(intr_info)) {
3066                 /* EPT won't cause page fault directly */
3067                 if (enable_ept)
3068                         BUG();
3069                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3070                 trace_kvm_page_fault(cr2, error_code);
3071
3072                 if (kvm_event_needs_reinjection(vcpu))
3073                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3074                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3075         }
3076
3077         if (vmx->rmode.vm86_active &&
3078             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3079                                                                 error_code)) {
3080                 if (vcpu->arch.halt_request) {
3081                         vcpu->arch.halt_request = 0;
3082                         return kvm_emulate_halt(vcpu);
3083                 }
3084                 return 1;
3085         }
3086
3087         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3088         switch (ex_no) {
3089         case DB_VECTOR:
3090                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3091                 if (!(vcpu->guest_debug &
3092                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3093                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3094                         kvm_queue_exception(vcpu, DB_VECTOR);
3095                         return 1;
3096                 }
3097                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3098                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3099                 /* fall through */
3100         case BP_VECTOR:
3101                 /*
3102                  * Update instruction length as we may reinject #BP from
3103                  * user space while in guest debugging mode. Reading it for
3104                  * #DB as well causes no harm, it is not used in that case.
3105                  */
3106                 vmx->vcpu.arch.event_exit_inst_len =
3107                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3108                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3109                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3110                 kvm_run->debug.arch.exception = ex_no;
3111                 break;
3112         default:
3113                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3114                 kvm_run->ex.exception = ex_no;
3115                 kvm_run->ex.error_code = error_code;
3116                 break;
3117         }
3118         return 0;
3119 }
3120
3121 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3122 {
3123         ++vcpu->stat.irq_exits;
3124         return 1;
3125 }
3126
3127 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3128 {
3129         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3130         return 0;
3131 }
3132
3133 static int handle_io(struct kvm_vcpu *vcpu)
3134 {
3135         unsigned long exit_qualification;
3136         int size, in, string;
3137         unsigned port;
3138
3139         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3140         string = (exit_qualification & 16) != 0;
3141         in = (exit_qualification & 8) != 0;
3142
3143         ++vcpu->stat.io_exits;
3144
3145         if (string || in)
3146                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3147
3148         port = exit_qualification >> 16;
3149         size = (exit_qualification & 7) + 1;
3150         skip_emulated_instruction(vcpu);
3151
3152         return kvm_fast_pio_out(vcpu, size, port);
3153 }
3154
3155 static void
3156 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3157 {
3158         /*
3159          * Patch in the VMCALL instruction:
3160          */
3161         hypercall[0] = 0x0f;
3162         hypercall[1] = 0x01;
3163         hypercall[2] = 0xc1;
3164 }
3165
3166 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3167 {
3168         if (err)
3169                 kvm_inject_gp(vcpu, 0);
3170         else
3171                 skip_emulated_instruction(vcpu);
3172 }
3173
3174 static int handle_cr(struct kvm_vcpu *vcpu)
3175 {
3176         unsigned long exit_qualification, val;
3177         int cr;
3178         int reg;
3179         int err;
3180
3181         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3182         cr = exit_qualification & 15;
3183         reg = (exit_qualification >> 8) & 15;
3184         switch ((exit_qualification >> 4) & 3) {
3185         case 0: /* mov to cr */
3186                 val = kvm_register_read(vcpu, reg);
3187                 trace_kvm_cr_write(cr, val);
3188                 switch (cr) {
3189                 case 0:
3190                         err = kvm_set_cr0(vcpu, val);
3191                         complete_insn_gp(vcpu, err);
3192                         return 1;
3193                 case 3:
3194                         err = kvm_set_cr3(vcpu, val);
3195                         complete_insn_gp(vcpu, err);
3196                         return 1;
3197                 case 4:
3198                         err = kvm_set_cr4(vcpu, val);
3199                         complete_insn_gp(vcpu, err);
3200                         return 1;
3201                 case 8: {
3202                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3203                                 u8 cr8 = kvm_register_read(vcpu, reg);
3204                                 kvm_set_cr8(vcpu, cr8);
3205                                 skip_emulated_instruction(vcpu);
3206                                 if (irqchip_in_kernel(vcpu->kvm))
3207                                         return 1;
3208                                 if (cr8_prev <= cr8)
3209                                         return 1;
3210                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3211                                 return 0;
3212                         }
3213                 };
3214                 break;
3215         case 2: /* clts */
3216                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3217                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3218                 skip_emulated_instruction(vcpu);
3219                 vmx_fpu_activate(vcpu);
3220                 return 1;
3221         case 1: /*mov from cr*/
3222                 switch (cr) {
3223                 case 3:
3224                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3225                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3226                         skip_emulated_instruction(vcpu);
3227                         return 1;
3228                 case 8:
3229                         val = kvm_get_cr8(vcpu);
3230                         kvm_register_write(vcpu, reg, val);
3231                         trace_kvm_cr_read(cr, val);
3232                         skip_emulated_instruction(vcpu);
3233                         return 1;
3234                 }
3235                 break;
3236         case 3: /* lmsw */
3237                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3238                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3239                 kvm_lmsw(vcpu, val);
3240
3241                 skip_emulated_instruction(vcpu);
3242                 return 1;
3243         default:
3244                 break;
3245         }
3246         vcpu->run->exit_reason = 0;
3247         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3248                (int)(exit_qualification >> 4) & 3, cr);
3249         return 0;
3250 }
3251
3252 static int handle_dr(struct kvm_vcpu *vcpu)
3253 {
3254         unsigned long exit_qualification;
3255         int dr, reg;
3256
3257         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3258         if (!kvm_require_cpl(vcpu, 0))
3259                 return 1;
3260         dr = vmcs_readl(GUEST_DR7);
3261         if (dr & DR7_GD) {
3262                 /*
3263                  * As the vm-exit takes precedence over the debug trap, we
3264                  * need to emulate the latter, either for the host or the
3265                  * guest debugging itself.
3266                  */
3267                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3268                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3269                         vcpu->run->debug.arch.dr7 = dr;
3270                         vcpu->run->debug.arch.pc =
3271                                 vmcs_readl(GUEST_CS_BASE) +
3272                                 vmcs_readl(GUEST_RIP);
3273                         vcpu->run->debug.arch.exception = DB_VECTOR;
3274                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3275                         return 0;
3276                 } else {
3277                         vcpu->arch.dr7 &= ~DR7_GD;
3278                         vcpu->arch.dr6 |= DR6_BD;
3279                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3280                         kvm_queue_exception(vcpu, DB_VECTOR);
3281                         return 1;
3282                 }
3283         }
3284
3285         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3286         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3287         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3288         if (exit_qualification & TYPE_MOV_FROM_DR) {
3289                 unsigned long val;
3290                 if (!kvm_get_dr(vcpu, dr, &val))
3291                         kvm_register_write(vcpu, reg, val);
3292         } else
3293                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3294         skip_emulated_instruction(vcpu);
3295         return 1;
3296 }
3297
3298 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3299 {
3300         vmcs_writel(GUEST_DR7, val);
3301 }
3302
3303 static int handle_cpuid(struct kvm_vcpu *vcpu)
3304 {
3305         kvm_emulate_cpuid(vcpu);
3306         return 1;
3307 }
3308
3309 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3310 {
3311         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3312         u64 data;
3313
3314         if (vmx_get_msr(vcpu, ecx, &data)) {
3315                 trace_kvm_msr_read_ex(ecx);
3316                 kvm_inject_gp(vcpu, 0);
3317                 return 1;
3318         }
3319
3320         trace_kvm_msr_read(ecx, data);
3321
3322         /* FIXME: handling of bits 32:63 of rax, rdx */
3323         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3324         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3325         skip_emulated_instruction(vcpu);
3326         return 1;
3327 }
3328
3329 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3330 {
3331         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3332         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3333                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3334
3335         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3336                 trace_kvm_msr_write_ex(ecx, data);
3337                 kvm_inject_gp(vcpu, 0);
3338                 return 1;
3339         }
3340
3341         trace_kvm_msr_write(ecx, data);
3342         skip_emulated_instruction(vcpu);
3343         return 1;
3344 }
3345
3346 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3347 {
3348         return 1;
3349 }
3350
3351 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3352 {
3353         u32 cpu_based_vm_exec_control;
3354
3355         /* clear pending irq */
3356         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3357         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3358         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3359
3360         ++vcpu->stat.irq_window_exits;
3361
3362         /*
3363          * If the user space waits to inject interrupts, exit as soon as
3364          * possible
3365          */
3366         if (!irqchip_in_kernel(vcpu->kvm) &&
3367             vcpu->run->request_interrupt_window &&
3368             !kvm_cpu_has_interrupt(vcpu)) {
3369                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3370                 return 0;
3371         }
3372         return 1;
3373 }
3374
3375 static int handle_halt(struct kvm_vcpu *vcpu)
3376 {
3377         skip_emulated_instruction(vcpu);
3378         return kvm_emulate_halt(vcpu);
3379 }
3380
3381 static int handle_vmcall(struct kvm_vcpu *vcpu)
3382 {
3383         skip_emulated_instruction(vcpu);
3384         kvm_emulate_hypercall(vcpu);
3385         return 1;
3386 }
3387
3388 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3389 {
3390         kvm_queue_exception(vcpu, UD_VECTOR);
3391         return 1;
3392 }
3393
3394 static int handle_invlpg(struct kvm_vcpu *vcpu)
3395 {
3396         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3397
3398         kvm_mmu_invlpg(vcpu, exit_qualification);
3399         skip_emulated_instruction(vcpu);
3400         return 1;
3401 }
3402
3403 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3404 {
3405         skip_emulated_instruction(vcpu);
3406         kvm_emulate_wbinvd(vcpu);
3407         return 1;
3408 }
3409
3410 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3411 {
3412         u64 new_bv = kvm_read_edx_eax(vcpu);
3413         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3414
3415         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3416                 skip_emulated_instruction(vcpu);
3417         return 1;
3418 }
3419
3420 static int handle_apic_access(struct kvm_vcpu *vcpu)
3421 {
3422         return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3423 }
3424
3425 static int handle_task_switch(struct kvm_vcpu *vcpu)
3426 {
3427         struct vcpu_vmx *vmx = to_vmx(vcpu);
3428         unsigned long exit_qualification;
3429         bool has_error_code = false;
3430         u32 error_code = 0;
3431         u16 tss_selector;
3432         int reason, type, idt_v;
3433
3434         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3435         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3436
3437         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3438
3439         reason = (u32)exit_qualification >> 30;
3440         if (reason == TASK_SWITCH_GATE && idt_v) {
3441                 switch (type) {
3442                 case INTR_TYPE_NMI_INTR:
3443                         vcpu->arch.nmi_injected = false;
3444                         if (cpu_has_virtual_nmis())
3445                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3446                                               GUEST_INTR_STATE_NMI);
3447                         break;
3448                 case INTR_TYPE_EXT_INTR:
3449                 case INTR_TYPE_SOFT_INTR:
3450                         kvm_clear_interrupt_queue(vcpu);
3451                         break;
3452                 case INTR_TYPE_HARD_EXCEPTION:
3453                         if (vmx->idt_vectoring_info &
3454                             VECTORING_INFO_DELIVER_CODE_MASK) {
3455                                 has_error_code = true;
3456                                 error_code =
3457                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3458                         }
3459                         /* fall through */
3460                 case INTR_TYPE_SOFT_EXCEPTION:
3461                         kvm_clear_exception_queue(vcpu);
3462                         break;
3463                 default:
3464                         break;
3465                 }
3466         }
3467         tss_selector = exit_qualification;
3468
3469         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3470                        type != INTR_TYPE_EXT_INTR &&
3471                        type != INTR_TYPE_NMI_INTR))
3472                 skip_emulated_instruction(vcpu);
3473
3474         if (kvm_task_switch(vcpu, tss_selector, reason,
3475                                 has_error_code, error_code) == EMULATE_FAIL) {
3476                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3477                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3478                 vcpu->run->internal.ndata = 0;
3479                 return 0;
3480         }
3481
3482         /* clear all local breakpoint enable flags */
3483         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3484
3485         /*
3486          * TODO: What about debug traps on tss switch?
3487          *       Are we supposed to inject them and update dr6?
3488          */
3489
3490         return 1;
3491 }
3492
3493 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3494 {
3495         unsigned long exit_qualification;
3496         gpa_t gpa;
3497         int gla_validity;
3498
3499         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3500
3501         if (exit_qualification & (1 << 6)) {
3502                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3503                 return -EINVAL;
3504         }
3505
3506         gla_validity = (exit_qualification >> 7) & 0x3;
3507         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3508                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3509                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3510                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3511                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3512                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3513                         (long unsigned int)exit_qualification);
3514                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3515                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3516                 return 0;
3517         }
3518
3519         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3520         trace_kvm_page_fault(gpa, exit_qualification);
3521         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3522 }
3523
3524 static u64 ept_rsvd_mask(u64 spte, int level)
3525 {
3526         int i;
3527         u64 mask = 0;
3528
3529         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3530                 mask |= (1ULL << i);
3531
3532         if (level > 2)
3533                 /* bits 7:3 reserved */
3534                 mask |= 0xf8;
3535         else if (level == 2) {
3536                 if (spte & (1ULL << 7))
3537                         /* 2MB ref, bits 20:12 reserved */
3538                         mask |= 0x1ff000;
3539                 else
3540                         /* bits 6:3 reserved */
3541                         mask |= 0x78;
3542         }
3543
3544         return mask;
3545 }
3546
3547 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3548                                        int level)
3549 {
3550         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3551
3552         /* 010b (write-only) */
3553         WARN_ON((spte & 0x7) == 0x2);
3554
3555         /* 110b (write/execute) */
3556         WARN_ON((spte & 0x7) == 0x6);
3557
3558         /* 100b (execute-only) and value not supported by logical processor */
3559         if (!cpu_has_vmx_ept_execute_only())
3560                 WARN_ON((spte & 0x7) == 0x4);
3561
3562         /* not 000b */
3563         if ((spte & 0x7)) {
3564                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3565
3566                 if (rsvd_bits != 0) {
3567                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3568                                          __func__, rsvd_bits);
3569                         WARN_ON(1);
3570                 }
3571
3572                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3573                         u64 ept_mem_type = (spte & 0x38) >> 3;
3574
3575                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3576                             ept_mem_type == 7) {
3577                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3578                                                 __func__, ept_mem_type);
3579                                 WARN_ON(1);
3580                         }
3581                 }
3582         }
3583 }
3584
3585 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3586 {
3587         u64 sptes[4];
3588         int nr_sptes, i;
3589         gpa_t gpa;
3590
3591         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3592
3593         printk(KERN_ERR "EPT: Misconfiguration.\n");
3594         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3595
3596         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3597
3598         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3599                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3600
3601         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3602         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3603
3604         return 0;
3605 }
3606
3607 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3608 {
3609         u32 cpu_based_vm_exec_control;
3610
3611         /* clear pending NMI */
3612         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3613         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3614         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3615         ++vcpu->stat.nmi_window_exits;
3616
3617         return 1;
3618 }
3619
3620 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3621 {
3622         struct vcpu_vmx *vmx = to_vmx(vcpu);
3623         enum emulation_result err = EMULATE_DONE;
3624         int ret = 1;
3625
3626         while (!guest_state_valid(vcpu)) {
3627                 err = emulate_instruction(vcpu, 0, 0, 0);
3628
3629                 if (err == EMULATE_DO_MMIO) {
3630                         ret = 0;
3631                         goto out;
3632                 }
3633
3634                 if (err != EMULATE_DONE)
3635                         return 0;
3636
3637                 if (signal_pending(current))
3638                         goto out;
3639                 if (need_resched())
3640                         schedule();
3641         }
3642
3643         vmx->emulation_required = 0;
3644 out:
3645         return ret;
3646 }
3647
3648 /*
3649  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3650  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3651  */
3652 static int handle_pause(struct kvm_vcpu *vcpu)
3653 {
3654         skip_emulated_instruction(vcpu);
3655         kvm_vcpu_on_spin(vcpu);
3656
3657         return 1;
3658 }
3659
3660 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3661 {
3662         kvm_queue_exception(vcpu, UD_VECTOR);
3663         return 1;
3664 }
3665
3666 /*
3667  * The exit handlers return 1 if the exit was handled fully and guest execution
3668  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3669  * to be done to userspace and return 0.
3670  */
3671 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3672         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3673         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3674         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3675         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3676         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3677         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3678         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3679         [EXIT_REASON_CPUID]                   = handle_cpuid,
3680         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3681         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3682         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3683         [EXIT_REASON_HLT]                     = handle_halt,
3684         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3685         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3686         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3687         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3688         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3689         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3690         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3691         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3692         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3693         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3694         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3695         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3696         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3697         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3698         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3699         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3700         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3701         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3702         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3703         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3704         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3705         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3706 };
3707
3708 static const int kvm_vmx_max_exit_handlers =
3709         ARRAY_SIZE(kvm_vmx_exit_handlers);
3710
3711 /*
3712  * The guest has exited.  See if we can fix it or if we need userspace
3713  * assistance.
3714  */
3715 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3716 {
3717         struct vcpu_vmx *vmx = to_vmx(vcpu);
3718         u32 exit_reason = vmx->exit_reason;
3719         u32 vectoring_info = vmx->idt_vectoring_info;
3720
3721         trace_kvm_exit(exit_reason, vcpu);
3722
3723         /* If guest state is invalid, start emulating */
3724         if (vmx->emulation_required && emulate_invalid_guest_state)
3725                 return handle_invalid_guest_state(vcpu);
3726
3727         /* Access CR3 don't cause VMExit in paging mode, so we need
3728          * to sync with guest real CR3. */
3729         if (enable_ept && is_paging(vcpu))
3730                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3731
3732         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3733                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3734                 vcpu->run->fail_entry.hardware_entry_failure_reason
3735                         = exit_reason;
3736                 return 0;
3737         }
3738
3739         if (unlikely(vmx->fail)) {
3740                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3741                 vcpu->run->fail_entry.hardware_entry_failure_reason
3742                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3743                 return 0;
3744         }
3745
3746         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3747                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3748                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3749                         exit_reason != EXIT_REASON_TASK_SWITCH))
3750                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3751                        "(0x%x) and exit reason is 0x%x\n",
3752                        __func__, vectoring_info, exit_reason);
3753
3754         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3755                 if (vmx_interrupt_allowed(vcpu)) {
3756                         vmx->soft_vnmi_blocked = 0;
3757                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3758                            vcpu->arch.nmi_pending) {
3759                         /*
3760                          * This CPU don't support us in finding the end of an
3761                          * NMI-blocked window if the guest runs with IRQs
3762                          * disabled. So we pull the trigger after 1 s of
3763                          * futile waiting, but inform the user about this.
3764                          */
3765                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3766                                "state on VCPU %d after 1 s timeout\n",
3767                                __func__, vcpu->vcpu_id);
3768                         vmx->soft_vnmi_blocked = 0;
3769                 }
3770         }
3771
3772         if (exit_reason < kvm_vmx_max_exit_handlers
3773             && kvm_vmx_exit_handlers[exit_reason])
3774                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3775         else {
3776                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3777                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3778         }
3779         return 0;
3780 }
3781
3782 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3783 {
3784         if (irr == -1 || tpr < irr) {
3785                 vmcs_write32(TPR_THRESHOLD, 0);
3786                 return;
3787         }
3788
3789         vmcs_write32(TPR_THRESHOLD, irr);
3790 }
3791
3792 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3793 {
3794         u32 exit_intr_info;
3795         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3796         bool unblock_nmi;
3797         u8 vector;
3798         int type;
3799         bool idtv_info_valid;
3800
3801         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3802
3803         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3804
3805         /* Handle machine checks before interrupts are enabled */
3806         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3807             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3808                 && is_machine_check(exit_intr_info)))
3809                 kvm_machine_check();
3810
3811         /* We need to handle NMIs before interrupts are enabled */
3812         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3813             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3814                 kvm_before_handle_nmi(&vmx->vcpu);
3815                 asm("int $2");
3816                 kvm_after_handle_nmi(&vmx->vcpu);
3817         }
3818
3819         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3820
3821         if (cpu_has_virtual_nmis()) {
3822                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3823                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3824                 /*
3825                  * SDM 3: 27.7.1.2 (September 2008)
3826                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3827                  * a guest IRET fault.
3828                  * SDM 3: 23.2.2 (September 2008)
3829                  * Bit 12 is undefined in any of the following cases:
3830                  *  If the VM exit sets the valid bit in the IDT-vectoring
3831                  *   information field.
3832                  *  If the VM exit is due to a double fault.
3833                  */
3834                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3835                     vector != DF_VECTOR && !idtv_info_valid)
3836                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3837                                       GUEST_INTR_STATE_NMI);
3838         } else if (unlikely(vmx->soft_vnmi_blocked))
3839                 vmx->vnmi_blocked_time +=
3840                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3841
3842         vmx->vcpu.arch.nmi_injected = false;
3843         kvm_clear_exception_queue(&vmx->vcpu);
3844         kvm_clear_interrupt_queue(&vmx->vcpu);
3845
3846         if (!idtv_info_valid)
3847                 return;
3848
3849         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3850         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3851
3852         switch (type) {
3853         case INTR_TYPE_NMI_INTR:
3854                 vmx->vcpu.arch.nmi_injected = true;
3855                 /*
3856                  * SDM 3: 27.7.1.2 (September 2008)
3857                  * Clear bit "block by NMI" before VM entry if a NMI
3858                  * delivery faulted.
3859                  */
3860                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3861                                 GUEST_INTR_STATE_NMI);
3862                 break;
3863         case INTR_TYPE_SOFT_EXCEPTION:
3864                 vmx->vcpu.arch.event_exit_inst_len =
3865                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3866                 /* fall through */
3867         case INTR_TYPE_HARD_EXCEPTION:
3868                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3869                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3870                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3871                 } else
3872                         kvm_queue_exception(&vmx->vcpu, vector);
3873                 break;
3874         case INTR_TYPE_SOFT_INTR:
3875                 vmx->vcpu.arch.event_exit_inst_len =
3876                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3877                 /* fall through */
3878         case INTR_TYPE_EXT_INTR:
3879                 kvm_queue_interrupt(&vmx->vcpu, vector,
3880                         type == INTR_TYPE_SOFT_INTR);
3881                 break;
3882         default:
3883                 break;
3884         }
3885 }
3886
3887 /*
3888  * Failure to inject an interrupt should give us the information
3889  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3890  * when fetching the interrupt redirection bitmap in the real-mode
3891  * tss, this doesn't happen.  So we do it ourselves.
3892  */
3893 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3894 {
3895         vmx->rmode.irq.pending = 0;
3896         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3897                 return;
3898         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3899         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3900                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3901                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3902                 return;
3903         }
3904         vmx->idt_vectoring_info =
3905                 VECTORING_INFO_VALID_MASK
3906                 | INTR_TYPE_EXT_INTR
3907                 | vmx->rmode.irq.vector;
3908 }
3909
3910 #ifdef CONFIG_X86_64
3911 #define R "r"
3912 #define Q "q"
3913 #else
3914 #define R "e"
3915 #define Q "l"
3916 #endif
3917
3918 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3919 {
3920         struct vcpu_vmx *vmx = to_vmx(vcpu);
3921
3922         /* Record the guest's net vcpu time for enforced NMI injections. */
3923         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3924                 vmx->entry_time = ktime_get();
3925
3926         /* Don't enter VMX if guest state is invalid, let the exit handler
3927            start emulation until we arrive back to a valid state */
3928         if (vmx->emulation_required && emulate_invalid_guest_state)
3929                 return;
3930
3931         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3932                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3933         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3934                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3935
3936         /* When single-stepping over STI and MOV SS, we must clear the
3937          * corresponding interruptibility bits in the guest state. Otherwise
3938          * vmentry fails as it then expects bit 14 (BS) in pending debug
3939          * exceptions being set, but that's not correct for the guest debugging
3940          * case. */
3941         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3942                 vmx_set_interrupt_shadow(vcpu, 0);
3943
3944         asm(
3945                 /* Store host registers */
3946                 "push %%"R"dx; push %%"R"bp;"
3947                 "push %%"R"cx \n\t"
3948                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3949                 "je 1f \n\t"
3950                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3951                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3952                 "1: \n\t"
3953                 /* Reload cr2 if changed */
3954                 "mov %c[cr2](%0), %%"R"ax \n\t"
3955                 "mov %%cr2, %%"R"dx \n\t"
3956                 "cmp %%"R"ax, %%"R"dx \n\t"
3957                 "je 2f \n\t"
3958                 "mov %%"R"ax, %%cr2 \n\t"
3959                 "2: \n\t"
3960                 /* Check if vmlaunch of vmresume is needed */
3961                 "cmpl $0, %c[launched](%0) \n\t"
3962                 /* Load guest registers.  Don't clobber flags. */
3963                 "mov %c[rax](%0), %%"R"ax \n\t"
3964                 "mov %c[rbx](%0), %%"R"bx \n\t"
3965                 "mov %c[rdx](%0), %%"R"dx \n\t"
3966                 "mov %c[rsi](%0), %%"R"si \n\t"
3967                 "mov %c[rdi](%0), %%"R"di \n\t"
3968                 "mov %c[rbp](%0), %%"R"bp \n\t"
3969 #ifdef CONFIG_X86_64
3970                 "mov %c[r8](%0),  %%r8  \n\t"
3971                 "mov %c[r9](%0),  %%r9  \n\t"
3972                 "mov %c[r10](%0), %%r10 \n\t"
3973                 "mov %c[r11](%0), %%r11 \n\t"
3974                 "mov %c[r12](%0), %%r12 \n\t"
3975                 "mov %c[r13](%0), %%r13 \n\t"
3976                 "mov %c[r14](%0), %%r14 \n\t"
3977                 "mov %c[r15](%0), %%r15 \n\t"
3978 #endif
3979                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3980
3981                 /* Enter guest mode */
3982                 "jne .Llaunched \n\t"
3983                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3984                 "jmp .Lkvm_vmx_return \n\t"
3985                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3986                 ".Lkvm_vmx_return: "
3987                 /* Save guest registers, load host registers, keep flags */
3988                 "xchg %0,     (%%"R"sp) \n\t"
3989                 "mov %%"R"ax, %c[rax](%0) \n\t"
3990                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3991                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3992                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3993                 "mov %%"R"si, %c[rsi](%0) \n\t"
3994                 "mov %%"R"di, %c[rdi](%0) \n\t"
3995                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3996 #ifdef CONFIG_X86_64
3997                 "mov %%r8,  %c[r8](%0) \n\t"
3998                 "mov %%r9,  %c[r9](%0) \n\t"
3999                 "mov %%r10, %c[r10](%0) \n\t"
4000                 "mov %%r11, %c[r11](%0) \n\t"
4001                 "mov %%r12, %c[r12](%0) \n\t"
4002                 "mov %%r13, %c[r13](%0) \n\t"
4003                 "mov %%r14, %c[r14](%0) \n\t"
4004                 "mov %%r15, %c[r15](%0) \n\t"
4005 #endif
4006                 "mov %%cr2, %%"R"ax   \n\t"
4007                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4008
4009                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
4010                 "setbe %c[fail](%0) \n\t"
4011               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4012                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4013                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4014                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4015                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4016                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4017                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4018                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4019                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4020                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4021                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4022 #ifdef CONFIG_X86_64
4023                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4024                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4025                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4026                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4027                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4028                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4029                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4030                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4031 #endif
4032                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4033               : "cc", "memory"
4034                 , R"bx", R"di", R"si"
4035 #ifdef CONFIG_X86_64
4036                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4037 #endif
4038               );
4039
4040         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4041                                   | (1 << VCPU_EXREG_PDPTR));
4042         vcpu->arch.regs_dirty = 0;
4043
4044         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4045         if (vmx->rmode.irq.pending)
4046                 fixup_rmode_irq(vmx);
4047
4048         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4049         vmx->launched = 1;
4050
4051         vmx_complete_interrupts(vmx);
4052 }
4053
4054 #undef R
4055 #undef Q
4056
4057 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4058 {
4059         struct vcpu_vmx *vmx = to_vmx(vcpu);
4060
4061         if (vmx->vmcs) {
4062                 vcpu_clear(vmx);
4063                 free_vmcs(vmx->vmcs);
4064                 vmx->vmcs = NULL;
4065         }
4066 }
4067
4068 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4069 {
4070         struct vcpu_vmx *vmx = to_vmx(vcpu);
4071
4072         free_vpid(vmx);
4073         vmx_free_vmcs(vcpu);
4074         kfree(vmx->guest_msrs);
4075         kvm_vcpu_uninit(vcpu);
4076         kmem_cache_free(kvm_vcpu_cache, vmx);
4077 }
4078
4079 static inline void vmcs_init(struct vmcs *vmcs)
4080 {
4081         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4082
4083         if (!vmm_exclusive)
4084                 kvm_cpu_vmxon(phys_addr);
4085
4086         vmcs_clear(vmcs);
4087
4088         if (!vmm_exclusive)
4089                 kvm_cpu_vmxoff();
4090 }
4091
4092 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4093 {
4094         int err;
4095         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4096         int cpu;
4097
4098         if (!vmx)
4099                 return ERR_PTR(-ENOMEM);
4100
4101         allocate_vpid(vmx);
4102
4103         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4104         if (err)
4105                 goto free_vcpu;
4106
4107         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4108         if (!vmx->guest_msrs) {
4109                 err = -ENOMEM;
4110                 goto uninit_vcpu;
4111         }
4112
4113         vmx->vmcs = alloc_vmcs();
4114         if (!vmx->vmcs)
4115                 goto free_msrs;
4116
4117         vmcs_init(vmx->vmcs);
4118
4119         cpu = get_cpu();
4120         vmx_vcpu_load(&vmx->vcpu, cpu);
4121         err = vmx_vcpu_setup(vmx);
4122         vmx_vcpu_put(&vmx->vcpu);
4123         put_cpu();
4124         if (err)
4125                 goto free_vmcs;
4126         if (vm_need_virtualize_apic_accesses(kvm))
4127                 if (alloc_apic_access_page(kvm) != 0)
4128                         goto free_vmcs;
4129
4130         if (enable_ept) {
4131                 if (!kvm->arch.ept_identity_map_addr)
4132                         kvm->arch.ept_identity_map_addr =
4133                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4134                 if (alloc_identity_pagetable(kvm) != 0)
4135                         goto free_vmcs;
4136         }
4137
4138         return &vmx->vcpu;
4139
4140 free_vmcs:
4141         free_vmcs(vmx->vmcs);
4142 free_msrs:
4143         kfree(vmx->guest_msrs);
4144 uninit_vcpu:
4145         kvm_vcpu_uninit(&vmx->vcpu);
4146 free_vcpu:
4147         free_vpid(vmx);
4148         kmem_cache_free(kvm_vcpu_cache, vmx);
4149         return ERR_PTR(err);
4150 }
4151
4152 static void __init vmx_check_processor_compat(void *rtn)
4153 {
4154         struct vmcs_config vmcs_conf;
4155
4156         *(int *)rtn = 0;
4157         if (setup_vmcs_config(&vmcs_conf) < 0)
4158                 *(int *)rtn = -EIO;
4159         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4160                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4161                                 smp_processor_id());
4162                 *(int *)rtn = -EIO;
4163         }
4164 }
4165
4166 static int get_ept_level(void)
4167 {
4168         return VMX_EPT_DEFAULT_GAW + 1;
4169 }
4170
4171 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4172 {
4173         u64 ret;
4174
4175         /* For VT-d and EPT combination
4176          * 1. MMIO: always map as UC
4177          * 2. EPT with VT-d:
4178          *   a. VT-d without snooping control feature: can't guarantee the
4179          *      result, try to trust guest.
4180          *   b. VT-d with snooping control feature: snooping control feature of
4181          *      VT-d engine can guarantee the cache correctness. Just set it
4182          *      to WB to keep consistent with host. So the same as item 3.
4183          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4184          *    consistent with host MTRR
4185          */
4186         if (is_mmio)
4187                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4188         else if (vcpu->kvm->arch.iommu_domain &&
4189                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4190                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4191                       VMX_EPT_MT_EPTE_SHIFT;
4192         else
4193                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4194                         | VMX_EPT_IPAT_BIT;
4195
4196         return ret;
4197 }
4198
4199 #define _ER(x) { EXIT_REASON_##x, #x }
4200
4201 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4202         _ER(EXCEPTION_NMI),
4203         _ER(EXTERNAL_INTERRUPT),
4204         _ER(TRIPLE_FAULT),
4205         _ER(PENDING_INTERRUPT),
4206         _ER(NMI_WINDOW),
4207         _ER(TASK_SWITCH),
4208         _ER(CPUID),
4209         _ER(HLT),
4210         _ER(INVLPG),
4211         _ER(RDPMC),
4212         _ER(RDTSC),
4213         _ER(VMCALL),
4214         _ER(VMCLEAR),
4215         _ER(VMLAUNCH),
4216         _ER(VMPTRLD),
4217         _ER(VMPTRST),
4218         _ER(VMREAD),
4219         _ER(VMRESUME),
4220         _ER(VMWRITE),
4221         _ER(VMOFF),
4222         _ER(VMON),
4223         _ER(CR_ACCESS),
4224         _ER(DR_ACCESS),
4225         _ER(IO_INSTRUCTION),
4226         _ER(MSR_READ),
4227         _ER(MSR_WRITE),
4228         _ER(MWAIT_INSTRUCTION),
4229         _ER(MONITOR_INSTRUCTION),
4230         _ER(PAUSE_INSTRUCTION),
4231         _ER(MCE_DURING_VMENTRY),
4232         _ER(TPR_BELOW_THRESHOLD),
4233         _ER(APIC_ACCESS),
4234         _ER(EPT_VIOLATION),
4235         _ER(EPT_MISCONFIG),
4236         _ER(WBINVD),
4237         { -1, NULL }
4238 };
4239
4240 #undef _ER
4241
4242 static int vmx_get_lpage_level(void)
4243 {
4244         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4245                 return PT_DIRECTORY_LEVEL;
4246         else
4247                 /* For shadow and EPT supported 1GB page */
4248                 return PT_PDPE_LEVEL;
4249 }
4250
4251 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4252 {
4253         struct kvm_cpuid_entry2 *best;
4254         struct vcpu_vmx *vmx = to_vmx(vcpu);
4255         u32 exec_control;
4256
4257         vmx->rdtscp_enabled = false;
4258         if (vmx_rdtscp_supported()) {
4259                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4260                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4261                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4262                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4263                                 vmx->rdtscp_enabled = true;
4264                         else {
4265                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4266                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4267                                                 exec_control);
4268                         }
4269                 }
4270         }
4271 }
4272
4273 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4274 {
4275 }
4276
4277 static struct kvm_x86_ops vmx_x86_ops = {
4278         .cpu_has_kvm_support = cpu_has_kvm_support,
4279         .disabled_by_bios = vmx_disabled_by_bios,
4280         .hardware_setup = hardware_setup,
4281         .hardware_unsetup = hardware_unsetup,
4282         .check_processor_compatibility = vmx_check_processor_compat,
4283         .hardware_enable = hardware_enable,
4284         .hardware_disable = hardware_disable,
4285         .cpu_has_accelerated_tpr = report_flexpriority,
4286
4287         .vcpu_create = vmx_create_vcpu,
4288         .vcpu_free = vmx_free_vcpu,
4289         .vcpu_reset = vmx_vcpu_reset,
4290
4291         .prepare_guest_switch = vmx_save_host_state,
4292         .vcpu_load = vmx_vcpu_load,
4293         .vcpu_put = vmx_vcpu_put,
4294
4295         .set_guest_debug = set_guest_debug,
4296         .get_msr = vmx_get_msr,
4297         .set_msr = vmx_set_msr,
4298         .get_segment_base = vmx_get_segment_base,
4299         .get_segment = vmx_get_segment,
4300         .set_segment = vmx_set_segment,
4301         .get_cpl = vmx_get_cpl,
4302         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4303         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4304         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4305         .set_cr0 = vmx_set_cr0,
4306         .set_cr3 = vmx_set_cr3,
4307         .set_cr4 = vmx_set_cr4,
4308         .set_efer = vmx_set_efer,
4309         .get_idt = vmx_get_idt,
4310         .set_idt = vmx_set_idt,
4311         .get_gdt = vmx_get_gdt,
4312         .set_gdt = vmx_set_gdt,
4313         .set_dr7 = vmx_set_dr7,
4314         .cache_reg = vmx_cache_reg,
4315         .get_rflags = vmx_get_rflags,
4316         .set_rflags = vmx_set_rflags,
4317         .fpu_activate = vmx_fpu_activate,
4318         .fpu_deactivate = vmx_fpu_deactivate,
4319
4320         .tlb_flush = vmx_flush_tlb,
4321
4322         .run = vmx_vcpu_run,
4323         .handle_exit = vmx_handle_exit,
4324         .skip_emulated_instruction = skip_emulated_instruction,
4325         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4326         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4327         .patch_hypercall = vmx_patch_hypercall,
4328         .set_irq = vmx_inject_irq,
4329         .set_nmi = vmx_inject_nmi,
4330         .queue_exception = vmx_queue_exception,
4331         .interrupt_allowed = vmx_interrupt_allowed,
4332         .nmi_allowed = vmx_nmi_allowed,
4333         .get_nmi_mask = vmx_get_nmi_mask,
4334         .set_nmi_mask = vmx_set_nmi_mask,
4335         .enable_nmi_window = enable_nmi_window,
4336         .enable_irq_window = enable_irq_window,
4337         .update_cr8_intercept = update_cr8_intercept,
4338
4339         .set_tss_addr = vmx_set_tss_addr,
4340         .get_tdp_level = get_ept_level,
4341         .get_mt_mask = vmx_get_mt_mask,
4342
4343         .exit_reasons_str = vmx_exit_reasons_str,
4344         .get_lpage_level = vmx_get_lpage_level,
4345
4346         .cpuid_update = vmx_cpuid_update,
4347
4348         .rdtscp_supported = vmx_rdtscp_supported,
4349
4350         .set_supported_cpuid = vmx_set_supported_cpuid,
4351
4352         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4353 };
4354
4355 static int __init vmx_init(void)
4356 {
4357         int r, i;
4358
4359         rdmsrl_safe(MSR_EFER, &host_efer);
4360
4361         for (i = 0; i < NR_VMX_MSR; ++i)
4362                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4363
4364         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4365         if (!vmx_io_bitmap_a)
4366                 return -ENOMEM;
4367
4368         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4369         if (!vmx_io_bitmap_b) {
4370                 r = -ENOMEM;
4371                 goto out;
4372         }
4373
4374         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4375         if (!vmx_msr_bitmap_legacy) {
4376                 r = -ENOMEM;
4377                 goto out1;
4378         }
4379
4380         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4381         if (!vmx_msr_bitmap_longmode) {
4382                 r = -ENOMEM;
4383                 goto out2;
4384         }
4385
4386         /*
4387          * Allow direct access to the PC debug port (it is often used for I/O
4388          * delays, but the vmexits simply slow things down).
4389          */
4390         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4391         clear_bit(0x80, vmx_io_bitmap_a);
4392
4393         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4394
4395         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4396         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4397
4398         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4399
4400         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4401                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4402         if (r)
4403                 goto out3;
4404
4405         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4406         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4407         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4408         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4409         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4410         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4411
4412         if (enable_ept) {
4413                 bypass_guest_pf = 0;
4414                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4415                         VMX_EPT_WRITABLE_MASK);
4416                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4417                                 VMX_EPT_EXECUTABLE_MASK);
4418                 kvm_enable_tdp();
4419         } else
4420                 kvm_disable_tdp();
4421
4422         if (bypass_guest_pf)
4423                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4424
4425         return 0;
4426
4427 out3:
4428         free_page((unsigned long)vmx_msr_bitmap_longmode);
4429 out2:
4430         free_page((unsigned long)vmx_msr_bitmap_legacy);
4431 out1:
4432         free_page((unsigned long)vmx_io_bitmap_b);
4433 out:
4434         free_page((unsigned long)vmx_io_bitmap_a);
4435         return r;
4436 }
4437
4438 static void __exit vmx_exit(void)
4439 {
4440         free_page((unsigned long)vmx_msr_bitmap_legacy);
4441         free_page((unsigned long)vmx_msr_bitmap_longmode);
4442         free_page((unsigned long)vmx_io_bitmap_b);
4443         free_page((unsigned long)vmx_io_bitmap_a);
4444
4445         kvm_exit();
4446 }
4447
4448 module_init(vmx_init)
4449 module_exit(vmx_exit)