2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
42 #undef DEBUG_PW /* Port-Write debugging */
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
50 #define RIO_ATMU_REGS_OFFSET 0x10c00
51 #define RIO_P_MSG_REGS_OFFSET 0x11000
52 #define RIO_S_MSG_REGS_OFFSET 0x13000
53 #define RIO_ESCSR 0x158
54 #define RIO_CCSR 0x15c
55 #define RIO_LTLEDCSR 0x0608
56 #define RIO_LTLEDCSR_IER 0x80000000
57 #define RIO_LTLEDCSR_PRT 0x01000000
58 #define RIO_LTLEECSR 0x060c
59 #define RIO_EPWISR 0x10010
60 #define RIO_ISR_AACR 0x10120
61 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
62 #define RIO_MAINT_WIN_SIZE 0x400000
63 #define RIO_DBELL_WIN_SIZE 0x1000
65 #define RIO_MSG_OMR_MUI 0x00000002
66 #define RIO_MSG_OSR_TE 0x00000080
67 #define RIO_MSG_OSR_QOI 0x00000020
68 #define RIO_MSG_OSR_QFI 0x00000010
69 #define RIO_MSG_OSR_MUB 0x00000004
70 #define RIO_MSG_OSR_EOMI 0x00000002
71 #define RIO_MSG_OSR_QEI 0x00000001
73 #define RIO_MSG_IMR_MI 0x00000002
74 #define RIO_MSG_ISR_TE 0x00000080
75 #define RIO_MSG_ISR_QFI 0x00000010
76 #define RIO_MSG_ISR_DIQI 0x00000001
78 #define RIO_IPWMR_SEN 0x00100000
79 #define RIO_IPWMR_QFIE 0x00000100
80 #define RIO_IPWMR_EIE 0x00000020
81 #define RIO_IPWMR_CQ 0x00000002
82 #define RIO_IPWMR_PWE 0x00000001
84 #define RIO_IPWSR_QF 0x00100000
85 #define RIO_IPWSR_TE 0x00000080
86 #define RIO_IPWSR_QFI 0x00000010
87 #define RIO_IPWSR_PWD 0x00000008
88 #define RIO_IPWSR_PWB 0x00000004
90 #define RIO_MSG_DESC_SIZE 32
91 #define RIO_MSG_BUFFER_SIZE 4096
92 #define RIO_MIN_TX_RING_SIZE 2
93 #define RIO_MAX_TX_RING_SIZE 2048
94 #define RIO_MIN_RX_RING_SIZE 2
95 #define RIO_MAX_RX_RING_SIZE 2048
97 #define DOORBELL_DMR_DI 0x00000002
98 #define DOORBELL_DSR_TE 0x00000080
99 #define DOORBELL_DSR_QFI 0x00000010
100 #define DOORBELL_DSR_DIQI 0x00000001
101 #define DOORBELL_TID_OFFSET 0x02
102 #define DOORBELL_SID_OFFSET 0x04
103 #define DOORBELL_INFO_OFFSET 0x06
105 #define DOORBELL_MESSAGE_SIZE 0x08
106 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
107 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
108 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
110 struct rio_atmu_regs {
119 struct rio_msg_regs {
171 struct rio_dbell_ring {
176 struct rio_msg_tx_ring {
179 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
180 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
186 struct rio_msg_rx_ring {
189 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
195 struct rio_port_write_msg {
205 void __iomem *regs_win;
206 struct rio_atmu_regs __iomem *atmu_regs;
207 struct rio_atmu_regs __iomem *maint_atmu_regs;
208 struct rio_atmu_regs __iomem *dbell_atmu_regs;
209 void __iomem *dbell_win;
210 void __iomem *maint_win;
211 struct rio_msg_regs __iomem *msg_regs;
212 struct rio_dbell_ring dbell_ring;
213 struct rio_msg_tx_ring msg_tx_ring;
214 struct rio_msg_rx_ring msg_rx_ring;
215 struct rio_port_write_msg port_write_msg;
220 struct work_struct pw_work;
221 struct kfifo pw_fifo;
222 spinlock_t pw_fifo_lock;
225 #define __fsl_read_rio_config(x, addr, err, op) \
226 __asm__ __volatile__( \
227 "1: "op" %1,0(%2)\n" \
230 ".section .fixup,\"ax\"\n" \
234 ".section __ex_table,\"a\"\n" \
238 : "=r" (err), "=r" (x) \
239 : "b" (addr), "i" (-EFAULT), "0" (err))
241 static void __iomem *rio_regs_win;
244 static int (*saved_mcheck_exception)(struct pt_regs *regs);
246 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
248 const struct exception_table_entry *entry = NULL;
249 unsigned long reason = mfspr(SPRN_MCSR);
251 if (reason & MCSR_BUS_RBERR) {
252 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
253 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
254 /* Check if we are prepared to handle this fault */
255 entry = search_exception_tables(regs->nip);
257 pr_debug("RIO: %s - MC Exception handled\n",
259 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
262 regs->nip = entry->fixup;
268 if (saved_mcheck_exception)
269 return saved_mcheck_exception(regs);
271 return cur_cpu_spec->machine_check(regs);
276 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
277 * @mport: RapidIO master port info
278 * @index: ID of RapidIO interface
279 * @destid: Destination ID of target device
280 * @data: 16-bit info field of RapidIO doorbell message
282 * Sends a MPC85xx doorbell message. Returns %0 on success or
283 * %-EINVAL on failure.
285 static int fsl_rio_doorbell_send(struct rio_mport *mport,
286 int index, u16 destid, u16 data)
288 struct rio_priv *priv = mport->priv;
289 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
290 index, destid, data);
291 switch (mport->phy_type) {
292 case RIO_PHY_PARALLEL:
293 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
294 out_be16(priv->dbell_win, data);
297 /* In the serial version silicons, such as MPC8548, MPC8641,
298 * below operations is must be.
300 out_be32(&priv->msg_regs->odmr, 0x00000000);
301 out_be32(&priv->msg_regs->odretcr, 0x00000004);
302 out_be32(&priv->msg_regs->oddpr, destid << 16);
303 out_be32(&priv->msg_regs->oddatr, data);
304 out_be32(&priv->msg_regs->odmr, 0x00000001);
312 * fsl_local_config_read - Generate a MPC85xx local config space read
313 * @mport: RapidIO master port info
314 * @index: ID of RapdiIO interface
315 * @offset: Offset into configuration space
316 * @len: Length (in bytes) of the maintenance transaction
317 * @data: Value to be read into
319 * Generates a MPC85xx local configuration space read. Returns %0 on
320 * success or %-EINVAL on failure.
322 static int fsl_local_config_read(struct rio_mport *mport,
323 int index, u32 offset, int len, u32 *data)
325 struct rio_priv *priv = mport->priv;
326 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
328 *data = in_be32(priv->regs_win + offset);
334 * fsl_local_config_write - Generate a MPC85xx local config space write
335 * @mport: RapidIO master port info
336 * @index: ID of RapdiIO interface
337 * @offset: Offset into configuration space
338 * @len: Length (in bytes) of the maintenance transaction
339 * @data: Value to be written
341 * Generates a MPC85xx local configuration space write. Returns %0 on
342 * success or %-EINVAL on failure.
344 static int fsl_local_config_write(struct rio_mport *mport,
345 int index, u32 offset, int len, u32 data)
347 struct rio_priv *priv = mport->priv;
349 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
350 index, offset, data);
351 out_be32(priv->regs_win + offset, data);
357 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
358 * @mport: RapidIO master port info
359 * @index: ID of RapdiIO interface
360 * @destid: Destination ID of transaction
361 * @hopcount: Number of hops to target device
362 * @offset: Offset into configuration space
363 * @len: Length (in bytes) of the maintenance transaction
364 * @val: Location to be read into
366 * Generates a MPC85xx read maintenance transaction. Returns %0 on
367 * success or %-EINVAL on failure.
370 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
371 u8 hopcount, u32 offset, int len, u32 *val)
373 struct rio_priv *priv = mport->priv;
378 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
379 index, destid, hopcount, offset, len);
381 /* 16MB maintenance window possible */
382 /* allow only aligned access to maintenance registers */
383 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
386 out_be32(&priv->maint_atmu_regs->rowtar,
387 (destid << 22) | (hopcount << 12) | (offset >> 12));
388 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
390 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
393 __fsl_read_rio_config(rval, data, err, "lbz");
396 __fsl_read_rio_config(rval, data, err, "lhz");
399 __fsl_read_rio_config(rval, data, err, "lwz");
406 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
407 err, destid, hopcount, offset);
416 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
417 * @mport: RapidIO master port info
418 * @index: ID of RapdiIO interface
419 * @destid: Destination ID of transaction
420 * @hopcount: Number of hops to target device
421 * @offset: Offset into configuration space
422 * @len: Length (in bytes) of the maintenance transaction
423 * @val: Value to be written
425 * Generates an MPC85xx write maintenance transaction. Returns %0 on
426 * success or %-EINVAL on failure.
429 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
430 u8 hopcount, u32 offset, int len, u32 val)
432 struct rio_priv *priv = mport->priv;
435 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
436 index, destid, hopcount, offset, len, val);
438 /* 16MB maintenance windows possible */
439 /* allow only aligned access to maintenance registers */
440 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
443 out_be32(&priv->maint_atmu_regs->rowtar,
444 (destid << 22) | (hopcount << 12) | (offset >> 12));
445 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
447 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
450 out_8((u8 *) data, val);
453 out_be16((u16 *) data, val);
456 out_be32((u32 *) data, val);
466 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
467 * @mport: Master port with outbound message queue
468 * @rdev: Target of outbound message
469 * @mbox: Outbound mailbox
470 * @buffer: Message to add to outbound queue
471 * @len: Length of message
473 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
474 * %0 on success or %-EINVAL on failure.
477 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
478 void *buffer, size_t len)
480 struct rio_priv *priv = mport->priv;
482 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
483 + priv->msg_tx_ring.tx_slot;
487 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
488 rdev->destid, mbox, (int)buffer, len);
490 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
495 /* Copy and clear rest of buffer */
496 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
498 if (len < (RIO_MAX_MSG_SIZE - 4))
499 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
500 + len, 0, RIO_MAX_MSG_SIZE - len);
502 switch (mport->phy_type) {
503 case RIO_PHY_PARALLEL:
504 /* Set mbox field for message */
505 desc->dport = mbox & 0x3;
507 /* Enable EOMI interrupt, set priority, and set destid */
508 desc->dattr = 0x28000000 | (rdev->destid << 2);
511 /* Set mbox field for message, and set destid */
512 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
514 /* Enable EOMI interrupt and priority */
515 desc->dattr = 0x28000000;
519 /* Set transfer size aligned to next power of 2 (in double words) */
520 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
522 /* Set snooping and source buffer address */
523 desc->saddr = 0x00000004
524 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
526 /* Increment enqueue pointer */
527 omr = in_be32(&priv->msg_regs->omr);
528 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
530 /* Go to next descriptor */
531 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
532 priv->msg_tx_ring.tx_slot = 0;
538 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
541 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
542 * @irq: Linux interrupt number
543 * @dev_instance: Pointer to interrupt-specific data
545 * Handles outbound message interrupts. Executes a register outbound
546 * mailbox event handler and acks the interrupt occurrence.
549 fsl_rio_tx_handler(int irq, void *dev_instance)
552 struct rio_mport *port = (struct rio_mport *)dev_instance;
553 struct rio_priv *priv = port->priv;
555 osr = in_be32(&priv->msg_regs->osr);
557 if (osr & RIO_MSG_OSR_TE) {
558 pr_info("RIO: outbound message transmission error\n");
559 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
563 if (osr & RIO_MSG_OSR_QOI) {
564 pr_info("RIO: outbound message queue overflow\n");
565 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
569 if (osr & RIO_MSG_OSR_EOMI) {
570 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
571 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
572 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
575 /* Ack the end-of-message interrupt */
576 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
584 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
585 * @mport: Master port implementing the outbound message unit
586 * @dev_id: Device specific pointer to pass on event
587 * @mbox: Mailbox to open
588 * @entries: Number of entries in the outbound mailbox ring
590 * Initializes buffer ring, request the outbound message interrupt,
591 * and enables the outbound message unit. Returns %0 on success and
592 * %-EINVAL or %-ENOMEM on failure.
594 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
597 struct rio_priv *priv = mport->priv;
599 if ((entries < RIO_MIN_TX_RING_SIZE) ||
600 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
605 /* Initialize shadow copy ring */
606 priv->msg_tx_ring.dev_id = dev_id;
607 priv->msg_tx_ring.size = entries;
609 for (i = 0; i < priv->msg_tx_ring.size; i++) {
610 priv->msg_tx_ring.virt_buffer[i] =
611 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
612 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
613 if (!priv->msg_tx_ring.virt_buffer[i]) {
615 for (j = 0; j < priv->msg_tx_ring.size; j++)
616 if (priv->msg_tx_ring.virt_buffer[j])
617 dma_free_coherent(priv->dev,
627 /* Initialize outbound message descriptor ring */
628 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
629 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
630 &priv->msg_tx_ring.phys, GFP_KERNEL);
631 if (!priv->msg_tx_ring.virt) {
635 memset(priv->msg_tx_ring.virt, 0,
636 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
637 priv->msg_tx_ring.tx_slot = 0;
639 /* Point dequeue/enqueue pointers at first entry in ring */
640 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
641 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
643 /* Configure for snooping */
644 out_be32(&priv->msg_regs->osar, 0x00000004);
646 /* Clear interrupt status */
647 out_be32(&priv->msg_regs->osr, 0x000000b3);
649 /* Hook up outbound message handler */
650 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
651 "msg_tx", (void *)mport);
656 * Configure outbound message unit
658 * Interrupts (all enabled, except QEIE)
662 out_be32(&priv->msg_regs->omr, 0x00100220);
664 /* Set number of entries */
665 out_be32(&priv->msg_regs->omr,
666 in_be32(&priv->msg_regs->omr) |
667 ((get_bitmask_order(entries) - 2) << 12));
669 /* Now enable the unit */
670 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
676 dma_free_coherent(priv->dev,
677 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
678 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
681 for (i = 0; i < priv->msg_tx_ring.size; i++)
682 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
683 priv->msg_tx_ring.virt_buffer[i],
684 priv->msg_tx_ring.phys_buffer[i]);
690 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
691 * @mport: Master port implementing the outbound message unit
692 * @mbox: Mailbox to close
694 * Disables the outbound message unit, free all buffers, and
695 * frees the outbound message interrupt.
697 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
699 struct rio_priv *priv = mport->priv;
700 /* Disable inbound message unit */
701 out_be32(&priv->msg_regs->omr, 0);
704 dma_free_coherent(priv->dev,
705 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
706 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
709 free_irq(IRQ_RIO_TX(mport), (void *)mport);
713 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
714 * @irq: Linux interrupt number
715 * @dev_instance: Pointer to interrupt-specific data
717 * Handles inbound message interrupts. Executes a registered inbound
718 * mailbox event handler and acks the interrupt occurrence.
721 fsl_rio_rx_handler(int irq, void *dev_instance)
724 struct rio_mport *port = (struct rio_mport *)dev_instance;
725 struct rio_priv *priv = port->priv;
727 isr = in_be32(&priv->msg_regs->isr);
729 if (isr & RIO_MSG_ISR_TE) {
730 pr_info("RIO: inbound message reception error\n");
731 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
735 /* XXX Need to check/dispatch until queue empty */
736 if (isr & RIO_MSG_ISR_DIQI) {
738 * We implement *only* mailbox 0, but can receive messages
739 * for any mailbox/letter to that mailbox destination. So,
740 * make the callback with an unknown/invalid mailbox number
743 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
745 /* Ack the queueing interrupt */
746 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
754 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
755 * @mport: Master port implementing the inbound message unit
756 * @dev_id: Device specific pointer to pass on event
757 * @mbox: Mailbox to open
758 * @entries: Number of entries in the inbound mailbox ring
760 * Initializes buffer ring, request the inbound message interrupt,
761 * and enables the inbound message unit. Returns %0 on success
762 * and %-EINVAL or %-ENOMEM on failure.
764 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
767 struct rio_priv *priv = mport->priv;
769 if ((entries < RIO_MIN_RX_RING_SIZE) ||
770 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
775 /* Initialize client buffer ring */
776 priv->msg_rx_ring.dev_id = dev_id;
777 priv->msg_rx_ring.size = entries;
778 priv->msg_rx_ring.rx_slot = 0;
779 for (i = 0; i < priv->msg_rx_ring.size; i++)
780 priv->msg_rx_ring.virt_buffer[i] = NULL;
782 /* Initialize inbound message ring */
783 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
784 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
785 &priv->msg_rx_ring.phys, GFP_KERNEL);
786 if (!priv->msg_rx_ring.virt) {
791 /* Point dequeue/enqueue pointers at first entry in ring */
792 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
793 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
795 /* Clear interrupt status */
796 out_be32(&priv->msg_regs->isr, 0x00000091);
798 /* Hook up inbound message handler */
799 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
800 "msg_rx", (void *)mport);
802 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
803 priv->msg_tx_ring.virt_buffer[i],
804 priv->msg_tx_ring.phys_buffer[i]);
809 * Configure inbound message unit:
811 * 4KB max message size
812 * Unmask all interrupt sources
815 out_be32(&priv->msg_regs->imr, 0x001b0060);
817 /* Set number of queue entries */
818 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
820 /* Now enable the unit */
821 setbits32(&priv->msg_regs->imr, 0x1);
828 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
829 * @mport: Master port implementing the inbound message unit
830 * @mbox: Mailbox to close
832 * Disables the inbound message unit, free all buffers, and
833 * frees the inbound message interrupt.
835 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
837 struct rio_priv *priv = mport->priv;
838 /* Disable inbound message unit */
839 out_be32(&priv->msg_regs->imr, 0);
842 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
843 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
846 free_irq(IRQ_RIO_RX(mport), (void *)mport);
850 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
851 * @mport: Master port implementing the inbound message unit
852 * @mbox: Inbound mailbox number
853 * @buf: Buffer to add to inbound queue
855 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
856 * %0 on success or %-EINVAL on failure.
858 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
861 struct rio_priv *priv = mport->priv;
863 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
864 priv->msg_rx_ring.rx_slot);
866 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
868 "RIO: error adding inbound buffer %d, buffer exists\n",
869 priv->msg_rx_ring.rx_slot);
874 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
875 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
876 priv->msg_rx_ring.rx_slot = 0;
882 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
885 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
886 * @mport: Master port implementing the inbound message unit
887 * @mbox: Inbound mailbox number
889 * Gets the next available inbound message from the inbound message queue.
890 * A pointer to the message is returned on success or NULL on failure.
892 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
894 struct rio_priv *priv = mport->priv;
895 u32 phys_buf, virt_buf;
899 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
901 /* If no more messages, then bail out */
902 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
905 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
906 - priv->msg_rx_ring.phys);
907 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
908 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
912 "RIO: inbound message copy failed, no buffers\n");
916 /* Copy max message size, caller is expected to allocate that big */
917 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
919 /* Clear the available buffer */
920 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
923 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
929 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
932 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
933 * @irq: Linux interrupt number
934 * @dev_instance: Pointer to interrupt-specific data
936 * Handles doorbell interrupts. Parses a list of registered
937 * doorbell event handlers and executes a matching event handler.
940 fsl_rio_dbell_handler(int irq, void *dev_instance)
943 struct rio_mport *port = (struct rio_mport *)dev_instance;
944 struct rio_priv *priv = port->priv;
946 dsr = in_be32(&priv->msg_regs->dsr);
948 if (dsr & DOORBELL_DSR_TE) {
949 pr_info("RIO: doorbell reception error\n");
950 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
954 if (dsr & DOORBELL_DSR_QFI) {
955 pr_info("RIO: doorbell queue full\n");
956 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
959 /* XXX Need to check/dispatch until queue empty */
960 if (dsr & DOORBELL_DSR_DIQI) {
962 (u32) priv->dbell_ring.virt +
963 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
964 struct rio_dbell *dbell;
968 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
969 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
971 list_for_each_entry(dbell, &port->dbells, node) {
972 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
973 (dbell->res->end >= DBELL_INF(dmsg))) {
979 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
983 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
984 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
986 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
987 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
995 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
996 * @mport: Master port implementing the inbound doorbell unit
998 * Initializes doorbell unit hardware and inbound DMA buffer
999 * ring. Called from fsl_rio_setup(). Returns %0 on success
1000 * or %-ENOMEM on failure.
1002 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1004 struct rio_priv *priv = mport->priv;
1007 /* Map outbound doorbell window immediately after maintenance window */
1008 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1009 RIO_DBELL_WIN_SIZE);
1010 if (!priv->dbell_win) {
1012 "RIO: unable to map outbound doorbell window\n");
1017 /* Initialize inbound doorbells */
1018 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1019 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1020 if (!priv->dbell_ring.virt) {
1021 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1023 iounmap(priv->dbell_win);
1027 /* Point dequeue/enqueue pointers at first entry in ring */
1028 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1029 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1031 /* Clear interrupt status */
1032 out_be32(&priv->msg_regs->dsr, 0x00000091);
1034 /* Hook up doorbell handler */
1035 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1036 "dbell_rx", (void *)mport);
1038 iounmap(priv->dbell_win);
1039 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1040 priv->dbell_ring.virt, priv->dbell_ring.phys);
1042 "MPC85xx RIO: unable to request inbound doorbell irq");
1046 /* Configure doorbells for snooping, 512 entries, and enable */
1047 out_be32(&priv->msg_regs->dmr, 0x00108161);
1054 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1055 * @irq: Linux interrupt number
1056 * @dev_instance: Pointer to interrupt-specific data
1058 * Handles port write interrupts. Parses a list of registered
1059 * port write event handlers and executes a matching event handler.
1062 fsl_rio_port_write_handler(int irq, void *dev_instance)
1065 struct rio_mport *port = (struct rio_mport *)dev_instance;
1066 struct rio_priv *priv = port->priv;
1069 ipwmr = in_be32(&priv->msg_regs->pwmr);
1070 ipwsr = in_be32(&priv->msg_regs->pwsr);
1072 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1073 if (epwisr & 0x80000000) {
1074 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1075 pr_info("RIO_LTLEDCSR = 0x%x\n", tmp);
1076 out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1079 if (!(epwisr & 0x00000001))
1083 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1084 if (ipwsr & RIO_IPWSR_QF)
1086 if (ipwsr & RIO_IPWSR_TE)
1088 if (ipwsr & RIO_IPWSR_QFI)
1090 if (ipwsr & RIO_IPWSR_PWD)
1092 if (ipwsr & RIO_IPWSR_PWB)
1096 out_be32(&priv->msg_regs->pwsr,
1097 ipwsr & (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1099 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1100 priv->port_write_msg.err_count++;
1101 pr_info("RIO: Port-Write Transaction Err (%d)\n",
1102 priv->port_write_msg.err_count);
1104 if (ipwsr & RIO_IPWSR_PWD) {
1105 priv->port_write_msg.discard_count++;
1106 pr_info("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1107 priv->port_write_msg.discard_count);
1110 /* Schedule deferred processing if PW was received */
1111 if (ipwsr & RIO_IPWSR_QFI) {
1112 /* Save PW message (if there is room in FIFO),
1113 * otherwise discard it.
1115 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1116 priv->port_write_msg.msg_count++;
1117 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1120 priv->port_write_msg.discard_count++;
1121 pr_info("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1122 priv->port_write_msg.discard_count);
1124 schedule_work(&priv->pw_work);
1127 /* Issue Clear Queue command. This allows another
1128 * port-write to be received.
1130 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1135 static void fsl_pw_dpc(struct work_struct *work)
1137 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1138 unsigned long flags;
1139 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1142 * Process port-write messages
1144 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1145 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1147 /* Process one message */
1148 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1152 pr_debug("%s : Port-Write Message:", __func__);
1153 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1155 pr_debug("\n0x%02x: 0x%08x", i*4,
1158 pr_debug(" 0x%08x", msg_buffer[i]);
1163 /* Pass the port-write message to RIO core for processing */
1164 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1165 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1167 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1171 * fsl_rio_pw_enable - enable/disable port-write interface init
1172 * @mport: Master port implementing the port write unit
1173 * @enable: 1=enable; 0=disable port-write message handling
1175 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1177 struct rio_priv *priv = mport->priv;
1180 rval = in_be32(&priv->msg_regs->pwmr);
1183 rval |= RIO_IPWMR_PWE;
1185 rval &= ~RIO_IPWMR_PWE;
1187 out_be32(&priv->msg_regs->pwmr, rval);
1193 * fsl_rio_port_write_init - MPC85xx port write interface init
1194 * @mport: Master port implementing the port write unit
1196 * Initializes port write unit hardware and DMA buffer
1197 * ring. Called from fsl_rio_setup(). Returns %0 on success
1198 * or %-ENOMEM on failure.
1200 static int fsl_rio_port_write_init(struct rio_mport *mport)
1202 struct rio_priv *priv = mport->priv;
1205 /* Following configurations require a disabled port write controller */
1206 out_be32(&priv->msg_regs->pwmr,
1207 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1209 /* Initialize port write */
1210 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1212 &priv->port_write_msg.phys, GFP_KERNEL);
1213 if (!priv->port_write_msg.virt) {
1214 pr_err("RIO: unable allocate port write queue\n");
1218 priv->port_write_msg.err_count = 0;
1219 priv->port_write_msg.discard_count = 0;
1221 /* Point dequeue/enqueue pointers at first entry */
1222 out_be32(&priv->msg_regs->epwqbar, 0);
1223 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1225 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1226 in_be32(&priv->msg_regs->epwqbar),
1227 in_be32(&priv->msg_regs->pwqbar));
1229 /* Clear interrupt status IPWSR */
1230 out_be32(&priv->msg_regs->pwsr,
1231 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1233 /* Configure port write contoller for snooping enable all reporting,
1235 out_be32(&priv->msg_regs->pwmr,
1236 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1239 /* Hook up port-write handler */
1240 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1241 "port-write", (void *)mport);
1243 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1247 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1248 spin_lock_init(&priv->pw_fifo_lock);
1249 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1250 pr_err("FIFO allocation failed\n");
1255 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1256 in_be32(&priv->msg_regs->pwmr),
1257 in_be32(&priv->msg_regs->pwsr));
1262 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1264 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1265 priv->port_write_msg.virt,
1266 priv->port_write_msg.phys);
1270 static char *cmdline = NULL;
1272 static int fsl_rio_get_hdid(int index)
1274 /* XXX Need to parse multiple entries in some format */
1278 return simple_strtol(cmdline, NULL, 0);
1281 static int fsl_rio_get_cmdline(char *s)
1290 __setup("riohdid=", fsl_rio_get_cmdline);
1292 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1297 switch (ccsr >> 30) {
1308 dev_info(dev, "Hardware port width: %s\n", str);
1310 switch ((ccsr >> 27) & 7) {
1312 str = "Single-lane 0";
1315 str = "Single-lane 2";
1324 dev_info(dev, "Training connection status: %s\n", str);
1327 if (!(ccsr & 0x80000000))
1328 dev_info(dev, "Output port operating in 8-bit mode\n");
1329 if (!(ccsr & 0x08000000))
1330 dev_info(dev, "Input port operating in 8-bit mode\n");
1335 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1336 * @dev: platform_device pointer
1338 * Initializes MPC85xx RapidIO hardware interface, configures
1339 * master port with system-specific info, and registers the
1340 * master port with the RapidIO subsystem.
1342 int fsl_rio_setup(struct platform_device *dev)
1344 struct rio_ops *ops;
1345 struct rio_mport *port;
1346 struct rio_priv *priv;
1348 const u32 *dt_range, *cell;
1349 struct resource regs;
1352 u64 law_start, law_size;
1355 if (!dev->dev.of_node) {
1356 dev_err(&dev->dev, "Device OF-Node is NULL");
1360 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
1362 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1363 dev->dev.of_node->full_name);
1366 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1367 dev_info(&dev->dev, "Regs: %pR\n", ®s);
1369 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1371 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1372 dev->dev.of_node->full_name);
1376 /* Get node address wide */
1377 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1381 aw = of_n_addr_cells(dev->dev.of_node);
1382 /* Get node size wide */
1383 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1387 sw = of_n_size_cells(dev->dev.of_node);
1388 /* Get parent address wide wide */
1389 paw = of_n_addr_cells(dev->dev.of_node);
1391 law_start = of_read_number(dt_range + aw, paw);
1392 law_size = of_read_number(dt_range + aw + paw, sw);
1394 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1395 law_start, law_size);
1397 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1402 ops->lcread = fsl_local_config_read;
1403 ops->lcwrite = fsl_local_config_write;
1404 ops->cread = fsl_rio_config_read;
1405 ops->cwrite = fsl_rio_config_write;
1406 ops->dsend = fsl_rio_doorbell_send;
1407 ops->pwenable = fsl_rio_pw_enable;
1409 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1417 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1419 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1424 INIT_LIST_HEAD(&port->dbells);
1425 port->iores.start = law_start;
1426 port->iores.end = law_start + law_size - 1;
1427 port->iores.flags = IORESOURCE_MEM;
1428 port->iores.name = "rio_io_win";
1430 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1431 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1432 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1433 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1434 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1435 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1437 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1438 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1439 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1440 strcpy(port->name, "RIO0 mport");
1442 priv->dev = &dev->dev;
1445 port->host_deviceid = fsl_rio_get_hdid(port->id);
1448 rio_register_mport(port);
1450 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1451 rio_regs_win = priv->regs_win;
1453 /* Probe the master port phy type */
1454 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1455 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1456 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1457 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1458 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1460 /* Checking the port training status */
1461 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1462 dev_err(&dev->dev, "Port is not ready. "
1463 "Try to restart connection...\n");
1464 switch (port->phy_type) {
1465 case RIO_PHY_SERIAL:
1467 out_be32(priv->regs_win + RIO_CCSR, 0);
1469 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1471 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1473 case RIO_PHY_PARALLEL:
1475 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1477 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1481 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1482 dev_err(&dev->dev, "Port restart failed.\n");
1486 dev_info(&dev->dev, "Port restart success!\n");
1488 fsl_rio_info(&dev->dev, ccsr);
1490 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1491 & RIO_PEF_CTLS) >> 4;
1492 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1493 port->sys_size ? 65536 : 256);
1495 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1496 + RIO_ATMU_REGS_OFFSET);
1497 priv->maint_atmu_regs = priv->atmu_regs + 1;
1498 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1499 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1500 ((port->phy_type == RIO_PHY_SERIAL) ?
1501 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1503 /* Set to receive any dist ID for serial RapidIO controller. */
1504 if (port->phy_type == RIO_PHY_SERIAL)
1505 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1507 /* Configure maintenance transaction window */
1508 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1509 out_be32(&priv->maint_atmu_regs->rowar,
1510 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1512 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1514 /* Configure outbound doorbell window */
1515 out_be32(&priv->dbell_atmu_regs->rowbar,
1516 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1517 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1518 fsl_rio_doorbell_init(port);
1519 fsl_rio_port_write_init(port);
1522 saved_mcheck_exception = ppc_md.machine_check_exception;
1523 ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1525 /* Ensure that RFXE is set */
1526 mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
1530 iounmap(priv->regs_win);
1540 /* The probe function for RapidIO peer-to-peer network.
1542 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
1543 const struct of_device_id *match)
1546 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1547 dev->dev.of_node->full_name);
1549 rc = fsl_rio_setup(dev);
1553 /* Enumerate all registered ports */
1554 rc = rio_init_mports();
1559 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1561 .compatible = "fsl,rapidio-delta",
1566 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1568 .name = "fsl-of-rio",
1569 .owner = THIS_MODULE,
1570 .of_match_table = fsl_of_rio_rpn_ids,
1572 .probe = fsl_of_rio_rpn_probe,
1575 static __init int fsl_of_rio_rpn_init(void)
1577 return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1580 subsys_initcall(fsl_of_rio_rpn_init);