2 * linux/arch/arm/mach-vexpress/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/jiffies.h>
16 #include <linux/smp.h>
19 #include <asm/cacheflush.h>
20 #include <asm/localtimer.h>
21 #include <asm/smp_scu.h>
22 #include <asm/unified.h>
24 #include <mach/ct-ca9x4.h>
25 #include <mach/motherboard.h>
26 #define V2M_PA_CS7 0x10000000
30 extern void vexpress_secondary_startup(void);
33 * control for which core is the next to come out of the secondary
36 volatile int __cpuinitdata pen_release = -1;
39 * Write pen_release in a way that is guaranteed to be visible to all
40 * observers, irrespective of whether they're taking part in coherency
41 * or not. This is necessary for the hotplug code to work reliably.
43 static void write_pen_release(int val)
47 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
48 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
51 static void __iomem *scu_base_addr(void)
53 return MMIO_P2V(A9_MPCORE_SCU);
56 static DEFINE_SPINLOCK(boot_lock);
58 void __cpuinit platform_secondary_init(unsigned int cpu)
63 * if any interrupts are already enabled for the primary
64 * core (e.g. timer irq), then they will not have been enabled
67 gic_cpu_init(0, gic_cpu_base_addr);
70 * let the primary processor know we're out of the
71 * pen, then head off into the C entry point
73 write_pen_release(-1);
76 * Synchronise with the boot thread.
78 spin_lock(&boot_lock);
79 spin_unlock(&boot_lock);
82 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
84 unsigned long timeout;
87 * Set synchronisation state between this boot processor
88 * and the secondary one
90 spin_lock(&boot_lock);
93 * This is really belt and braces; we hold unintended secondary
94 * CPUs in the holding pen until we're ready for them. However,
95 * since we haven't sent them a soft interrupt, they shouldn't
98 write_pen_release(cpu);
101 * Send the secondary CPU a soft interrupt, thereby causing
102 * the boot monitor to read the system wide flags register,
103 * and branch to the address found there.
105 smp_cross_call(cpumask_of(cpu));
107 timeout = jiffies + (1 * HZ);
108 while (time_before(jiffies, timeout)) {
110 if (pen_release == -1)
117 * now the secondary core is starting up let it run its
118 * calibrations, then wait for it to finish
120 spin_unlock(&boot_lock);
122 return pen_release != -1 ? -ENOSYS : 0;
126 * Initialise the CPU possible map early - this describes the CPUs
127 * which may be present or become present in the system.
129 void __init smp_init_cpus(void)
131 void __iomem *scu_base = scu_base_addr();
132 unsigned int i, ncores;
134 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
139 "vexpress: strange CM count of 0? Default to 1\n");
144 if (ncores > NR_CPUS) {
146 "vexpress: no. of cores (%d) greater than configured "
147 "maximum of %d - clipping\n",
152 for (i = 0; i < ncores; i++)
153 set_cpu_possible(i, true);
156 void __init smp_prepare_cpus(unsigned int max_cpus)
158 unsigned int ncores = num_possible_cpus();
159 unsigned int cpu = smp_processor_id();
162 smp_store_cpu_info(cpu);
165 * are we trying to boot more cores than exist?
167 if (max_cpus > ncores)
171 * Initialise the present map, which describes the set of CPUs
172 * actually populated at the present time.
174 for (i = 0; i < max_cpus; i++)
175 set_cpu_present(i, true);
178 * Initialise the SCU if there are more than one CPU and let
179 * them know where to start.
183 * Enable the local timer or broadcast device for the
184 * boot CPU, but only if we have more than one CPU.
186 percpu_timer_setup();
188 scu_enable(scu_base_addr());
191 * Write the address of secondary startup into the
192 * system-wide flags register. The boot monitor waits
193 * until it receives a soft interrupt, and then the
194 * secondary CPU branches to this address.
196 writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
197 writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
198 MMIO_P2V(V2M_SYS_FLAGSSET));