1 /* linux/arch/arm/mach-s5pv310/platsmp.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * Based on linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/localtimer.h>
26 #include <asm/smp_scu.h>
27 #include <asm/unified.h>
29 #include <plat/s5pv310.h>
31 #include <mach/hardware.h>
32 #include <mach/regs-clock.h>
33 #include <mach/cpu_revision.h>
36 #define IC_STANDBY_EN (1 << 6)
37 #define SCU_STANDBY_EN (1 << 5)
39 extern void s5pv310_secondary_startup(void);
40 extern inline void platform_do_lowpower(unsigned int cpu);
42 #define CPU1_BOOT_REG (s5pv310_subrev() == 0 ? S5P_VA_SYSRAM : S5P_INFORM5)
45 * control for which core is the next to come out of the secondary
49 volatile int pen_release = -1;
52 * Write pen_release in a way that is guaranteed to be visible to all
53 * observers, irrespective of whether they're taking part in coherency
54 * or not. This is necessary for the hotplug code to work reliably.
56 static void write_pen_release(int val)
60 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
61 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
64 static void __iomem *scu_base_addr(void)
66 return (void __iomem *)(S5P_VA_SCU);
69 static DEFINE_SPINLOCK(boot_lock);
72 static void vfp_enable(void *unused)
74 u32 access = get_copro_access();
77 * Enable full access to VFP (cp10 and cp11)
79 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
83 void __cpuinit platform_secondary_init(unsigned int cpu)
86 unsigned int cpu_arch = cpu_architecture();
88 if (cpu_arch >= CPU_ARCH_ARMv6)
95 * if any interrupts are already enabled for the primary
96 * core (e.g. timer irq), then they will not have been enabled
99 gic_cpu_init(0, gic_cpu_base_addr);
102 * let the primary processor know we're out of the
103 * pen, then head off into the C entry point
105 write_pen_release(-1);
108 * Synchronise with the boot thread.
110 spin_lock(&boot_lock);
111 spin_unlock(&boot_lock);
114 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
116 unsigned long timeout;
119 * Set synchronisation state between this boot processor
120 * and the secondary one
122 spin_lock(&boot_lock);
125 * The secondary processor is waiting to be released from
126 * the holding pen - release it, then wait for it to flag
127 * that it has been released by resetting pen_release.
129 * Note that "pen_release" is the hardware CPU ID, whereas
130 * "cpu" is Linux's internal ID.
132 write_pen_release(cpu);
134 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
135 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
136 S5P_ARM_CORE1_CONFIGURATION);
140 /* wait max 10 ms until cpu1 is on */
141 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
142 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
150 printk(KERN_ERR "cpu1 power enable failed");
151 spin_unlock(&boot_lock);
158 * Send the secondary CPU a soft interrupt, thereby causing
159 * the boot monitor to read the system ram, and branch to
160 * the address found there.
162 smp_cross_call(cpumask_of(cpu));
164 timeout = jiffies + (1 * HZ);
165 while (time_before(jiffies, timeout)) {
168 if (!__raw_readl(CPU1_BOOT_REG)) {
169 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)),
171 smp_cross_call(cpumask_of(cpu));
174 if (pen_release == -1)
181 * now the secondary core is starting up let it run its
182 * calibrations, then wait for it to finish
184 spin_unlock(&boot_lock);
186 return pen_release != -1 ? -ENOSYS : 0;
190 * Initialise the CPU possible map early - this describes the CPUs
191 * which may be present or become present in the system.
194 void __init smp_init_cpus(void)
196 void __iomem *scu_base = scu_base_addr();
197 unsigned int i, ncores;
199 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
204 "S5PV310: strange CM count of 0? Default to 1\n");
209 if (ncores > NR_CPUS) {
211 "S5PV310: no. of cores (%d) greater than configured "
212 "maximum of %d - clipping\n",
217 for (i = 0; i < ncores; i++)
218 set_cpu_possible(i, true);
221 void __init smp_prepare_cpus(unsigned int max_cpus)
223 unsigned int ncores = num_possible_cpus();
224 unsigned int cpu = smp_processor_id();
227 smp_store_cpu_info(cpu);
229 /* are we trying to boot more cores than exist? */
230 if (max_cpus > ncores)
234 * Initialise the present map, which describes the set of CPUs
235 * actually populated at the present time.
237 for (i = 0; i < ncores; i++)
238 set_cpu_present(i, true);
241 * Initialise the SCU if there are more than one CPU and let
242 * them know where to start.
245 for (i = max_cpus; i < ncores; i++)
246 platform_do_lowpower(i);
249 * Enable the local timer or broadcast device for the
250 * boot CPU, but only if we have more than one CPU.
252 percpu_timer_setup();
254 i = __raw_readl(scu_base_addr() + SCU_CTRL);
256 __raw_writel(i, scu_base_addr() + SCU_CTRL);
258 scu_enable(scu_base_addr());
262 * Write the address of secondary startup into the
263 * system-wide flags register. The boot monitor waits
264 * until it receives a soft interrupt, and then the
265 * secondary CPU branches to this address.
267 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)),