arch/arm/mach-s5pv310/include/mach/regs-hdmi.h

   1 /* linux/arch/arm/mach-s5pv310/include/mach/regs-hdmi.h
   2  *
   3  * Copyright (c) 2010 Samsung Electronics
   4  *              http://www.samsung.com/
   5  *
   6  * HDMI register header file for Samsung TVOUT driver
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ARCH_ARM_REGS_HDMI_H
  14 #define __ARCH_ARM_REGS_HDMI_H
  15
  16 /*
  17  * Register part
  18 */
  19
  20 #define S5P_HDMI_I2C_PHY_BASE(x)                (x)
  21
  22 #define HDMI_I2C_CON                            S5P_HDMI_I2C_PHY_BASE(0x0000)
  23 #define HDMI_I2C_STAT                           S5P_HDMI_I2C_PHY_BASE(0x0004)
  24 #define HDMI_I2C_ADD                            S5P_HDMI_I2C_PHY_BASE(0x0008)
  25 #define HDMI_I2C_DS                             S5P_HDMI_I2C_PHY_BASE(0x000c)
  26 #define HDMI_I2C_LC                             S5P_HDMI_I2C_PHY_BASE(0x0010)
  27
  28 #define S5P_HDMI_CTRL_BASE(x)                   (x)
  29 #define S5P_HDMI_BASE(x)                        ((x) + 0x00010000)
  30 #define S5P_HDMI_SPDIF_BASE(x)                  ((x) + 0x00030000)
  31 #define S5P_HDMI_I2S_BASE(x)                    ((x) + 0x00040000)
  32 #define S5P_HDMI_TG_BASE(x)                     ((x) + 0x00050000)
  33 #define S5P_HDMI_EFUSE_BASE(x)                  ((x) + 0x00060000)
  34
  35
  36 #define S5P_HDMI_INTC_CON                       S5P_HDMI_CTRL_BASE(0x0000)
  37 #define S5P_HDMI_INTC_FLAG                      S5P_HDMI_CTRL_BASE(0x0004)
  38 #define S5P_HDMI_HDCP_KEY_LOAD                  S5P_HDMI_CTRL_BASE(0x0008)
  39 #define S5P_HDMI_HPD_STATUS                     S5P_HDMI_CTRL_BASE(0x000C)
  40 #define S5P_HDMI_AUDIO_CLKSEL                   S5P_HDMI_CTRL_BASE(0x0010)
  41 #define S5P_HDMI_PHY_RSTOUT                     S5P_HDMI_CTRL_BASE(0x0014)
  42 #define S5P_HDMI_PHY_VPLL                       S5P_HDMI_CTRL_BASE(0x0018)
  43 #define S5P_HDMI_PHY_CMU                        S5P_HDMI_CTRL_BASE(0x001C)
  44 #define S5P_HDMI_CORE_RSTOUT                    S5P_HDMI_CTRL_BASE(0x0020)
  45
  46 #define S5P_HDMI_CON_0                          S5P_HDMI_BASE(0x0000)
  47 #define S5P_HDMI_CON_1                          S5P_HDMI_BASE(0x0004)
  48 #define S5P_HDMI_CON_2                          S5P_HDMI_BASE(0x0008)
  49 #define S5P_HDMI_SYS_STATUS                     S5P_HDMI_BASE(0x0010)
  50 #define S5P_HDMI_PHY_STATUS                     S5P_HDMI_BASE(0x0014)
  51 #define S5P_HDMI_STATUS_EN                      S5P_HDMI_BASE(0x0020)
  52 #define S5P_HDMI_HPD                            S5P_HDMI_BASE(0x0030)
  53 #define S5P_HDMI_MODE_SEL                       S5P_HDMI_BASE(0x0040)
  54 #define S5P_HDMI_ENC_EN                         S5P_HDMI_BASE(0x0044)
  55
  56 #define S5P_HDMI_BLUE_SCREEN_0                  S5P_HDMI_BASE(0x0050)
  57 #define S5P_HDMI_BLUE_SCREEN_1                  S5P_HDMI_BASE(0x0054)
  58 #define S5P_HDMI_BLUE_SCREEN_2                  S5P_HDMI_BASE(0x0058)
  59
  60 #define S5P_HDMI_YMAX                           S5P_HDMI_BASE(0x0060)
  61 #define S5P_HDMI_YMIN                           S5P_HDMI_BASE(0x0064)
  62 #define S5P_HDMI_CMAX                           S5P_HDMI_BASE(0x0068)
  63 #define S5P_HDMI_CMIN                           S5P_HDMI_BASE(0x006C)
  64
  65 #define S5P_HDMI_H_BLANK_0                      S5P_HDMI_BASE(0x00A0)
  66 #define S5P_HDMI_H_BLANK_1                      S5P_HDMI_BASE(0x00A4)
  67 #define S5P_HDMI_V_BLANK_0                      S5P_HDMI_BASE(0x00B0)
  68 #define S5P_HDMI_V_BLANK_1                      S5P_HDMI_BASE(0x00B4)
  69 #define S5P_HDMI_V_BLANK_2                      S5P_HDMI_BASE(0x00B8)
  70 #define S5P_HDMI_H_V_LINE_0                     S5P_HDMI_BASE(0x00C0)
  71 #define S5P_HDMI_H_V_LINE_1                     S5P_HDMI_BASE(0x00C4)
  72 #define S5P_HDMI_H_V_LINE_2                     S5P_HDMI_BASE(0x00C8)
  73
  74 #define S5P_HDMI_SYNC_MODE                      S5P_HDMI_BASE(0x00E4)
  75 #define S5P_HDMI_INT_PRO_MODE                   S5P_HDMI_BASE(0x00E8)
  76
  77 #define S5P_HDMI_V_BLANK_F_0                    S5P_HDMI_BASE(0x0110)
  78 #define S5P_HDMI_V_BLANK_F_1                    S5P_HDMI_BASE(0x0114)
  79 #define S5P_HDMI_V_BLANK_F_2                    S5P_HDMI_BASE(0x0118)
  80 #define S5P_HDMI_H_SYNC_GEN_0                   S5P_HDMI_BASE(0x0120)
  81 #define S5P_HDMI_H_SYNC_GEN_1                   S5P_HDMI_BASE(0x0124)
  82 #define S5P_HDMI_H_SYNC_GEN_2                   S5P_HDMI_BASE(0x0128)
  83 #define S5P_HDMI_V_SYNC_GEN_1_0                 S5P_HDMI_BASE(0x0130)
  84 #define S5P_HDMI_V_SYNC_GEN_1_1                 S5P_HDMI_BASE(0x0134)
  85 #define S5P_HDMI_V_SYNC_GEN_1_2                 S5P_HDMI_BASE(0x0138)
  86 #define S5P_HDMI_V_SYNC_GEN_2_0                 S5P_HDMI_BASE(0x0140)
  87 #define S5P_HDMI_V_SYNC_GEN_2_1                 S5P_HDMI_BASE(0x0144)
  88 #define S5P_HDMI_V_SYNC_GEN_2_2                 S5P_HDMI_BASE(0x0148)
  89 #define S5P_HDMI_V_SYNC_GEN_3_0                 S5P_HDMI_BASE(0x0150)
  90 #define S5P_HDMI_V_SYNC_GEN_3_1                 S5P_HDMI_BASE(0x0154)
  91 #define S5P_HDMI_V_SYNC_GEN_3_2                 S5P_HDMI_BASE(0x0158)
  92
  93 #define S5P_HDMI_ASP_CON                        S5P_HDMI_BASE(0x0160)
  94 #define S5P_HDMI_ASP_SP_FLAT                    S5P_HDMI_BASE(0x0164)
  95 #define S5P_HDMI_ASP_CHCFG0                     S5P_HDMI_BASE(0x0170)
  96 #define S5P_HDMI_ASP_CHCFG1                     S5P_HDMI_BASE(0x0174)
  97 #define S5P_HDMI_ASP_CHCFG2                     S5P_HDMI_BASE(0x0178)
  98 #define S5P_HDMI_ASP_CHCFG3                     S5P_HDMI_BASE(0x017C)
  99
 100 #define S5P_HDMI_ACR_CON                        S5P_HDMI_BASE(0x0180)
 101 #define S5P_HDMI_ACR_MCTS0                      S5P_HDMI_BASE(0x0184)
 102 #define S5P_HDMI_ACR_MCTS1                      S5P_HDMI_BASE(0x0188)
 103 #define S5P_HDMI_ACR_MCTS2                      S5P_HDMI_BASE(0x018C)
 104 #define S5P_HDMI_ACR_CTS0                       S5P_HDMI_BASE(0x0190)
 105 #define S5P_HDMI_ACR_CTS1                       S5P_HDMI_BASE(0x0194)
 106 #define S5P_HDMI_ACR_CTS2                       S5P_HDMI_BASE(0x0198)
 107 #define S5P_HDMI_ACR_N0                         S5P_HDMI_BASE(0x01A0)
 108 #define S5P_HDMI_ACR_N1                         S5P_HDMI_BASE(0x01A4)
 109 #define S5P_HDMI_ACR_N2                         S5P_HDMI_BASE(0x01A8)
 110 #define S5P_HDMI_ACR_LSB2                       S5P_HDMI_BASE(0x01B0)
 111 #define S5P_HDMI_ACR_TXCNT                      S5P_HDMI_BASE(0x01B4)
 112 #define S5P_HDMI_ACR_TXINTERVAL                 S5P_HDMI_BASE(0x01B8)
 113 #define S5P_HDMI_ACR_CTS_OFFSET                 S5P_HDMI_BASE(0x01BC)
 114
 115 #define S5P_HDMI_GCP_CON                        S5P_HDMI_BASE(0x01C0)
 116 #define S5P_HDMI_GCP_BYTE1                      S5P_HDMI_BASE(0x01D0)
 117 #define S5P_HDMI_GCP_BYTE2                      S5P_HDMI_BASE(0x01D4)
 118 #define S5P_HDMI_GCP_BYTE3                      S5P_HDMI_BASE(0x01D8)
 119
 120 #define S5P_HDMI_ACP_CON                        S5P_HDMI_BASE(0x01E0)
 121 #define S5P_HDMI_ACP_TYPE                       S5P_HDMI_BASE(0x01E4)
 122 #define S5P_HDMI_ACP_DATA                       S5P_HDMI_BASE(0x0200)
 123
 124 #define S5P_HDMI_ISRC_CON                       S5P_HDMI_BASE(0x0250)
 125 #define S5P_HDMI_ISRC1_HEADER1                  S5P_HDMI_BASE(0x0264)
 126 #define S5P_HDMI_ISRC1_DATA                     S5P_HDMI_BASE(0x0270)
 127 #define S5P_HDMI_ISRC2_DATA                     S5P_HDMI_BASE(0x02b0)
 128
 129 #define S5P_HDMI_AVI_CON                        S5P_HDMI_BASE(0x0300)
 130 #define S5P_HDMI_AVI_CHECK_SUM                  S5P_HDMI_BASE(0x0310)
 131 #define S5P_HDMI_AVI_DATA                       S5P_HDMI_BASE(0x0320)
 132
 133 #define S5P_HDMI_AUI_CON                        S5P_HDMI_BASE(0x0360)
 134 #define S5P_HDMI_AUI_CHECK_SUM                  S5P_HDMI_BASE(0x0370)
 135
 136 #define S5P_HDMI_AUI_BYTE1                      S5P_HDMI_BASE(0x0380)
 137 #define S5P_HDMI_AUI_BYTE2                      S5P_HDMI_BASE(0x0384)
 138 #define S5P_HDMI_AUI_BYTE3                      S5P_HDMI_BASE(0x0388)
 139 #define S5P_HDMI_AUI_BYTE4                      S5P_HDMI_BASE(0x038c)
 140 #define S5P_HDMI_AUI_BYTE5                      S5P_HDMI_BASE(0x0390)
 141
 142 #define S5P_HDMI_MPG_CON                        S5P_HDMI_BASE(0x03A0)
 143 #define S5P_HDMI_MPG_CHECK_SUM                  S5P_HDMI_BASE(0x03B0)
 144 #define S5P_HDMI_MPG_DATA                       S5P_HDMI_BASE(0x03c0)
 145
 146 #define S5P_HDMI_SPD_CON                        S5P_HDMI_BASE(0x0400)
 147 #define S5P_HDMI_SPD_HEADER                     S5P_HDMI_BASE(0x0410)
 148 #define S5P_HDMI_SPD_DATA                       S5P_HDMI_BASE(0x0420)
 149
 150 #define S5P_HDMI_HDCP_RX_SHA1_0_0               S5P_HDMI_BASE(0x0600)
 151 #define S5P_HDMI_HDCP_RX_SHA1_0_1               S5P_HDMI_BASE(0x0604)
 152 #define S5P_HDMI_HDCP_RX_SHA1_0_2               S5P_HDMI_BASE(0x0608)
 153 #define S5P_HDMI_HDCP_RX_SHA1_0_3               S5P_HDMI_BASE(0x060C)
 154 #define S5P_HDMI_HDCP_RX_SHA1_1_0               S5P_HDMI_BASE(0x0610)
 155 #define S5P_HDMI_HDCP_RX_SHA1_1_1               S5P_HDMI_BASE(0x0614)
 156 #define S5P_HDMI_HDCP_RX_SHA1_1_2               S5P_HDMI_BASE(0x0618)
 157 #define S5P_HDMI_HDCP_RX_SHA1_1_3               S5P_HDMI_BASE(0x061C)
 158 #define S5P_HDMI_HDCP_RX_SHA1_2_0               S5P_HDMI_BASE(0x0620)
 159 #define S5P_HDMI_HDCP_RX_SHA1_2_1               S5P_HDMI_BASE(0x0624)
 160 #define S5P_HDMI_HDCP_RX_SHA1_2_2               S5P_HDMI_BASE(0x0628)
 161 #define S5P_HDMI_HDCP_RX_SHA1_2_3               S5P_HDMI_BASE(0x062C)
 162 #define S5P_HDMI_HDCP_RX_SHA1_3_0               S5P_HDMI_BASE(0x0630)
 163 #define S5P_HDMI_HDCP_RX_SHA1_3_1               S5P_HDMI_BASE(0x0634)
 164 #define S5P_HDMI_HDCP_RX_SHA1_3_2               S5P_HDMI_BASE(0x0638)
 165 #define S5P_HDMI_HDCP_RX_SHA1_3_3               S5P_HDMI_BASE(0x063C)
 166 #define S5P_HDMI_HDCP_RX_SHA1_4_0               S5P_HDMI_BASE(0x0640)
 167 #define S5P_HDMI_HDCP_RX_SHA1_4_1               S5P_HDMI_BASE(0x0644)
 168 #define S5P_HDMI_HDCP_RX_SHA1_4_2               S5P_HDMI_BASE(0x0648)
 169 #define S5P_HDMI_HDCP_RX_SHA1_4_3               S5P_HDMI_BASE(0x064C)
 170
 171 #define S5P_HDMI_HDCP_RX_KSV_0_0                S5P_HDMI_BASE(0x0650)
 172 #define S5P_HDMI_HDCP_RX_KSV_0_1                S5P_HDMI_BASE(0x0654)
 173 #define S5P_HDMI_HDCP_RX_KSV_0_2                S5P_HDMI_BASE(0x0658)
 174 #define S5P_HDMI_HDCP_RX_KSV_0_3                S5P_HDMI_BASE(0x065C)
 175 #define S5P_HDMI_HDCP_RX_KSV_0_4                S5P_HDMI_BASE(0x0660)
 176
 177 #define S5P_HDMI_HDCP_KSV_LIST_CON              S5P_HDMI_BASE(0x0664)
 178 #define S5P_HDMI_HDCP_SHA_RESULT                S5P_HDMI_BASE(0x0670)
 179 #define S5P_HDMI_HDCP_CTRL1                     S5P_HDMI_BASE(0x0680)
 180 #define S5P_HDMI_HDCP_CTRL2                     S5P_HDMI_BASE(0x0684)
 181 #define S5P_HDMI_HDCP_CHECK_RESULT              S5P_HDMI_BASE(0x0690)
 182
 183 #define S5P_HDMI_HDCP_BKSV_0_0                  S5P_HDMI_BASE(0x06A0)
 184 #define S5P_HDMI_HDCP_BKSV_0_1                  S5P_HDMI_BASE(0x06A4)
 185 #define S5P_HDMI_HDCP_BKSV_0_2                  S5P_HDMI_BASE(0x06A8)
 186 #define S5P_HDMI_HDCP_BKSV_0_3                  S5P_HDMI_BASE(0x06AC)
 187 #define S5P_HDMI_HDCP_BKSV_1                    S5P_HDMI_BASE(0x06B0)
 188
 189 #define S5P_HDMI_HDCP_AKSV_0_0                  S5P_HDMI_BASE(0x06C0)
 190 #define S5P_HDMI_HDCP_AKSV_0_1                  S5P_HDMI_BASE(0x06C4)
 191 #define S5P_HDMI_HDCP_AKSV_0_2                  S5P_HDMI_BASE(0x06C8)
 192 #define S5P_HDMI_HDCP_AKSV_0_3                  S5P_HDMI_BASE(0x06CC)
 193 #define S5P_HDMI_HDCP_AKSV_1                    S5P_HDMI_BASE(0x06D0)
 194
 195 #define S5P_HDMI_HDCP_An_0_0                    S5P_HDMI_BASE(0x06E0)
 196 #define S5P_HDMI_HDCP_An_0_1                    S5P_HDMI_BASE(0x06E4)
 197 #define S5P_HDMI_HDCP_An_0_2                    S5P_HDMI_BASE(0x06E8)
 198 #define S5P_HDMI_HDCP_An_0_3                    S5P_HDMI_BASE(0x06EC)
 199 #define S5P_HDMI_HDCP_An_1_0                    S5P_HDMI_BASE(0x06F0)
 200 #define S5P_HDMI_HDCP_An_1_1                    S5P_HDMI_BASE(0x06F4)
 201 #define S5P_HDMI_HDCP_An_1_2                    S5P_HDMI_BASE(0x06F8)
 202 #define S5P_HDMI_HDCP_An_1_3                    S5P_HDMI_BASE(0x06FC)
 203
 204 #define S5P_HDMI_HDCP_BCAPS                     S5P_HDMI_BASE(0x0700)
 205 #define S5P_HDMI_HDCP_BSTATUS_0                 S5P_HDMI_BASE(0x0710)
 206 #define S5P_HDMI_HDCP_BSTATUS_1                 S5P_HDMI_BASE(0x0714)
 207 #define S5P_HDMI_HDCP_Ri_0                      S5P_HDMI_BASE(0x0740)
 208 #define S5P_HDMI_HDCP_Ri_1                      S5P_HDMI_BASE(0x0744)
 209
 210 #define S5P_HDMI_HDCP_I2C_INT                   S5P_HDMI_BASE(0x0780)
 211 #define S5P_HDMI_HDCP_AN_INT                    S5P_HDMI_BASE(0x0790)
 212 #define S5P_HDMI_HDCP_WDT_INT                   S5P_HDMI_BASE(0x07a0)
 213 #define S5P_HDMI_HDCP_RI_INT                    S5P_HDMI_BASE(0x07b0)
 214
 215 #define S5P_HDMI_HDCP_RI_COMPARE_0              S5P_HDMI_BASE(0x07d0)
 216 #define S5P_HDMI_HDCP_RI_COMPARE_1              S5P_HDMI_BASE(0x07d4)
 217 #define S5P_HDMI_HDCP_FRAME_COUNT               S5P_HDMI_BASE(0x07e0)
 218
 219 #define S5P_HDMI_GAMUT_CON                      S5P_HDMI_BASE(0x0500)
 220 #define S5P_HDMI_GAMUT_HEADER0                  S5P_HDMI_BASE(0x0504)
 221 #define S5P_HDMI_GAMUT_HEADER1                  S5P_HDMI_BASE(0x0508)
 222 #define S5P_HDMI_GAMUT_HEADER2                  S5P_HDMI_BASE(0x050c)
 223 #define S5P_HDMI_GAMUT_DATA                     S5P_HDMI_BASE(0x0510)
 224
 225 #define S5P_HDMI_DC_CONTROL                     S5P_HDMI_BASE(0x05C0)
 226 #define S5P_HDMI_VIDEO_PATTERN_GEN              S5P_HDMI_BASE(0x05C4)
 227 #define S5P_HDMI_HPD_GEN                        S5P_HDMI_BASE(0x05C8)
 228
 229
 230 #define S5P_HDMI_SPDIFIN_CLK_CTRL               S5P_HDMI_SPDIF_BASE(0x0000)
 231 #define S5P_HDMI_SPDIFIN_OP_CTRL                S5P_HDMI_SPDIF_BASE(0x0004)
 232 #define S5P_HDMI_SPDIFIN_IRQ_MASK               S5P_HDMI_SPDIF_BASE(0x0008)
 233 #define S5P_HDMI_SPDIFIN_IRQ_STATUS             S5P_HDMI_SPDIF_BASE(0x000C)
 234 #define S5P_HDMI_SPDIFIN_CONFIG_1               S5P_HDMI_SPDIF_BASE(0x0010)
 235 #define S5P_HDMI_SPDIFIN_CONFIG_2               S5P_HDMI_SPDIF_BASE(0x0014)
 236 #define S5P_HDMI_SPDIFIN_USER_VALUE_1           S5P_HDMI_SPDIF_BASE(0x0020)
 237 #define S5P_HDMI_SPDIFIN_USER_VALUE_2           S5P_HDMI_SPDIF_BASE(0x0024)
 238 #define S5P_HDMI_SPDIFIN_USER_VALUE_3           S5P_HDMI_SPDIF_BASE(0x0028)
 239 #define S5P_HDMI_SPDIFIN_USER_VALUE_4           S5P_HDMI_SPDIF_BASE(0x002C)
 240 #define S5P_HDMI_SPDIFIN_CH_STATUS_0_1          S5P_HDMI_SPDIF_BASE(0x0030)
 241 #define S5P_HDMI_SPDIFIN_CH_STATUS_0_2          S5P_HDMI_SPDIF_BASE(0x0034)
 242 #define S5P_HDMI_SPDIFIN_CH_STATUS_0_3          S5P_HDMI_SPDIF_BASE(0x0038)
 243 #define S5P_HDMI_SPDIFIN_CH_STATUS_0_4          S5P_HDMI_SPDIF_BASE(0x003C)
 244 #define S5P_HDMI_SPDIFIN_CH_STATUS_1            S5P_HDMI_SPDIF_BASE(0x0040)
 245 #define S5P_HDMI_SPDIFIN_FRAME_PERIOD_1         S5P_HDMI_SPDIF_BASE(0x0048)
 246 #define S5P_HDMI_SPDIFIN_FRAME_PERIOD_2         S5P_HDMI_SPDIF_BASE(0x004C)
 247 #define S5P_HDMI_SPDIFIN_Pc_INFO_1              S5P_HDMI_SPDIF_BASE(0x0050)
 248 #define S5P_HDMI_SPDIFIN_Pc_INFO_2              S5P_HDMI_SPDIF_BASE(0x0054)
 249 #define S5P_HDMI_SPDIFIN_Pd_INFO_1              S5P_HDMI_SPDIF_BASE(0x0058)
 250 #define S5P_HDMI_SPDIFIN_Pd_INFO_2              S5P_HDMI_SPDIF_BASE(0x005C)
 251 #define S5P_HDMI_SPDIFIN_DATA_BUF_0_1           S5P_HDMI_SPDIF_BASE(0x0060)
 252 #define S5P_HDMI_SPDIFIN_DATA_BUF_0_2           S5P_HDMI_SPDIF_BASE(0x0064)
 253 #define S5P_HDMI_SPDIFIN_DATA_BUF_0_3           S5P_HDMI_SPDIF_BASE(0x0068)
 254 #define S5P_HDMI_SPDIFIN_USER_BUF_0             S5P_HDMI_SPDIF_BASE(0x006C)
 255 #define S5P_HDMI_SPDIFIN_DATA_BUF_1_1           S5P_HDMI_SPDIF_BASE(0x0070)
 256 #define S5P_HDMI_SPDIFIN_DATA_BUF_1_2           S5P_HDMI_SPDIF_BASE(0x0074)
 257 #define S5P_HDMI_SPDIFIN_DATA_BUF_1_3           S5P_HDMI_SPDIF_BASE(0x0078)
 258 #define S5P_HDMI_SPDIFIN_USER_BUF_1             S5P_HDMI_SPDIF_BASE(0x007C)
 259
 260
 261 #define S5P_HDMI_I2S_CLK_CON                    S5P_HDMI_I2S_BASE(0x0000)
 262 #define S5P_HDMI_I2S_CON_1                      S5P_HDMI_I2S_BASE(0x0004)
 263 #define S5P_HDMI_I2S_CON_2                      S5P_HDMI_I2S_BASE(0x0008)
 264 #define S5P_HDMI_I2S_PIN_SEL_0                  S5P_HDMI_I2S_BASE(0x000C)
 265 #define S5P_HDMI_I2S_PIN_SEL_1                  S5P_HDMI_I2S_BASE(0x0010)
 266 #define S5P_HDMI_I2S_PIN_SEL_2                  S5P_HDMI_I2S_BASE(0x0014)
 267 #define S5P_HDMI_I2S_PIN_SEL_3                  S5P_HDMI_I2S_BASE(0x0018)
 268 #define S5P_HDMI_I2S_DSD_CON                    S5P_HDMI_I2S_BASE(0x001C)
 269 #define S5P_HDMI_I2S_MUX_CON                    S5P_HDMI_I2S_BASE(0x0020)
 270 #define S5P_HDMI_I2S_CH_ST_CON                  S5P_HDMI_I2S_BASE(0x0024)
 271 #define S5P_HDMI_I2S_CH_ST_0                    S5P_HDMI_I2S_BASE(0x0028)
 272 #define S5P_HDMI_I2S_CH_ST_1                    S5P_HDMI_I2S_BASE(0x002C)
 273 #define S5P_HDMI_I2S_CH_ST_2                    S5P_HDMI_I2S_BASE(0x0030)
 274 #define S5P_HDMI_I2S_CH_ST_3                    S5P_HDMI_I2S_BASE(0x0034)
 275 #define S5P_HDMI_I2S_CH_ST_4                    S5P_HDMI_I2S_BASE(0x0038)
 276 #define S5P_HDMI_I2S_CH_ST_SH_0                 S5P_HDMI_I2S_BASE(0x003C)
 277 #define S5P_HDMI_I2S_CH_ST_SH_1                 S5P_HDMI_I2S_BASE(0x0040)
 278 #define S5P_HDMI_I2S_CH_ST_SH_2                 S5P_HDMI_I2S_BASE(0x0044)
 279 #define S5P_HDMI_I2S_CH_ST_SH_3                 S5P_HDMI_I2S_BASE(0x0048)
 280 #define S5P_HDMI_I2S_CH_ST_SH_4                 S5P_HDMI_I2S_BASE(0x004C)
 281 #define S5P_HDMI_I2S_VD_DATA                    S5P_HDMI_I2S_BASE(0x0050)
 282 #define S5P_HDMI_I2S_MUX_CH                     S5P_HDMI_I2S_BASE(0x0054)
 283 #define S5P_HDMI_I2S_MUX_CUV                    S5P_HDMI_I2S_BASE(0x0058)
 284 #define S5P_HDMI_I2S_IRQ_MASK                   S5P_HDMI_I2S_BASE(0x005C)
 285 #define S5P_HDMI_I2S_IRQ_STATUS                 S5P_HDMI_I2S_BASE(0x0060)
 286 #define S5P_HDMI_I2S_CH0_L_0                    S5P_HDMI_I2S_BASE(0x0064)
 287 #define S5P_HDMI_I2S_CH0_L_1                    S5P_HDMI_I2S_BASE(0x0068)
 288 #define S5P_HDMI_I2S_CH0_L_2                    S5P_HDMI_I2S_BASE(0x006C)
 289 #define S5P_HDMI_I2S_CH0_L_3                    S5P_HDMI_I2S_BASE(0x0070)
 290 #define S5P_HDMI_I2S_CH0_R_0                    S5P_HDMI_I2S_BASE(0x0074)
 291 #define S5P_HDMI_I2S_CH0_R_1                    S5P_HDMI_I2S_BASE(0x0078)
 292 #define S5P_HDMI_I2S_CH0_R_2                    S5P_HDMI_I2S_BASE(0x007C)
 293 #define S5P_HDMI_I2S_CH0_R_3                    S5P_HDMI_I2S_BASE(0x0080)
 294 #define S5P_HDMI_I2S_CH1_L_0                    S5P_HDMI_I2S_BASE(0x0084)
 295 #define S5P_HDMI_I2S_CH1_L_1                    S5P_HDMI_I2S_BASE(0x0088)
 296 #define S5P_HDMI_I2S_CH1_L_2                    S5P_HDMI_I2S_BASE(0x008C)
 297 #define S5P_HDMI_I2S_CH1_L_3                    S5P_HDMI_I2S_BASE(0x0090)
 298 #define S5P_HDMI_I2S_CH1_R_0                    S5P_HDMI_I2S_BASE(0x0094)
 299 #define S5P_HDMI_I2S_CH1_R_1                    S5P_HDMI_I2S_BASE(0x0098)
 300 #define S5P_HDMI_I2S_CH1_R_2                    S5P_HDMI_I2S_BASE(0x009C)
 301 #define S5P_HDMI_I2S_CH1_R_3                    S5P_HDMI_I2S_BASE(0x00A0)
 302 #define S5P_HDMI_I2S_CH2_L_0                    S5P_HDMI_I2S_BASE(0x00A4)
 303 #define S5P_HDMI_I2S_CH2_L_1                    S5P_HDMI_I2S_BASE(0x00A8)
 304 #define S5P_HDMI_I2S_CH2_L_2                    S5P_HDMI_I2S_BASE(0x00AC)
 305 #define S5P_HDMI_I2S_CH2_L_3                    S5P_HDMI_I2S_BASE(0x00B0)
 306 #define S5P_HDMI_I2S_CH2_R_0                    S5P_HDMI_I2S_BASE(0x00B4)
 307 #define S5P_HDMI_I2S_CH2_R_1                    S5P_HDMI_I2S_BASE(0x00B8)
 308 #define S5P_HDMI_I2S_CH2_R_2                    S5P_HDMI_I2S_BASE(0x00BC)
 309 #define S5P_HDMI_I2S_Ch2_R_3                    S5P_HDMI_I2S_BASE(0x00C0)
 310 #define S5P_HDMI_I2S_CH3_L_0                    S5P_HDMI_I2S_BASE(0x00C4)
 311 #define S5P_HDMI_I2S_CH3_L_1                    S5P_HDMI_I2S_BASE(0x00C8)
 312 #define S5P_HDMI_I2S_CH3_L_2                    S5P_HDMI_I2S_BASE(0x00CC)
 313 #define S5P_HDMI_I2S_CH3_R_0                    S5P_HDMI_I2S_BASE(0x00D0)
 314 #define S5P_HDMI_I2S_CH3_R_1                    S5P_HDMI_I2S_BASE(0x00D4)
 315 #define S5P_HDMI_I2S_CH3_R_2                    S5P_HDMI_I2S_BASE(0x00D8)
 316 #define S5P_HDMI_I2S_CUV_L_R                    S5P_HDMI_I2S_BASE(0x00DC)
 317
 318
 319 #define S5P_HDMI_TG_CMD                         S5P_HDMI_TG_BASE(0x0000)
 320 #define S5P_HDMI_TG_H_FSZ_L                     S5P_HDMI_TG_BASE(0x0018)
 321 #define S5P_HDMI_TG_H_FSZ_H                     S5P_HDMI_TG_BASE(0x001C)
 322 #define S5P_HDMI_TG_HACT_ST_L                   S5P_HDMI_TG_BASE(0x0020)
 323 #define S5P_HDMI_TG_HACT_ST_H                   S5P_HDMI_TG_BASE(0x0024)
 324 #define S5P_HDMI_TG_HACT_SZ_L                   S5P_HDMI_TG_BASE(0x0028)
 325 #define S5P_HDMI_TG_HACT_SZ_H                   S5P_HDMI_TG_BASE(0x002C)
 326 #define S5P_HDMI_TG_V_FSZ_L                     S5P_HDMI_TG_BASE(0x0030)
 327 #define S5P_HDMI_TG_V_FSZ_H                     S5P_HDMI_TG_BASE(0x0034)
 328 #define S5P_HDMI_TG_VSYNC_L                     S5P_HDMI_TG_BASE(0x0038)
 329 #define S5P_HDMI_TG_VSYNC_H                     S5P_HDMI_TG_BASE(0x003C)
 330 #define S5P_HDMI_TG_VSYNC2_L                    S5P_HDMI_TG_BASE(0x0040)
 331 #define S5P_HDMI_TG_VSYNC2_H                    S5P_HDMI_TG_BASE(0x0044)
 332 #define S5P_HDMI_TG_VACT_ST_L                   S5P_HDMI_TG_BASE(0x0048)
 333 #define S5P_HDMI_TG_VACT_ST_H                   S5P_HDMI_TG_BASE(0x004C)
 334 #define S5P_HDMI_TG_VACT_SZ_L                   S5P_HDMI_TG_BASE(0x0050)
 335 #define S5P_HDMI_TG_VACT_SZ_H                   S5P_HDMI_TG_BASE(0x0054)
 336 #define S5P_HDMI_TG_FIELD_CHG_L                 S5P_HDMI_TG_BASE(0x0058)
 337 #define S5P_HDMI_TG_FIELD_CHG_H                 S5P_HDMI_TG_BASE(0x005C)
 338 #define S5P_HDMI_TG_VACT_ST2_L                  S5P_HDMI_TG_BASE(0x0060)
 339 #define S5P_HDMI_TG_VACT_ST2_H                  S5P_HDMI_TG_BASE(0x0064)
 340
 341 #define S5P_HDMI_TG_VSYNC_TOP_HDMI_L            S5P_HDMI_TG_BASE(0x0078)
 342 #define S5P_HDMI_TG_VSYNC_TOP_HDMI_H            S5P_HDMI_TG_BASE(0x007C)
 343 #define S5P_HDMI_TG_VSYNC_BOT_HDMI_L            S5P_HDMI_TG_BASE(0x0080)
 344 #define S5P_HDMI_TG_VSYNC_BOT_HDMI_H            S5P_HDMI_TG_BASE(0x0084)
 345 #define S5P_HDMI_TG_FIELD_TOP_HDMI_L            S5P_HDMI_TG_BASE(0x0088)
 346 #define S5P_HDMI_TG_FIELD_TOP_HDMI_H            S5P_HDMI_TG_BASE(0x008C)
 347 #define S5P_HDMI_TG_FIELD_BOT_HDMI_L            S5P_HDMI_TG_BASE(0x0090)
 348 #define S5P_HDMI_TG_FIELD_BOT_HDMI_H            S5P_HDMI_TG_BASE(0x0094)
 349
 350 #define S5P_HDMI_EFUSE_CTRL                     S5P_HDMI_EFUSE_BASE(0x0000)
 351 #define S5P_HDMI_EFUSE_STATUS                   S5P_HDMI_EFUSE_BASE(0x0004)
 352 #define S5P_HDMI_EFUSE_ADDR_WIDTH               S5P_HDMI_EFUSE_BASE(0x0008)
 353 #define S5P_HDMI_EFUSE_SIGDEV_ASSERT            S5P_HDMI_EFUSE_BASE(0x000c)
 354 #define S5P_HDMI_EFUSE_SIGDEV_DEASSERT          S5P_HDMI_EFUSE_BASE(0x0010)
 355 #define S5P_HDMI_EFUSE_PRCHG_ASSERT             S5P_HDMI_EFUSE_BASE(0x0014)
 356 #define S5P_HDMI_EFUSE_PRCHG_DEASSERT           S5P_HDMI_EFUSE_BASE(0x0018)
 357 #define S5P_HDMI_EFUSE_FSET_ASSERT              S5P_HDMI_EFUSE_BASE(0x001c)
 358 #define S5P_HDMI_EFUSE_FSET_DEASSERT            S5P_HDMI_EFUSE_BASE(0x0020)
 359 #define S5P_HDMI_EFUSE_SENSING                  S5P_HDMI_EFUSE_BASE(0x0024)
 360 #define S5P_HDMI_EFUSE_SCK_ASSERT               S5P_HDMI_EFUSE_BASE(0x0028)
 361 #define S5P_HDMI_EFUSE_SCK_DEASSERT             S5P_HDMI_EFUSE_BASE(0x002c)
 362 #define S5P_HDMI_EFUSE_SDOUT_OFFSET             S5P_HDMI_EFUSE_BASE(0x0030)
 363 #define S5P_HDMI_EFUSE_READ_OFFSET              S5P_HDMI_EFUSE_BASE(0x0034)
 364
 365 #define S5P_HDMI_AUI_SZ                         5
 366 #define S5P_HDMI_GCP_SZ                         3
 367 #define S5P_HDMI_SPD_SZ                         28
 368 #define S5P_HDMI_AVI_SZ                         13
 369 #define S5P_HDMI_MPG_SZ                         5
 370 #define S5P_HDMI_GMU_SX                         28
 371 #define S5P_HDMI_ISRC_SZ                        16
 372 #define S5P_HDMI_ACP_SZ                         17
 373
 374 /*
 375  * Bit definition part
 376  */
 377
 378 /* Control Register */
 379
 380 /* INTC_CON */
 381 #define S5P_HDMI_INTC_ACT_HI                    (1 << 7)
 382 #define S5P_HDMI_INTC_ACT_LOW                   (0 << 7)
 383 #define S5P_HDMI_INTC_EN_GLOBAL                 (1 << 6)
 384 #define S5P_HDMI_INTC_DIS_GLOBAL                (0 << 6)
 385 #define S5P_HDMI_INTC_EN_I2S                    (1 << 5)
 386 #define S5P_HDMI_INTC_DIS_I2S                   (0 << 5)
 387 #define S5P_HDMI_INTC_EN_CEC                    (1 << 4)
 388 #define S5P_HDMI_INTC_DIS_CEC                   (0 << 4)
 389 #define S5P_HDMI_INTC_EN_HPD_PLUG               (1 << 3)
 390 #define S5P_HDMI_INTC_DIS_HPD_PLUG              (0 << 3)
 391 #define S5P_HDMI_INTC_EN_HPD_UNPLUG             (1 << 2)
 392 #define S5P_HDMI_INTC_DIS_HPD_UNPLUG            (0 << 2)
 393 #define S5P_HDMI_INTC_EN_SPDIF                  (1 << 1)
 394 #define S5P_HDMI_INTC_DIS_SPDIF                 (0 << 1)
 395 #define S5P_HDMI_INTC_EN_HDCP                   (1 << 0)
 396 #define S5P_HDMI_INTC_DIS_HDCP                  (0 << 0)
 397
 398 /* INTC_FLAG */
 399 #define S5P_HDMI_INTC_FLAG_I2S                  (1 << 5)
 400 #define S5P_HDMI_INTC_FLAG_CEC                  (1 << 4)
 401 #define S5P_HDMI_INTC_FLAG_HPD_PLUG             (1 << 3)
 402 #define S5P_HDMI_INTC_FLAG_HPD_UNPLUG           (1 << 2)
 403 #define S5P_HDMI_INTC_FLAG_SPDIF                (1 << 1)
 404 #define S5P_HDMI_INTC_FLAG_HDCP                 (1 << 0)
 405
 406 /* HDCP_KEY_LOAD_DONE */
 407 #define S5P_HDMI_HDCP_KEY_LOAD_DONE             (1 << 0)
 408
 409 /* HPD_STATUS */
 410 #define S5P_HDMI_HPD_PLUGED                     (1 << 0)
 411
 412 /* AUDIO_CLKSEL */
 413 #define S5P_HDMI_AUDIO_SPDIF_CLK                (1 << 0)
 414 #define S5P_HDMI_AUDIO_PCLK                     (0 << 0)
 415
 416 /* HDMI_PHY_RSTOUT */
 417 #define S5P_HDMI_PHY_SW_RSTOUT                  (1 << 0)
 418
 419 /* HDMI_PHY_VPLL */
 420 #define S5P_HDMI_PHY_VPLL_LOCK                  (1 << 7)
 421 #define S5P_HDMI_PHY_VPLL_CODE_MASK             (0x7 << 0)
 422
 423 /* HDMI_PHY_CMU */
 424 #define S5P_HDMI_PHY_CMU_LOCK                   (1 << 7)
 425 #define S5P_HDMI_PHY_CMU_CODE_MASK              (0x7 << 0)
 426
 427 /* HDMI_CORE_RSTOUT */
 428 #define S5P_HDMI_CORE_SW_RSTOUT                 (1 << 0)
 429
 430
 431 /* Core Register */
 432
 433 /* HDMI_CON_0 */
 434 #define S5P_HDMI_BLUE_SCR_EN                    (1 << 5)
 435 #define S5P_HDMI_BLUE_SCR_DIS                   (0 << 5)
 436 #define S5P_HDMI_ENC_OPTION                     (1 << 4)
 437 #define S5P_HDMI_ASP_EN                         (1 << 2)
 438 #define S5P_HDMI_ASP_DIS                        (0 << 2)
 439 #define S5P_HDMI_PWDN_ENB_NORMAL                (1 << 1)
 440 #define S5P_HDMI_PWDN_ENB_PD                    (0 << 1)
 441 #define S5P_HDMI_EN                             (1 << 0)
 442 #define S5P_HDMI_DIS                            (~(1 << 0))
 443
 444 /* HDMI_CON_1 */
 445 #define S5P_HDMI_PX_LMT_CTRL_BYPASS             (0 << 5)
 446 #define S5P_HDMI_PX_LMT_CTRL_RGB                (1 << 5)
 447 #define S5P_HDMI_PX_LMT_CTRL_YPBPR              (2 << 5)
 448 #define S5P_HDMI_PX_LMT_CTRL_RESERVED           (3 << 5)
 449 #define S5P_HDMI_CON_PXL_REP_RATIO_MASK         (1 << 1 | 1 << 0)
 450 #define S5P_HDMI_DOUBLE_PIXEL_REPETITION        (0x01)
 451
 452 /* HDMI_CON_2 */
 453 #define S5P_HDMI_VID_PREAMBLE_EN                (0 << 5)
 454 #define S5P_HDMI_VID_PREAMBLE_DIS               (1 << 5)
 455 #define S5P_HDMI_GUARD_BAND_EN                  (0 << 1)
 456 #define S5P_HDMI_GUARD_BAND_DIS                 (1 << 1)
 457
 458 /* STATUS */
 459 #define S5P_HDMI_AUTHEN_ACK_AUTH                (1 << 7)
 460 #define S5P_HDMI_AUTHEN_ACK_NOT                 (0 << 7)
 461 #define S5P_HDMI_AUD_FIFO_OVF_FULL              (1 << 6)
 462 #define S5P_HDMI_AUD_FIFO_OVF_NOT               (0 << 6)
 463 #define S5P_HDMI_UPDATE_RI_INT_OCC              (1 << 4)
 464 #define S5P_HDMI_UPDATE_RI_INT_NOT              (0 << 4)
 465 #define S5P_HDMI_UPDATE_RI_INT_CLEAR            (1 << 4)
 466 #define S5P_HDMI_UPDATE_PJ_INT_OCC              (1 << 3)
 467 #define S5P_HDMI_UPDATE_PJ_INT_NOT              (0 << 3)
 468 #define S5P_HDMI_UPDATE_PJ_INT_CLEAR            (1 << 3)
 469 #define S5P_HDMI_WRITE_INT_OCC                  (1 << 2)
 470 #define S5P_HDMI_WRITE_INT_NOT                  (0 << 2)
 471 #define S5P_HDMI_WRITE_INT_CLEAR                (1 << 2)
 472 #define S5P_HDMI_WATCHDOG_INT_OCC               (1 << 1)
 473 #define S5P_HDMI_WATCHDOG_INT_NOT               (0 << 1)
 474 #define S5P_HDMI_WATCHDOG_INT_CLEAR             (1 << 1)
 475 #define S5P_HDMI_WTFORACTIVERX_INT_OCC          (1)
 476 #define S5P_HDMI_WTFORACTIVERX_INT_NOT          (0)
 477 #define S5P_HDMI_WTFORACTIVERX_INT_CLEAR        (1)
 478
 479 /* PHY_STATUS */
 480 #define S5P_HDMI_PHY_STATUS_READY               (1)
 481
 482 /* STATUS_EN */
 483 #define S5P_HDMI_AUD_FIFO_OVF_EN                (1 << 6)
 484 #define S5P_HDMI_AUD_FIFO_OVF_DIS               (0 << 6)
 485 #define S5P_HDMI_UPDATE_RI_INT_EN               (1 << 4)
 486 #define S5P_HDMI_UPDATE_RI_INT_DIS              (0 << 4)
 487 #define S5P_HDMI_UPDATE_PJ_INT_EN               (1 << 3)
 488 #define S5P_HDMI_UPDATE_PJ_INT_DIS              (0 << 3)
 489 #define S5P_HDMI_WRITE_INT_EN                   (1 << 2)
 490 #define S5P_HDMI_WRITE_INT_DIS                  (0 << 2)
 491 #define S5P_HDMI_WATCHDOG_INT_EN                (1 << 1)
 492 #define S5P_HDMI_WATCHDOG_INT_DIS               (0 << 1)
 493 #define S5P_HDMI_WTFORACTIVERX_INT_EN           (1)
 494 #define S5P_HDMI_WTFORACTIVERX_INT_DIS          (0)
 495 #define S5P_HDMI_INT_EN_ALL                     (S5P_HDMI_UPDATE_RI_INT_EN|\
 496                                                 S5P_HDMI_UPDATE_PJ_INT_DIS|\
 497                                                 S5P_HDMI_WRITE_INT_EN|\
 498                                                 S5P_HDMI_WATCHDOG_INT_EN|\
 499                                                 S5P_HDMI_WTFORACTIVERX_INT_EN)
 500 #define S5P_HDMI_INT_DIS_ALL                    (~0x1F)
 501
 502 /* HPD */
 503 #define S5P_HDMI_SW_HPD_PLUGGED                 (1 << 1)
 504 #define S5P_HDMI_SW_HPD_UNPLUGGED               (0 << 1)
 505 #define S5P_HDMI_HPD_SEL_I_HPD                  (1)
 506 #define S5P_HDMI_HPD_SEL_SW_HPD                 (0)
 507
 508 /* MODE_SEL */
 509 #define S5P_HDMI_MODE_EN                        (1 << 1)
 510 #define S5P_HDMI_MODE_DIS                       (0 << 1)
 511 #define S5P_HDMI_DVI_MODE_EN                    (1)
 512 #define S5P_HDMI_DVI_MODE_DIS                   (0)
 513
 514 /* ENC_EN */
 515 #define S5P_HDMI_HDCP_ENC_ENABLE                (1)
 516 #define S5P_HDMI_HDCP_ENC_DISABLE               (0)
 517
 518
 519 /* Video Related Register */
 520
 521 /* BLUESCREEN_0/1/2 */
 522
 523 /* HDMI_YMAX/YMIN/CMAX/CMIN */
 524
 525 /* H_BLANK_0/1 */
 526
 527 /* V_BLANK_0/1/2 */
 528
 529 /* H_V_LINE_0/1/2 */
 530
 531 /* VSYNC_POL */
 532 #define S5P_HDMI_V_SYNC_POL_ACT_LOW             (1)
 533 #define S5P_HDMI_V_SYNC_POL_ACT_HIGH            (0)
 534
 535 /* INT_PRO_MODE */
 536 #define S5P_HDMI_INTERLACE_MODE                 (1)
 537 #define S5P_HDMI_PROGRESSIVE_MODE               (0)
 538
 539 /* V_BLANK_F_0/1/2 */
 540
 541 /* H_SYNC_GEN_0/1/2 */
 542
 543 /* V_SYNC_GEN1_0/1/2 */
 544
 545 /* V_SYNC_GEN2_0/1/2 */
 546
 547 /* V_SYNC_GEN3_0/1/2 */
 548
 549 /* Audio Related Packet Register */
 550
 551 /* ASP_CON */
 552 #define S5P_HDMI_AUD_DST_DOUBLE                 (1 << 7)
 553 #define S5P_HDMI_AUD_NO_DST_DOUBLE              (0 << 7)
 554 #define S5P_HDMI_AUD_TYPE_SAMPLE                (0 << 5)
 555 #define S5P_HDMI_AUD_TYPE_ONE_BIT               (1 << 5)
 556 #define S5P_HDMI_AUD_TYPE_HBR                   (2 << 5)
 557 #define S5P_HDMI_AUD_TYPE_DST                   (3 << 5)
 558 #define S5P_HDMI_AUD_MODE_TWO_CH                (0 << 4)
 559 #define S5P_HDMI_AUD_MODE_MULTI_CH              (1 << 4)
 560 #define S5P_HDMI_AUD_SP_AUD3_EN                 (1 << 3)
 561 #define S5P_HDMI_AUD_SP_AUD2_EN                 (1 << 2)
 562 #define S5P_HDMI_AUD_SP_AUD1_EN                 (1 << 1)
 563 #define S5P_HDMI_AUD_SP_AUD0_EN                 (1 << 0)
 564 #define S5P_HDMI_AUD_SP_ALL_DIS                 (0 << 0)
 565
 566 #define S5P_HDMI_AUD_SET_SP_PRE(x)              ((x) & 0xF)
 567
 568 /* ASP_SP_FLAT */
 569 #define S5P_HDMI_ASP_SP_FLAT_AUD_SAMPLE         (0)
 570
 571 /* ASP_CHCFG0/1/2/3 */
 572 #define S5P_HDMI_SPK3R_SEL_I_PCM0L              (0 << 27)
 573 #define S5P_HDMI_SPK3R_SEL_I_PCM0R              (1 << 27)
 574 #define S5P_HDMI_SPK3R_SEL_I_PCM1L              (2 << 27)
 575 #define S5P_HDMI_SPK3R_SEL_I_PCM1R              (3 << 27)
 576 #define S5P_HDMI_SPK3R_SEL_I_PCM2L              (4 << 27)
 577 #define S5P_HDMI_SPK3R_SEL_I_PCM2R              (5 << 27)
 578 #define S5P_HDMI_SPK3R_SEL_I_PCM3L              (6 << 27)
 579 #define S5P_HDMI_SPK3R_SEL_I_PCM3R              (7 << 27)
 580 #define S5P_HDMI_SPK3L_SEL_I_PCM0L              (0 << 24)
 581 #define S5P_HDMI_SPK3L_SEL_I_PCM0R              (1 << 24)
 582 #define S5P_HDMI_SPK3L_SEL_I_PCM1L              (2 << 24)
 583 #define S5P_HDMI_SPK3L_SEL_I_PCM1R              (3 << 24)
 584 #define S5P_HDMI_SPK3L_SEL_I_PCM2L              (4 << 24)
 585 #define S5P_HDMI_SPK3L_SEL_I_PCM2R              (5 << 24)
 586 #define S5P_HDMI_SPK3L_SEL_I_PCM3L              (6 << 24)
 587 #define S5P_HDMI_SPK3L_SEL_I_PCM3R              (7 << 24)
 588 #define S5P_HDMI_SPK2R_SEL_I_PCM0L              (0 << 19)
 589 #define S5P_HDMI_SPK2R_SEL_I_PCM0R              (1 << 19)
 590 #define S5P_HDMI_SPK2R_SEL_I_PCM1L              (2 << 19)
 591 #define S5P_HDMI_SPK2R_SEL_I_PCM1R              (3 << 19)
 592 #define S5P_HDMI_SPK2R_SEL_I_PCM2L              (4 << 19)
 593 #define S5P_HDMI_SPK2R_SEL_I_PCM2R              (5 << 19)
 594 #define S5P_HDMI_SPK2R_SEL_I_PCM3L              (6 << 19)
 595 #define S5P_HDMI_SPK2R_SEL_I_PCM3R              (7 << 19)
 596 #define S5P_HDMI_SPK2L_SEL_I_PCM0L              (0 << 16)
 597 #define S5P_HDMI_SPK2L_SEL_I_PCM0R              (1 << 16)
 598 #define S5P_HDMI_SPK2L_SEL_I_PCM1L              (2 << 16)
 599 #define S5P_HDMI_SPK2L_SEL_I_PCM1R              (3 << 16)
 600 #define S5P_HDMI_SPK2L_SEL_I_PCM2L              (4 << 16)
 601 #define S5P_HDMI_SPK2L_SEL_I_PCM2R              (5 << 16)
 602 #define S5P_HDMI_SPK2L_SEL_I_PCM3L              (6 << 16)
 603 #define S5P_HDMI_SPK2L_SEL_I_PCM3R              (7 << 16)
 604 #define S5P_HDMI_SPK1R_SEL_I_PCM0L              (0 << 11)
 605 #define S5P_HDMI_SPK1R_SEL_I_PCM0R              (1 << 11)
 606 #define S5P_HDMI_SPK1R_SEL_I_PCM1L              (2 << 11)
 607 #define S5P_HDMI_SPK1R_SEL_I_PCM1R              (3 << 11)
 608 #define S5P_HDMI_SPK1R_SEL_I_PCM2L              (4 << 11)
 609 #define S5P_HDMI_SPK1R_SEL_I_PCM2R              (5 << 11)
 610 #define S5P_HDMI_SPK1R_SEL_I_PCM3L              (6 << 11)
 611 #define S5P_HDMI_SPK1R_SEL_I_PCM3R              (7 << 11)
 612 #define S5P_HDMI_SPK1L_SEL_I_PCM0L              (0 << 8)
 613 #define S5P_HDMI_SPK1L_SEL_I_PCM0R              (1 << 8)
 614 #define S5P_HDMI_SPK1L_SEL_I_PCM1L              (2 << 8)
 615 #define S5P_HDMI_SPK1L_SEL_I_PCM1R              (3 << 8)
 616 #define S5P_HDMI_SPK1L_SEL_I_PCM2L              (4 << 8)
 617 #define S5P_HDMI_SPK1L_SEL_I_PCM2R              (5 << 8)
 618 #define S5P_HDMI_SPK1L_SEL_I_PCM3L              (6 << 8)
 619 #define S5P_HDMI_SPK1L_SEL_I_PCM3R              (7 << 8)
 620 #define S5P_HDMI_SPK0R_SEL_I_PCM0L              (0 << 3)
 621 #define S5P_HDMI_SPK0R_SEL_I_PCM0R              (1 << 3)
 622 #define S5P_HDMI_SPK0R_SEL_I_PCM1L              (2 << 3)
 623 #define S5P_HDMI_SPK0R_SEL_I_PCM1R              (3 << 3)
 624 #define S5P_HDMI_SPK0R_SEL_I_PCM2L              (4 << 3)
 625 #define S5P_HDMI_SPK0R_SEL_I_PCM2R              (5 << 3)
 626 #define S5P_HDMI_SPK0R_SEL_I_PCM3L              (6 << 3)
 627 #define S5P_HDMI_SPK0R_SEL_I_PCM3R              (7 << 3)
 628 #define S5P_HDMI_SPK0L_SEL_I_PCM0L              (0)
 629 #define S5P_HDMI_SPK0L_SEL_I_PCM0R              (1)
 630 #define S5P_HDMI_SPK0L_SEL_I_PCM1L              (2)
 631 #define S5P_HDMI_SPK0L_SEL_I_PCM1R              (3)
 632 #define S5P_HDMI_SPK0L_SEL_I_PCM2L              (4)
 633 #define S5P_HDMI_SPK0L_SEL_I_PCM2R              (5)
 634 #define S5P_HDMI_SPK0L_SEL_I_PCM3L              (6)
 635 #define S5P_HDMI_SPK0L_SEL_I_PCM3R              (7)
 636
 637 /* ACR_CON */
 638 #define S5P_HDMI_ALT_CTS_RATE_CTS_1             (0 << 3)
 639 #define S5P_HDMI_ALT_CTS_RATE_CTS_11            (1 << 3)
 640 #define S5P_HDMI_ALT_CTS_RATE_CTS_21            (2 << 3)
 641 #define S5P_HDMI_ALT_CTS_RATE_CTS_31            (3 << 3)
 642 #define S5P_HDMI_ACR_TX_MODE_NO_TX              (0)
 643 #define S5P_HDMI_ACR_TX_MODE_TX_ONCE            (1)
 644 #define S5P_HDMI_ACR_TX_MODE_TXCNT_VBI          (2)
 645 #define S5P_HDMI_ACR_TX_MODE_TX_VPC             (3)
 646 #define S5P_HDMI_ACR_TX_MODE_MESURE_CTS         (4)
 647
 648 /* ACR_MCTS0/1/2 */
 649
 650 /* ACR_CTS0/1/2 */
 651
 652 /* ACR_N0/1/2 */
 653
 654 /* ACR_LSB2 */
 655 #define S5P_HDMI_ACR_LSB2_MASK                  (0xFF)
 656
 657 /* ACR_TXCNT */
 658 #define S5P_HDMI_ACR_TXCNT_MASK                 (0x1F)
 659
 660 /* ACR_TXINTERNAL */
 661 #define S5P_HDMI_ACR_TX_INTERNAL_MASK           (0xFF)
 662
 663 /* ACR_CTS_OFFSET */
 664 #define S5P_HDMI_ACR_CTS_OFFSET_MASK            (0xFF)
 665
 666 /* GCP_CON */
 667 #define S5P_HDMI_GCP_CON_EN_1ST_VSYNC           (1 << 3)
 668 #define S5P_HDMI_GCP_CON_EN_2ST_VSYNC           (1 << 2)
 669 #define S5P_HDMI_GCP_CON_TRANS_EVERY_VSYNC      (2)
 670 #define S5P_HDMI_GCP_CON_NO_TRAN                (0)
 671 #define S5P_HDMI_GCP_CON_TRANS_ONCE             (1)
 672 #define S5P_HDMI_GCP_CON_TRANS_EVERY_VSYNC      (2)
 673
 674 /* GCP_BYTE1 */
 675 #define S5P_HDMI_GCP_BYTE1_MASK                 (0xFF)
 676
 677 /* GCP_BYTE2 */
 678 #define S5P_HDMI_GCP_BYTE2_PP_MASK              (0xF << 4)
 679 #define S5P_HDMI_GCP_24BPP                      (1 << 2)
 680 #define S5P_HDMI_GCP_30BPP                      (1 << 0 | 1 << 2)
 681 #define S5P_HDMI_GCP_36BPP                      (1 << 1 | 1 << 2)
 682 #define S5P_HDMI_GCP_48BPP                      (1 << 0 | 1 << 1 | 1 << 2)
 683
 684
 685 /* GCP_BYTE3 */
 686 #define S5P_HDMI_GCP_BYTE3_MASK                 (0xFF)
 687
 688
 689 /* ACP Packet Register */
 690
 691 /* ACP_CON */
 692 #define S5P_HDMI_ACP_FR_RATE_MASK               (0x1F << 3)
 693 #define S5P_HDMI_ACP_CON_NO_TRAN                (0)
 694 #define S5P_HDMI_ACP_CON_TRANS_ONCE             (1)
 695 #define S5P_HDMI_ACP_CON_TRANS_EVERY_VSYNC      (2)
 696
 697 /* ACP_TYPE */
 698 #define S5P_HDMI_ACP_TYPE_MASK                  (0xFF)
 699
 700 /* ACP_DATA00~16 */
 701 #define S5P_HDMI_ACP_DATA_MASK                  (0xFF)
 702
 703
 704 /* ISRC1/2 Packet Register */
 705
 706 /* ISRC_CON */
 707 #define S5P_HDMI_ISRC_FR_RATE_MASK              (0x1F << 3)
 708 #define S5P_HDMI_ISRC_EN                        (1 << 2)
 709 #define S5P_HDMI_ISRC_DIS                       (0 << 2)
 710
 711
 712 /* ISRC1_HEADER1 */
 713 #define S5P_HDMI_ISRC1_HEADER_MASK              (0xFF)
 714
 715 /* ISRC1_DATA 00~15 */
 716 #define S5P_HDMI_ISRC1_DATA_MASK                (0xFF)
 717
 718 /* ISRC2_DATA 00~15 */
 719 #define S5P_HDMI_ISRC2_DATA_MASK                (0xFF)
 720
 721
 722 /* AVI InfoFrame Register */
 723
 724 /* AVI_CON */
 725
 726 /* AVI_CHECK_SUM */
 727
 728 /* AVI_DATA01~13 */
 729 #define S5P_HDMI_AVI_PIXEL_REPETITION_DOUBLE    (1<<0)
 730 #define S5P_HDMI_AVI_PICTURE_ASPECT_4_3         (1<<4)
 731 #define S5P_HDMI_AVI_PICTURE_ASPECT_16_9        (1<<5)
 732
 733
 734 /* Audio InfoFrame Register */
 735
 736 /* AUI_CON */
 737
 738 /* AUI_CHECK_SUM */
 739
 740 /* AUI_DATA1~5 */
 741
 742
 743 /* MPEG Source InfoFrame registers */
 744
 745 /* MPG_CON */
 746
 747 /* HDMI_MPG_CHECK_SUM */
 748
 749 /* MPG_DATA1~5 */
 750
 751 /* Source Product Descriptor Infoframe registers */
 752
 753 /* SPD_CON */
 754
 755 /* SPD_HEADER0/1/2 */
 756
 757 /* SPD_DATA0~27 */
 758
 759 /* HDCP Register */
 760
 761 /* HDCP_SHA1_00~19 */
 762
 763 /* HDCP_KSV_LIST_0~4 */
 764
 765 /* HDCP_KSV_LIST_CON */
 766 #define S5P_HDMI_HDCP_KSV_WRITE_DONE            (0x1 << 3)
 767 #define S5P_HDMI_HDCP_KSV_LIST_EMPTY            (0x1 << 2)
 768 #define S5P_HDMI_HDCP_KSV_END                   (0x1 << 1)
 769 #define S5P_HDMI_HDCP_KSV_READ                  (0x1 << 0)
 770
 771 /* HDCP_CTRL1 */
 772 #define S5P_HDMI_HDCP_EN_PJ_EN                  (1 << 4)
 773 #define S5P_HDMI_HDCP_EN_PJ_DIS                 (~(1 << 4))
 774 #define S5P_HDMI_HDCP_SET_REPEATER_TIMEOUT      (1 << 2)
 775 #define S5P_HDMI_HDCP_CLEAR_REPEATER_TIMEOUT    (~(1 << 2))
 776 #define S5P_HDMI_HDCP_CP_DESIRED_EN             (1 << 1)
 777 #define S5P_HDMI_HDCP_CP_DESIRED_DIS            (~(1 << 1))
 778 #define S5P_HDMI_HDCP_ENABLE_1_1_FEATURE_EN     (1)
 779 #define S5P_HDMI_HDCP_ENABLE_1_1_FEATURE_DIS    (~(1))
 780
 781 /* HDCP_CHECK_RESULT */
 782 #define S5P_HDMI_HDCP_Pi_MATCH_RESULT_Y         ((0x1 << 3) | (0x1 << 2))
 783 #define S5P_HDMI_HDCP_Pi_MATCH_RESULT_N         ((0x1 << 3) | (0x0 << 2))
 784 #define S5P_HDMI_HDCP_Ri_MATCH_RESULT_Y         ((0x1 << 1) | (0x1 << 0))
 785 #define S5P_HDMI_HDCP_Ri_MATCH_RESULT_N         ((0x1 << 1) | (0x0 << 0))
 786 #define S5P_HDMI_HDCP_CLR_ALL_RESULTS           (0)
 787
 788 /* HDCP_BKSV0~4 */
 789 /* HDCP_AKSV0~4 */
 790
 791 /* HDCP_BCAPS */
 792 #define S5P_HDMI_HDCP_BCAPS_REPEATER            (1 << 6)
 793 #define S5P_HDMI_HDCP_BCAPS_READY               (1 << 5)
 794 #define S5P_HDMI_HDCP_BCAPS_FAST                (1 << 4)
 795 #define S5P_HDMI_HDCP_BCAPS_1_1_FEATURES        (1 << 1)
 796 #define S5P_HDMI_HDCP_BCAPS_FAST_REAUTH         (1)
 797
 798 /* HDCP_BSTATUS_0/1 */
 799 /* HDCP_Ri_0/1 */
 800 /* HDCP_I2C_INT */
 801 /* HDCP_AN_INT */
 802 /* HDCP_WATCHDOG_INT */
 803 /* HDCP_RI_INT/1 */
 804 /* HDCP_Ri_Compare_0 */
 805 /* HDCP_Ri_Compare_1 */
 806 /* HDCP_Frame_Count */
 807
 808
 809 /* Gamut Metadata Packet Register */
 810
 811 /* GAMUT_CON */
 812 /* GAMUT_HEADER0 */
 813 /* GAMUT_HEADER1 */
 814 /* GAMUT_HEADER2 */
 815 /* GAMUT_METADATA0~27 */
 816
 817
 818 /* Video Mode Register */
 819
 820 /* VIDEO_PATTERN_GEN */
 821 /* HPD_GEN */
 822 /* HDCP_Ri_Compare_0 */
 823 /* HDCP_Ri_Compare_0 */
 824 /* HDCP_Ri_Compare_0 */
 825 /* HDCP_Ri_Compare_0 */
 826 /* HDCP_Ri_Compare_0 */
 827 /* HDCP_Ri_Compare_0 */
 828 /* HDCP_Ri_Compare_0 */
 829 /* HDCP_Ri_Compare_0 */
 830 /* HDCP_Ri_Compare_0 */
 831 /* HDCP_Ri_Compare_0 */
 832
 833
 834 /* SPDIF Register */
 835
 836 /* SPDIFIN_CLK_CTRL */
 837 #define S5P_HDMI_SPDIFIN_READY_CLK_DOWN         (1 << 1)
 838 #define S5P_HDMI_SPDIFIN_CLK_ON                 (1)
 839
 840 /* SPDIFIN_OP_CTRL */
 841 #define S5P_HDMI_SPDIFIN_SW_RESET               (0)
 842 #define S5P_HDMI_SPDIFIN_STATUS_CHECK_MODE      (1)
 843 #define S5P_HDMI_SPDIFIN_STATUS_CHK_OP_MODE     (3)
 844
 845 /* SPDIFIN_IRQ_MASK */
 846
 847 /* SPDIFIN_IRQ_STATUS */
 848 #define S5P_HDMI_SPDIFIN_IRQ_OVERFLOW_EN                        (1 << 7)
 849 #define S5P_HDMI_SPDIFIN_IRQ_ABNORMAL_PD_EN                     (1 << 6)
 850 #define S5P_HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_RIGHTTIME_EN       (1 << 5)
 851 #define S5P_HDMI_SPDIFIN_IRQ_SH_DETECTED_EN                     (1 << 4)
 852 #define S5P_HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_EN                 (1 << 3)
 853 #define S5P_HDMI_SPDIFIN_IRQ_WRONG_PREAMBLE_EN                  (1 << 2)
 854 #define S5P_HDMI_SPDIFIN_IRQ_CH_STATUS_RECOVERED_EN             (1 << 1)
 855 #define S5P_HDMI_SPDIFIN_IRQ_WRONG_SIG_EN                       (1 << 0)
 856
 857 /* SPDIFIN_CONFIG_1 */
 858 #define S5P_HDMI_SPDIFIN_CFG_FILTER_3_SAMPLE                    (0 << 6)
 859 #define S5P_HDMI_SPDIFIN_CFG_FILTER_2_SAMPLE                    (1 << 6)
 860 #define S5P_HDMI_SPDIFIN_CFG_LINEAR_PCM_TYPE                    (0 << 5)
 861 #define S5P_HDMI_SPDIFIN_CFG_NO_LINEAR_PCM_TYPE                 (1 << 5)
 862 #define S5P_HDMI_SPDIFIN_CFG_PCPD_AUTO_SET                      (0 << 4)
 863 #define S5P_HDMI_SPDIFIN_CFG_PCPD_MANUAL_SET                    (1 << 4)
 864 #define S5P_HDMI_SPDIFIN_CFG_WORD_LENGTH_A_SET                  (0 << 3)
 865 #define S5P_HDMI_SPDIFIN_CFG_WORD_LENGTH_M_SET                  (1 << 3)
 866 #define S5P_HDMI_SPDIFIN_CFG_U_V_C_P_NEGLECT                    (0 << 2)
 867 #define S5P_HDMI_SPDIFIN_CFG_U_V_C_P_REPORT                     (1 << 2)
 868 #define S5P_HDMI_SPDIFIN_CFG_BURST_SIZE_1                       (0 << 1)
 869 #define S5P_HDMI_SPDIFIN_CFG_BURST_SIZE_2                       (1 << 1)
 870 #define S5P_HDMI_SPDIFIN_CFG_DATA_ALIGN_16BIT                   (0 << 0)
 871 #define S5P_HDMI_SPDIFIN_CFG_DATA_ALIGN_32BIT                   (1 << 0)
 872
 873 /* SPDIFIN_CONFIG_2 */
 874 #define S5P_HDMI_SPDIFIN_CFG2_NO_CLK_DIV                        (0)
 875
 876 /* SPDIFIN_USER_VALUE_1 */
 877 /* SPDIFIN_USER_VALUE_2 */
 878 /* SPDIFIN_USER_VALUE_3 */
 879 /* SPDIFIN_USER_VALUE_4 */
 880 /* SPDIFIN_CH_STATUS_0_1 */
 881 /* SPDIFIN_CH_STATUS_0_2 */
 882 /* SPDIFIN_CH_STATUS_0_3 */
 883 /* SPDIFIN_CH_STATUS_0_4 */
 884 /* SPDIFIN_CH_STATUS_1 */
 885 /* SPDIFIN_FRAME_PERIOD_1 */
 886 /* SPDIFIN_FRAME_PERIOD_2 */
 887 /* SPDIFIN_PC_INFO_1 */
 888 /* SPDIFIN_PC_INFO_2 */
 889 /* SPDIFIN_PD_INFO_1 */
 890 /* SPDIFIN_PD_INFO_2 */
 891 /* SPDIFIN_DATA_BUF_0_1 */
 892 /* SPDIFIN_DATA_BUF_0_2 */
 893 /* SPDIFIN_DATA_BUF_0_3 */
 894 /* SPDIFIN_USER_BUF_0 */
 895 /* SPDIFIN_USER_BUF_1_1 */
 896 /* SPDIFIN_USER_BUF_1_2 */
 897 /* SPDIFIN_USER_BUF_1_3 */
 898 /* SPDIFIN_USER_BUF_1 */
 899
 900
 901 /* I2S Register */
 902
 903 /* I2S_CLK_CON */
 904 #define S5P_HDMI_I2S_CLK_DIS                    (0)
 905 #define S5P_HDMI_I2S_CLK_EN                     (1)
 906
 907 /* I2S_CON_1 */
 908 #define S5P_HDMI_I2S_SCLK_FALLING_EDGE          (0 << 1)
 909 #define S5P_HDMI_I2S_SCLK_RISING_EDGE           (1 << 1)
 910 #define S5P_HDMI_I2S_L_CH_LOW_POL               (0)
 911 #define S5P_HDMI_I2S_L_CH_HIGH_POL              (1)
 912
 913 /* I2S_CON_2 */
 914 #define S5P_HDMI_I2S_MSB_FIRST_MODE             (0 << 6)
 915 #define S5P_HDMI_I2S_LSB_FIRST_MODE             (1 << 6)
 916 #define S5P_HDMI_I2S_BIT_CH_32FS                (0 << 4)
 917 #define S5P_HDMI_I2S_BIT_CH_48FS                (1 << 4)
 918 #define S5P_HDMI_I2S_BIT_CH_RESERVED            (2 << 4)
 919 #define S5P_HDMI_I2S_SDATA_16BIT                (1 << 2)
 920 #define S5P_HDMI_I2S_SDATA_20BIT                (2 << 2)
 921 #define S5P_HDMI_I2S_SDATA_24BIT                (3 << 2)
 922 #define S5P_HDMI_I2S_BASIC_FORMAT               (0)
 923 #define S5P_HDMI_I2S_L_JUST_FORMAT              (2)
 924 #define S5P_HDMI_I2S_R_JUST_FORMAT              (3)
 925 #define S5P_HDMI_I2S_CON_2_CLR                  ~(0xFF)
 926 #define S5P_HDMI_I2S_SET_BIT_CH(x)              (((x) & 0x7) << 4)
 927 #define S5P_HDMI_I2S_SET_SDATA_BIT(x)           (((x) & 0x7) << 2)
 928
 929 /* I2S_PIN_SEL_0 */
 930 #define S5P_HDMI_I2S_SEL_SCLK(x)                (((x) & 0x7) << 4)
 931 #define S5P_HDMI_I2S_SEL_SCLK_DEFAULT_1         (0x7 << 4)
 932 #define S5P_HDMI_I2S_SEL_LRCK(x)                ((x) & 0x7)
 933 #define S5P_HDMI_I2S_SEL_LRCK_DEFAULT_0         (0x7)
 934
 935 /* I2S_PIN_SEL_1 */
 936 #define S5P_HDMI_I2S_SEL_SDATA1(x)              (((x) & 0x7) << 4)
 937 #define S5P_HDMI_I2S_SEL_SDATA1_DEFAULT_3       (0x7 << 4)
 938 #define S5P_HDMI_I2S_SEL_SDATA2(x)              ((x) & 0x7)
 939 #define S5P_HDMI_I2S_SEL_SDATA2_DEFAULT_2       (0x7)
 940
 941 /* I2S_PIN_SEL_2 */
 942 #define S5P_HDMI_I2S_SEL_SDATA3(x)              (((x) & 0x7) << 4)
 943 #define S5P_HDMI_I2S_SEL_SDATA3_DEFAULT_5       (0x7 << 4)
 944 #define S5P_HDMI_I2S_SEL_SDATA2(x)              ((x) & 0x7)
 945 #define S5P_HDMI_I2S_SEL_SDATA2_DEFAULT_4       (0x7)
 946
 947 /* I2S_PIN_SEL_3 */
 948 #define S5P_HDMI_I2S_SEL_DSD(x)                 ((x) & 0x7)
 949 #define S5P_HDMI_I2S_SEL_DSD_DEFAULT_6          (0x7)
 950
 951 /* I2S_DSD_CON */
 952 #define S5P_HDMI_I2S_DSD_CLK_RI_EDGE            (1 << 1)
 953 #define S5P_HDMI_I2S_DSD_CLK_FA_EDGE            (0 << 1)
 954 #define S5P_HDMI_I2S_DSD_ENABLE                 (1)
 955 #define S5P_HDMI_I2S_DSD_DISABLE                (0)
 956
 957 /* I2S_MUX_CON */
 958 #define S5P_HDMI_I2S_NOISE_FILTER_ZERO          (0 << 5)
 959 #define S5P_HDMI_I2S_NOISE_FILTER_2_STAGE       (1 << 5)
 960 #define S5P_HDMI_I2S_NOISE_FILTER_3_STAGE       (2 << 5)
 961 #define S5P_HDMI_I2S_NOISE_FILTER_4_STAGE       (3 << 5)
 962 #define S5P_HDMI_I2S_NOISE_FILTER_5_STAGE       (4 << 5)
 963 #define S5P_HDMI_I2S_IN_DISABLE                 (1 << 4)
 964 #define S5P_HDMI_I2S_IN_ENABLE                  (0 << 4)
 965 #define S5P_HDMI_I2S_AUD_SPDIF                  (0 << 2)
 966 #define S5P_HDMI_I2S_AUD_I2S                    (1 << 2)
 967 #define S5P_HDMI_I2S_AUD_DSD                    (2 << 2)
 968 #define S5P_HDMI_I2S_CUV_SPDIF_ENABLE           (0 << 1)
 969 #define S5P_HDMI_I2S_CUV_I2S_ENABLE             (1 << 1)
 970 #define S5P_HDMI_I2S_MUX_DISABLE                (0)
 971 #define S5P_HDMI_I2S_MUX_ENABLE                 (1)
 972 #define S5P_HDMI_I2S_MUX_CON_CLR                ~(0xFF)
 973
 974 /* I2S_CH_ST_CON */
 975 #define S5P_HDMI_I2S_CH_STATUS_RELOAD           (1)
 976 #define S5P_HDMI_I2S_CH_ST_CON_CLR              ~(1)
 977
 978 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
 979 #define S5P_HDMI_I2S_CH_STATUS_MODE_0           (0 << 6)
 980 #define S5P_HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH    (0 << 3)
 981 #define S5P_HDMI_I2S_2AUD_CH_WITH_PREEMPH       (1 << 3)
 982 #define S5P_HDMI_I2S_DEFAULT_EMPHASIS           (0 << 3)
 983 #define S5P_HDMI_I2S_COPYRIGHT                  (0 << 2)
 984 #define S5P_HDMI_I2S_NO_COPYRIGHT               (1 << 2)
 985 #define S5P_HDMI_I2S_LINEAR_PCM                 (0 << 1)
 986 #define S5P_HDMI_I2S_NO_LINEAR_PCM              (1 << 1)
 987 #define S5P_HDMI_I2S_CONSUMER_FORMAT            (0)
 988 #define S5P_HDMI_I2S_PROF_FORMAT                (1)
 989 #define S5P_HDMI_I2S_CH_ST_0_CLR                ~(0xFF)
 990
 991 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
 992 #define S5P_HDMI_I2S_CD_PLAYER                  (0x00)
 993 #define S5P_HDMI_I2S_DAT_PLAYER                 (0x03)
 994 #define S5P_HDMI_I2S_DCC_PLAYER                 (0x43)
 995 #define S5P_HDMI_I2S_MINI_DISC_PLAYER           (0x49)
 996
 997 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
 998 #define S5P_HDMI_I2S_CHANNEL_NUM_MASK           (0xF << 4)
 999 #define S5P_HDMI_I2S_SOURCE_NUM_MASK            (0xF)
1000 #define S5P_HDMI_I2S_SET_CHANNEL_NUM(x)         ((x) & (0xF) << 4)
1001 #define S5P_HDMI_I2S_SET_SOURCE_NUM(x)          ((x) & (0xF))
1002
1003 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
1004 #define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_1          (1 << 4)
1005 #define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_2          (0 << 4)
1006 #define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_3          (2 << 4)
1007 #define S5P_HDMI_I2S_SAMPLING_FREQ_44_1         (0x0)
1008 #define S5P_HDMI_I2S_SAMPLING_FREQ_48           (0x2)
1009 #define S5P_HDMI_I2S_SAMPLING_FREQ_32           (0x3)
1010 #define S5P_HDMI_I2S_SAMPLING_FREQ_96           (0xA)
1011 #define S5P_HDMI_I2S_SET_SAMPLING_FREQ(x)       ((x) & (0xF))
1012
1013 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
1014 #define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_44_1     (0xF << 4)
1015 #define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_88_2     (0x7 << 4)
1016 #define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_22_05    (0xB << 4)
1017 #define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_176_4    (0x3 << 4)
1018 #define S5P_HDMI_I2S_WORD_LENGTH_NOT_DEFINE     (0x0 << 1)
1019 #define S5P_HDMI_I2S_WORD_LENGTH_MAX24_20BITS   (0x1 << 1)
1020 #define S5P_HDMI_I2S_WORD_LENGTH_MAX24_22BITS   (0x2 << 1)
1021 #define S5P_HDMI_I2S_WORD_LENGTH_MAX24_23BITS   (0x4 << 1)
1022 #define S5P_HDMI_I2S_WORD_LENGTH_MAX24_24BITS   (0x5 << 1)
1023 #define S5P_HDMI_I2S_WORD_LENGTH_MAX24_21BITS   (0x6 << 1)
1024 #define S5P_HDMI_I2S_WORD_LENGTH_MAX20_16BITS   (0x1 << 1)
1025 #define S5P_HDMI_I2S_WORD_LENGTH_MAX20_18BITS   (0x2 << 1)
1026 #define S5P_HDMI_I2S_WORD_LENGTH_MAX20_19BITS   (0x4 << 1)
1027 #define S5P_HDMI_I2S_WORD_LENGTH_MAX20_20BITS   (0x5 << 1)
1028 #define S5P_HDMI_I2S_WORD_LENGTH_MAX20_17BITS   (0x6 << 1)
1029 #define S5P_HDMI_I2S_WORD_LENGTH_MAX_24BITS     (1)
1030 #define S5P_HDMI_I2S_WORD_LENGTH_MAX_20BITS     (0)
1031
1032 /* I2S_VD_DATA */
1033 #define S5P_HDMI_I2S_VD_AUD_SAMPLE_RELIABLE     (0)
1034 #define S5P_HDMI_I2S_VD_AUD_SAMPLE_UNRELIABLE   (1)
1035
1036 /* I2S_MUX_CH */
1037 #define S5P_HDMI_I2S_CH3_R_EN                   (1 << 7)
1038 #define S5P_HDMI_I2S_CH3_L_EN                   (1 << 6)
1039 #define S5P_HDMI_I2S_CH3_EN                     (3 << 6)
1040 #define S5P_HDMI_I2S_CH2_R_EN                   (1 << 5)
1041 #define S5P_HDMI_I2S_CH2_L_EN                   (1 << 4)
1042 #define S5P_HDMI_I2S_CH2_EN                     (3 << 4)
1043 #define S5P_HDMI_I2S_CH1_R_EN                   (1 << 3)
1044 #define S5P_HDMI_I2S_CH1_L_EN                   (1 << 2)
1045 #define S5P_HDMI_I2S_CH1_EN                     (3 << 2)
1046 #define S5P_HDMI_I2S_CH0_R_EN                   (1 << 1)
1047 #define S5P_HDMI_I2S_CH0_L_EN                   (1)
1048 #define S5P_HDMI_I2S_CH0_EN                     (3)
1049 #define S5P_HDMI_I2S_CH_ALL_EN                  (0xFF)
1050 #define S5P_HDMI_I2S_MUX_CH_CLR                 ~S5P_HDMI_I2S_CH_ALL_EN
1051
1052 /* I2S_MUX_CUV */
1053 #define S5P_HDMI_I2S_CUV_R_EN                   (1 << 1)
1054 #define S5P_HDMI_I2S_CUV_L_EN                   (1)
1055 #define S5P_HDMI_I2S_CUV_RL_EN                  (0x03)
1056
1057 /* I2S_IRQ_MASK */
1058 #define S5P_HDMI_I2S_INT2_DIS                   (0 << 1)
1059 #define S5P_HDMI_I2S_INT2_EN                    (1 << 1)
1060
1061 /* I2S_IRQ_STATUS */
1062 #define S5P_HDMI_I2S_INT2_STATUS                (1 << 1)
1063
1064 /* I2S_CH0_L_0 */
1065 /* I2S_CH0_L_1 */
1066 /* I2S_CH0_L_2 */
1067 /* I2S_CH0_L_3 */
1068 /* I2S_CH0_R_0 */
1069 /* I2S_CH0_R_1 */
1070 /* I2S_CH0_R_2 */
1071 /* I2S_CH0_R_3 */
1072 /* I2S_CH1_L_0 */
1073 /* I2S_CH1_L_1 */
1074 /* I2S_CH1_L_2 */
1075 /* I2S_CH1_L_3 */
1076 /* I2S_CH1_R_0 */
1077 /* I2S_CH1_R_1 */
1078 /* I2S_CH1_R_2 */
1079 /* I2S_CH1_R_3 */
1080 /* I2S_CH2_L_0 */
1081 /* I2S_CH2_L_1 */
1082 /* I2S_CH2_L_2 */
1083 /* I2S_CH2_L_3 */
1084 /* I2S_CH2_R_0 */
1085 /* I2S_CH2_R_1 */
1086 /* I2S_CH2_R_2 */
1087 /* I2S_Ch2_R_3 */
1088 /* I2S_CH3_L_0 */
1089 /* I2S_CH3_L_1 */
1090 /* I2S_CH3_L_2 */
1091 /* I2S_CH3_R_0 */
1092 /* I2S_CH3_R_1 */
1093 /* I2S_CH3_R_2 */
1094
1095 /* I2S_CUV_L_R */
1096 #define S5P_HDMI_I2S_CUV_R_DATA_MASK            (0x7 << 4)
1097 #define S5P_HDMI_I2S_CUV_L_DATA_MASK            (0x7)
1098
1099
1100 /* Timing Generator Register */
1101 /* TG_CMD */
1102 #define S5P_HDMI_GETSYNC_TYPE                   (1 << 4)
1103 #define S5P_HDMI_GETSYNC                        (1 << 3)
1104 #define S5P_HDMI_FIELD                          (1 << 1)
1105 #define S5P_HDMI_TG                             (1)
1106
1107 /* TG_CFG */
1108 /* TG_CB_SZ */
1109 /* TG_INDELAY_L */
1110 /* TG_INDELAY_H */
1111 /* TG_POL_CTRL */
1112
1113 /* TG_H_FSZ_L */
1114 /* TG_H_FSZ_H */
1115 /* TG_HACT_ST_L */
1116 /* TG_HACT_ST_H */
1117 /* TG_HACT_SZ_L */
1118 /* TG_HACT_SZ_H */
1119 /* TG_V_FSZ_L */
1120 /* TG_V_FSZ_H */
1121 /* TG_VSYNC_L */
1122 /* TG_VSYNC_H */
1123 /* TG_VSYNC2_L */
1124 /* TG_VSYNC2_H */
1125 /* TG_VACT_ST_L */
1126 /* TG_VACT_ST_H */
1127 /* TG_VACT_SZ_L */
1128 /* TG_VACT_SZ_H */
1129 /* TG_FIELD_CHG_L */
1130 /* TG_FIELD_CHG_H */
1131 /* TG_VACT_ST2_L */
1132 /* TG_VACT_ST2_H */
1133 /* TG_VACT_SC_ST_L */
1134 /* TG_VACT_SC_ST_H */
1135 /* TG_VACT_SC_SZ_L */
1136 /* TG_VACT_SC_SZ_H */
1137
1138 /* TG_VSYNC_TOP_HDMI_L */
1139 /* TG_VSYNC_TOP_HDMI_H */
1140 /* TG_VSYNC_BOT_HDMI_L */
1141 /* TG_VSYNC_BOT_HDMI_H */
1142 /* TG_FIELD_TOP_HDMI_L */
1143 /* TG_FIELD_TOP_HDMI_H */
1144 /* TG_FIELD_BOT_HDMI_L */
1145 /* TG_FIELD_BOT_HDMI_H */
1146 /* TG_HSYNC_HDOUT_ST_L */
1147 /* TG_HSYNC_HDOUT_ST_H */
1148 /* TG_HSYNC_HDOUT_END_L */
1149 /* TG_HSYNC_HDOUT_END_H */
1150 /* TG_VSYNC_HDOUT_ST_L */
1151 /* TG_VSYNC_HDOUT_ST_H */
1152 /* TG_VSYNC_HDOUT_END_L */
1153 /* TG_VSYNC_HDOUT_END_H */
1154 /* TG_VSYNC_HDOUT_DLY_L */
1155 /* TG_VSYNC_HDOUT_DLY_H */
1156 /* TG_BT_ERR_RANGE */
1157 /* TG_BT_ERR_RESULT */
1158 /* TG_COR_THR */
1159 /* TG_COR_NUM */
1160 /* TG_BT_CON */
1161 /* TG_BT_H_FSZ_L */
1162 /* TG_BT_H_FSZ_H */
1163 /* TG_BT_HSYNC_ST */
1164 /* TG_BT_HSYNC_SZ */
1165 /* TG_BT_FSZ_L */
1166 /* TG_BT_FSZ_H */
1167 /* TG_BT_VACT_T_ST_L */
1168 /* TG_BT_VACT_T_ST_H */
1169 /* TG_BT_VACT_B_ST_L */
1170 /* TG_BT_VACT_B_ST_H */
1171 /* TG_BT_VACT_SZ_L */
1172 /* TG_BT_VACT_SZ_H */
1173 /* TG_BT_VSYNC_SZ */
1174
1175
1176 /* HDCP E-FUSE Control Register */
1177 /* HDCP_E_FUSE_CTRL */
1178 #define S5P_HDMI_EFUSE_CTRL_HDCP_KEY_READ       (1)
1179
1180 /* HDCP_E_FUSE_STATUS */
1181 #define S5P_HDMI_EFUSE_ECC_FAIL                 (1 << 2)
1182 #define S5P_HDMI_EFUSE_ECC_BUSY                 (1 << 1)
1183 #define S5P_HDMI_EFUSE_ECC_DONE                 (1)
1184
1185 /* EFUSE_ADDR_WIDTH */
1186 /* EFUSE_SIGDEV_ASSERT */
1187 /* EFUSE_SIGDEV_DE-ASSERT */
1188 /* EFUSE_PRCHG_ASSERT */
1189 /* EFUSE_PRCHG_DE-ASSERT */
1190 /* EFUSE_FSET_ASSERT */
1191 /* EFUSE_FSET_DE-ASSERT */
1192 /* EFUSE_SENSING */
1193 /* EFUSE_SCK_ASSERT */
1194 /* EFUSE_SCK_DEASSERT */
1195 /* EFUSE_SDOUT_OFFSET */
1196 /* EFUSE_READ_OFFSET */
1197
1198 /* HDCP_SHA_RESULT */
1199 #define S5P_HDMI_HDCP_SHA_VALID_NO_RD           (0 << 1)
1200 #define S5P_HDMI_HDCP_SHA_VALID_RD              (1 << 1)
1201 #define S5P_HDMI_HDCP_SHA_VALID                 (1)
1202 #define S5P_HDMI_HDCP_SHA_NO_VALID              (0)
1203
1204 /* DC_CONTRAL */
1205 #define S5P_HDMI_DC_CTL_12                      (1 << 1)
1206 #define S5P_HDMI_DC_CTL_8                       (0)
1207 #define S5P_HDMI_DC_CTL_10                      (1)
1208 #endif  /* __ARCH_ARM_REGS_HDMI_H */