2 * Copyright (C) 2010 Samsung Electronics
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
10 #include <mach/gpio.h>
15 #include "gpio-mobile.h"
19 * Please describe the how to setup the pins.
20 * E.g., what's the correct setings for I2C, PULL_UP or PULL_NONE?
30 /* UART 0 for BT & 1 for GPS */
31 static const struct s5p_gpio_group group_a0[] __initdata = {
32 /* XuRXD[0] BT_UART_RXD */
33 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
34 /* XuTXD[0] BT_UART_TXD */
35 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
36 /* XuCTSn[0] BT_UART_CTS */
37 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
38 /* XuRTSn[0] BT_UART_RTS */
39 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
40 /* XuRXD[1] GPS_UART_RXD */
41 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
42 /* XuTXD[1] GPS_UART_TXD */
43 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
44 /* XuCTSn[1] GPS_UART_CTS */
45 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
46 /* XuRTSn[1] GPS_UART_RTS */
47 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
50 /* UART 2 for debug & 3 for CP */
51 static const struct s5p_gpio_group group_a1[] __initdata = {
53 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
55 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
56 /* Xi2c2SDA TSP_SDA_2.8V (I2C3: TSP) PU by VTOUCH_VDD2.8V */
57 PIN(2, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
58 /* Xi2c2SCL TSP_SCL_2.8V (I2C3: TSP) PU by VTOUCH_VDD2.8V */
59 PIN(3, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
60 /* XuRXD[3] AP_FLM_RXD_2.8V */
61 PIN(4, SFN(0x2), NONE, NOP, DRV1X, INPUT, PULLDOWN),
62 /* XuTXD[3] AP_FLM_TXD_2.8V */
63 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
66 static const struct s5p_gpio_group group_b[] __initdata = {
67 /* XspiCLK[0] FM_RST */
68 PIN(0, SFN(0x1), LOW, NONE, DRV1X, OUTPUT0, NOP),
69 /* XspiCSn[0] FM_INT */
70 PIN(1, SFN(0xf), NONE, NONE, DRV1X, INPUT, PULLDOWN),
71 /* XspiMISO[0] PEN_SDA_2.8V */
72 PIN(2, SFN(0x0), NONE, NONE, DRV1X, INPUT, NOP),
73 /* XspiMOSI[0] PEN_SCL_2.8V */
74 PIN(3, SFN(0x0), NONE, NONE, DRV1X, INPUT, NOP),
75 /* XspiCLK[1] WLAN_WAKE (NC) */
79 /* XspiMISO[1] AP_PMIC_SDA (PU by VCC_2.8V_PDA */
80 PIN(6, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
81 /* XspiMOSI[1] AP_PMIC_SCLK (PU by VCC_2.8V_PDA */
82 PIN(7, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
85 static const struct s5p_gpio_group group_b_rev04[] __initdata = {
98 /* XspiMISO[1] AP_PMIC_SDA (PU by VCC_2.8V_PDA */
99 PIN(6, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
100 /* XspiMOSI[1] AP_PMIC_SCLK (PU by VCC_2.8V_PDA */
101 PIN(7, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
104 static const struct s5p_gpio_group group_c0[] __initdata = {
105 /* XIIS1SCLK REC_PCM_CLK */
106 PIN(0, SFN(0x2), NONE, XXXXXX, DRV1X, OUTPUT0, NOP),
109 /* XIIS1LRCK REC_PCM_SYNC */
110 PIN(2, SFN(0x2), NONE, XXXXXX, DRV1X, OUTPUT0, NOP),
111 /* XIIS1SDI REC_PCM_IN */
112 PIN(3, SFN(0x2), NONE, NOP, DRV1X, INPUT, PULLDOWN),
113 /* XIIS1SDO REC_PCM_OUT */
114 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
117 static const struct s5p_gpio_group group_c1[] __initdata = {
118 /* Xpcm2SCLk VT_CAM_SDA_1.8V */
119 PIN(0, SFN(0x0), NONE, NONE, DRV1X, INPUT, NOP),
120 /* Xpcm2EXTCLK CP_ON: Inefficient? */
121 PIN(1, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
122 /* Xpcm2FSYNC VT_CAM_SCL_1.8V */
123 PIN(2, SFN(0x0), NONE, NONE, DRV1X, INPUT, NOP),
124 /* Xpcm2SIN CODEC_SDA_1.8V PU by VCC_1.8V_PDA */
125 PIN(3, SFN(0x4), NONE, NOP, DRV1X, INPUT, NOP),
126 /* Xpcm2SOUT CODEV_VT_SCLK_1.8V PU by VCC_1.8V_PDA */
127 PIN(4, SFN(0x4), NONE, NOP, DRV1X, INPUT, NOP),
130 static const struct s5p_gpio_group group_d0[] __initdata = {
131 /* XpwmTOUT[0] LCD_PWM(rev03), NC(rev04) */
133 /* XpwmTOUT[1] VIBTONE_PWM */
134 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
135 /* XpwmTOUT[2] MSENSOR_SDA_2.8V = MHL_SDA_2.8VV PU by VCC_2.8V_PDA */
136 PIN(2, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
137 /* XpwmTOUT[3] MSENSOR_SCL_2.8V = MHL_SCL_2.8V PU by VCC_2.8V_PDA */
138 PIN(3, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
141 static const struct s5p_gpio_group group_d1[] __initdata = {
142 /* Xi2c0SDA 8M_CAM_SDA_2.8V PU by VCC_2.8V_PDA */
143 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
144 /* Xi2c0SCL 8M_CAM_SCL_2.8V PU by VCC_2.8V_PDA */
145 PIN(1, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
146 /* Xi2c1SDA SENSE_SDA_2.8V PU by VCC_2.8V_PDA */
147 PIN(2, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
148 /* Xi2c1SCL SENSE_SCL_2.8V PU by VCC_2.8V_PDA */
149 PIN(3, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
152 static const struct s5p_gpio_group group_e0[] __initdata = {
159 /* XmdmIRQn GPS_EN */
160 PIN(3, SFN(0x0), NONE, NONE, DRV1X, OUTPUT0, NOP),
161 /* XmdmADVN GPS_nRST */
162 PIN(4, SFN(0x0), NONE, NONE, DRV1X, OUTPUT0, NOP),
165 static const struct s5p_gpio_group group_e1[] __initdata = {
166 /* XmdmADDR[0] HW_REV0 PU by VCC_1.8V_PDA */
167 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0105 */
168 /* XmdmADDR[1] HW_REV1 PU by VCC_1.8V_PDA */
169 PIN(1, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0102 */
170 /* XmdmADDR[2] HW_REV2 PU by VCC_1.8V_PDA */
171 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* H at SLP7_0102 */
172 /* XmdmADDR[3] HW_REV3 PU by VCC_1.8V_PDA */
173 PIN(3, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0102 */
174 /* XmdmADDR[4] LCD_ONEWIRE */
175 PIN(4, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
176 /* XmdmADDR[5] FM_SCL_2.8V */
177 PIN(5, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
178 /* XmdmADDR[6] PEN_PDCT_2.8V */
179 PIN(6, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
180 /* XmdmADDR[7] PEN_SLP */
181 PIN(7, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
184 static const struct s5p_gpio_group group_e1_rev04[] __initdata = {
185 /* XmdmADDR[0] HW_REV0 PU by VCC_1.8V_PDA */
186 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0105 */
187 /* XmdmADDR[1] HW_REV1 PU by VCC_1.8V_PDA */
188 PIN(1, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0102 */
189 /* XmdmADDR[2] HW_REV2 PU by VCC_1.8V_PDA */
190 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* H at SLP7_0102 */
191 /* XmdmADDR[3] HW_REV3 PU by VCC_1.8V_PDA */
192 PIN(3, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at SLP7_0102 */
193 /* XmdmADDR[4] MIC_BIAS */
194 PIN(4, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
203 static const struct s5p_gpio_group group_e2[] __initdata = {
204 /* XmdmADDR[8] PEN_IRQ_2.8V */
205 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
206 /* XmdmADDR[9] CAM_IO_EN */
207 PIN(1, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
208 /* XmdmADDR[10] VT_CAM_1.5V_EN */
209 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
210 /* XmdmADDR[11] FM_SDA_2.8V */
211 PIN(3, SFN(0x0), NONE, NOP, DRV1X, INPUT, PULLDOWN),
212 /* XmdmADDR[12] EAR_MICBIAS_EN */
213 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
214 /* XmdmADDR[13] 8M_1.2V_EN */
215 PIN(5, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
218 static const struct s5p_gpio_group group_e2_rev04[] __initdata = {
221 /* XmdmADDR[9] CAM_IO_EN */
222 PIN(1, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
223 /* XmdmADDR[10] VT_CAM_1.5V_EN */
224 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
225 /* XmdmADDR[11] VT_CAM_1.8V_EN */
226 PIN(3, SFN(0x0), NONE, NOP, DRV1X, INPUT, PULLDOWN),
227 /* XmdmADDR[12] EAR_MICBIAS_EN */
228 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
229 /* XmdmADDR[13] NC */
233 static const struct s5p_gpio_group group_e3[] __initdata = {
252 static const struct s5p_gpio_group group_e4[] __initdata = {
257 /* XmdmDATA[10] NC */
259 /* XmdmDATA[11] NC */
261 /* XmdmDATA[12] NC */
263 /* XmdmDATA[13] NC */
265 /* XmdmDATA[14] NC */
267 /* XmdmDATA[15] NC */
272 static const struct s5p_gpio_group group_f0[] __initdata = {
273 /* XvHSYNC LCD_HSYNC */
274 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
275 /* XvVSYNC LCD_VSYNC */
276 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
278 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
279 /* XvVCLK LCD_PCLK CAP-Ground */
280 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
282 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
284 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
286 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
288 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
291 static const struct s5p_gpio_group group_f1[] __initdata = {
293 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
295 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
297 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
299 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
301 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
303 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
305 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
307 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
310 static const struct s5p_gpio_group group_f2[] __initdata = {
312 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
314 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
316 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
318 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
320 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
322 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
324 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
326 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
329 static const struct s5p_gpio_group group_f3[] __initdata = {
331 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
333 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
335 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
337 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
338 /* XvVSYNC_LDI MHL_RST */
339 PIN(4, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
340 /* XvSYS_OE MHL_INT PD by Ground*/
341 PIN(5, SFN(0xF), NONE, NOP, DRV1X, INPUT, NOP),
344 static const struct s5p_gpio_group group_f3_rev04[] __initdata = {
346 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
348 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
350 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
352 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
360 static const struct s5p_gpio_group group_j0[] __initdata = {
379 static const struct s5p_gpio_group group_j0_rev04[] __initdata = {
380 /* XciPCLK CAM_PCLK_F */
382 /* XciVSYNC CAM_VSYNC */
384 /* XciHREF CAM_HSYNC */
386 /* XciDATA[0] CAM_D(0) */
388 /* XciDATA[1] CAM_D(1) */
390 /* XciDATA[2] CAM_D(2) */
392 /* XciDATA[3] CAM_D(3) */
394 /* XciDATA[4] CAM_D(4) */
398 static const struct s5p_gpio_group group_j1[] __initdata = {
405 /* XciCLKenb CAM_MCLK */
406 PIN(3, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
407 /* XciFIELD MHL_WAKE_UP */
408 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
411 static const struct s5p_gpio_group group_j1_rev04[] __initdata = {
412 /* XciDATA[5] CAM_D(5) */
414 /* XciDATA[6] CAM_D(6) */
416 /* XciDATA[7] CAM_D(7) */
418 /* XciCLKenb CAM_MCLK */
419 PIN(3, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
424 static const struct s5p_gpio_group group_k0[] __initdata = {
425 /* Xmmc0CLK NAND_CLK */
426 PIN(0, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
427 /* Xmmc0CMD NAND_CMD */
428 PIN(1, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
429 /* Xmmc0CDn eMMC_EN */
430 PIN(2, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
431 /* Xmmc0DATA[0] NAND_D */
432 PIN(3, SFN(0x2), NONE, PULLUP, DRV4X, INPUT, NOP),
433 /* Xmmc0DATA[1] NAND_D */
434 PIN(4, SFN(0x2), NONE, PULLUP, DRV4X, INPUT, NOP),
435 /* Xmmc0DATA[2] NAND_D */
436 PIN(5, SFN(0x2), NONE, PULLUP, DRV4X, INPUT, NOP),
437 /* Xmmc0DATA[3] NAND_D */
438 PIN(6, SFN(0x2), NONE, PULLUP, DRV4X, INPUT, NOP),
441 static const struct s5p_gpio_group group_k1[] __initdata = {
442 /* Xmmc1CLK 3_TOUCH_SCL_2.8V */
443 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
444 /* Xmmc1CMD CAM_AF_EN */
445 PIN(1, SFN(0x1), LOW, PULLUP, DRV1X, OUTPUT0, NOP),
446 /* Xmmc1CDn 3_TOUCH_SDA_2.8V */
447 PIN(2, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
448 /* Xmmc1DATA[0] NAND_D */
449 PIN(3, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
450 /* Xmmc1DATA[1] NAND_D */
451 PIN(4, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
452 /* Xmmc1DATA[2] NAND_D */
453 PIN(5, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
454 /* Xmmc1DATA[3] NAND_D */
455 PIN(6, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
458 static const struct s5p_gpio_group group_k1_rev04[] __initdata = {
459 /* Xmmc1CLK 3_TOUCH_SCL_2.8V */
460 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
463 /* Xmmc1CDn 3_TOUCH_SDA_2.8V */
464 PIN(2, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
465 /* Xmmc1DATA[0] NAND_D */
466 PIN(3, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
467 /* Xmmc1DATA[1] NAND_D */
468 PIN(4, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
469 /* Xmmc1DATA[2] NAND_D */
470 PIN(5, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
471 /* Xmmc1DATA[3] NAND_D */
472 PIN(6, SFN(0x3), NONE, PULLUP, DRV4X, INPUT, NOP),
475 static const struct s5p_gpio_group group_k2[] __initdata = {
476 /* Xmmc2CLK T_FLASH_CLK */
477 PIN(0, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
478 /* Xmmc2CMD T_FLASH_CMD PU by VTF_2.8V */
479 PIN(1, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
480 /* Xmmc2CDn PS_ALS_SDA_2.8V */
481 PIN(2, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
482 /* Xmmc2DATA[0] T_FLASH_D PU by VTF_2.8V */
483 PIN(3, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
485 PIN(4, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
487 PIN(5, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
489 PIN(6, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
492 static const struct s5p_gpio_group group_k2_rev04[] __initdata = {
497 /* Xmmc2CDn PS_ALS_SDA_2.8V */
498 PIN(2, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
499 /* Xmmc2DATA[0] NC */
501 /* Xmmc2DATA[1] NC */
503 /* Xmmc2DATA[2] NC */
505 /* Xmmc2DATA[3] NC */
509 static const struct s5p_gpio_group group_k3[] __initdata = {
510 /* Xmmc3CLK WLAN_SDIO_CLK */
511 PIN(0, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
512 /* Xmmc3CMD WLAN_SDIO_CMD PU by VCC_2.8V_PDA */
513 PIN(1, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
514 /* Xmmc3CDn PS_ALS_SCL_2.8V */
515 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
516 /* Xmmc3DATA[0] WLAN_SDIO_D PU by VCC_2.8V_PDA */
517 PIN(3, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
519 PIN(4, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
521 PIN(5, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
523 PIN(6, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
526 static const struct s5p_gpio_group group_l0[] __initdata = {
527 /* XGNSS_SYNC BUCK2_EN: MAX8997 SET3 */
528 PIN(0, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
529 /* XGNSS_ISIGN MHL_SEL(rev03, Not Using), NC(rev04) */
531 /* XGNSS_IMAG GPS_nRST */
533 /* XGNSS_QSIGN TSP_LDO_ON */
534 PIN(3, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
535 /* XGNSS_QMAG BT_EN */
536 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
537 /* XGNSS_MCLK 3_TOUCH_INT */
538 PIN(5, SFN(0xf), NONE, NOP, DRV1X, INPUT, NOP),
539 /* XGNSS_RF_RSTN USB_SEL */
540 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
541 /* XGNSS_CLKREQ OLED_DET */
542 PIN(7, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
545 static const struct s5p_gpio_group group_l1[] __initdata = {
546 /* XGNSS_SCL BT_nRST */
547 PIN(0, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
548 /* XGNSS_SDA MASSMEMORY_EN(rev03, NC), NC(rev04) */
550 /* XGNSS_EPOCH WLAN_EN */
551 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
554 static const struct s5p_gpio_group group_l2[] __initdata = {
555 /* XGNSS_GPIO_0 CAM_VGA_nSTBY */
556 PIN(0, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
557 /* XGNSS_GPIO_1 CAM_VGA_nRST */
558 PIN(1, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
559 /* XGNSS_GPIO_2 LCD_TE */
560 PIN(2, SFN(0x0), NONE, NOP, DRV1X, OUTPUT0, NOP),
561 /* XGNSS_GPIO_3 2MIC_PWDN (NC) */
563 /* XGNSS_GPIO_4 2MIC_RST (NC) */
565 /* XGNSS_GPIO_5 2MIC_EN (NC) */
567 /* XGNSS_GPIO_6 NFC_EN */
568 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
569 /* XGNSS_GPIO_7 NFC_FIRMWARE */
570 PIN(7, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
573 static const struct s5p_gpio_group group_l2_rev04[] __initdata = {
574 /* XGNSS_GPIO_0 CAM_VGA_nSTBY */
575 PIN(0, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
576 /* XGNSS_GPIO_1 CAM_VGA_nRST */
577 PIN(1, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
578 /* XGNSS_GPIO_2 NC */
580 /* XGNSS_GPIO_3 DOUBLE_RR */
582 /* XGNSS_GPIO_4 NC */
584 /* XGNSS_GPIO_5 NC */
586 /* XGNSS_GPIO_6 NFC_EN */
587 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
588 /* XGNSS_GPIO_7 NFC_FIRMWARE */
589 PIN(7, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
593 static const struct s5p_gpio_group group_x0[] = {
594 /* XEINT[0] GYRO_INT */
595 EXTPIN(0, SFN(0x0), NONE, PULLDOWN, DRV1X),
596 /* XEINT[1] GYRO_INT2 */
597 EXTPIN(1, SFN(0x0), NONE, PULLDOWN, DRV1X),
598 /* XEINT[2] PS_ALS_INT */
599 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
600 /* XEINT[3] BOOT_MODE */
601 EXTPIN(3, SFN(0x0), NONE, NOP, DRV1X),
602 /* XEINT[4] TSP_INT */
603 EXTPIN(4, SFN(0xf), NONE, NOP, DRV1X),
604 /* XEINT[5] BUCK1_EN_A */
605 EXTPIN(5, SFN(0x1), LOW, NOP, DRV1X),
606 /* XEINT[6] BUCK2_EN_A */
607 EXTPIN(6, SFN(0x1), LOW, NOP, DRV1X),
608 /* XEINT[7] AP_PMIC_IRQ PU by VCC_2.8V_PDA */
609 EXTPIN(7, SFN(0xf), NONE, NOP, DRV1X),
613 static const struct s5p_gpio_group group_x1[] = {
614 /* XEINT[8] IPC_SLAVE_WAKEUP */
615 EXTPIN(0, SFN(0x1), LOW, PULLDOWN, DRV1X),
616 /* XEINT[9] IPC_HOST_WAKEUP */
617 EXTPIN(1, SFN(0xf), NONE, NOP, DRV1X),
618 /* XEINT[10] CP_DUMP_INT : Don't know how to set up? */
619 EXTPIN(2, SFN(0x0), NONE, NOP, DRV1X),
620 /* XEINT[11] SUSPEND_REQUEST_HSIC */
621 EXTPIN(3, SFN(0xf), NONE, NOP, DRV1X),
622 /* XEINT[12] CP_PMU_RST */
623 EXTPIN(4, SFN(0x0), NONE, NOP, DRV1X),
624 /* XEINT[13] ISP_INT */
625 EXTPIN(5, SFN(0xf), NONE, NOP, DRV1X),
626 /* XEINT[14] PHONE_ACTIVE */
627 EXTPIN(6, SFN(0xf), NONE, PULLDOWN, DRV1X),
628 /* XEINT[15] NFC_IRQ */
629 EXTPIN(7, SFN(0x0), NONE, NOP, DRV1X),
633 static const struct s5p_gpio_group group_x2[] = {
634 /* XEINT[16] VOL_UP (VCC_2.8V_PDA) */
635 EXTPIN(0, SFN(0xf), NONE, NOP, DRV1X),
636 /* XEINT[17] VOL_DOWN (VCC_2.8V_PDA) */
637 EXTPIN(1, SFN(0xf), NONE, NOP, DRV1X),
638 /* XEINT[18] MSENSOR_INT */
639 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
640 /* XEINT[19] FUEL_ALERT */
641 EXTPIN(3, SFN(0xf), NONE, NOP, DRV1X),
642 /* XEINT[20] HDMI_EN1(rev03, Not using), NC(rev04) */
644 /* XEINT[21] WLAN_HOST_WAKE */
645 EXTPIN(5, SFN(0xf), NONE, PULLDOWN, DRV1X),
646 /* XEINT[22] BT_HOST_WAKE */
647 EXTPIN(6, SFN(0xf), NONE, PULLDOWN, DRV1X),
648 /* XEINT[23] nPOWER */
649 EXTPIN(7, SFN(0xf), NONE, NOP, DRV1X),
653 static const struct s5p_gpio_group group_x3[] = {
654 /* XEINT[24] ACC_INT */
655 EXTPIN(0, SFN(0xf), NONE, PULLDOWN, DRV1X),
656 /* XEINT[25] BT_WAKE */
657 EXTPIN(1, SFN(0x1), LOW, NOP, DRV1X),
658 /* XEINT[26] DET_3.5 */
659 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
660 /* XEINT[27] USB_OTG_EN */
661 EXTPIN(3, SFN(0x1), LOW, NOP, DRV1X),
662 /* XEINT[28] T_FLASH_DETECT */
663 EXTPIN(4, SFN(0xf), NONE, NOP, DRV1X),
664 /* XEINT[29] OK_KEY (VCC_2.8V_PDA) */
665 EXTPIN(5, SFN(0xf), NONE, NOP, DRV1X),
666 /* XEINT[30] EAR_SEND_END */
667 EXTPIN(6, SFN(0xf), NONE, NOP, DRV1X),
668 /* XEINT[31] HDMI_HPD */
669 EXTPIN(7, SFN(0xf), NONE, NOP, DRV1X),
672 static const struct s5p_gpio_group group_x3_rev04[] = {
673 /* XEINT[24] ACC_INT */
674 EXTPIN(0, SFN(0xf), NONE, PULLDOWN, DRV1X),
675 /* XEINT[25] BT_WAKE */
676 EXTPIN(1, SFN(0x1), LOW, NOP, DRV1X),
677 /* XEINT[26] DET_3.5 */
678 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
679 /* XEINT[27] USB_OTG_EN */
680 EXTPIN(3, SFN(0x1), LOW, NOP, DRV1X),
683 /* XEINT[29] OK_KEY (VCC_2.8V_PDA) */
684 EXTPIN(5, SFN(0xf), NONE, NOP, DRV1X),
685 /* XEINT[30] EAR_SEND_END */
686 EXTPIN(6, SFN(0xf), NONE, NOP, DRV1X),
691 static const struct s5p_gpio_group group_y0[] __initdata = {
692 /* Xm0CSn[0] NFC_SCL_1.8V */
693 PIN(0, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
694 /* Xm0CSn[1] NFC_SDA_1.8V */
695 PIN(1, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
696 /* Xm0CSn[2] POP_nCS */
697 PIN(2, SKIP_SFN, NONE, XXXXXX, DRV1X, OUTPUT1, NOP),
706 static const struct s5p_gpio_group group_y1[] __initdata = {
717 static const struct s5p_gpio_group group_y2[] __initdata = {
723 PIN(2, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, NOP),
732 static const struct s5p_gpio_group group_y3[] __initdata = {
733 /* Xm0ADDR[0] MHL_SDA_1.8V(rev03, Not using), NC(rev04) */
735 /* Xm0ADDR[1] LCD_SCLK */
736 PIN(1, SFN(0x1), NONE, NOP, DRV1X, OUTPUT0, NOP),
737 /* Xm0ADDR[2] MHL_SCL_1.8V(rev03, Not using), NC(rev04) */
740 PIN(3, SFN(0x1), NONE, NOP, DRV1X, OUTPUT0, NOP),
742 PIN(4, SFN(0x0), NONE, NOP, DRV1X, INPUT, PULLDOWN),
743 /* ACTIVE_STATE_HSIC */
744 PIN(5, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
745 /* Xm0ADDR[6] GPS_CNTL */
746 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
747 /* Xm0ADDR[7] ISP_RESET (active low) */
748 PIN(7, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
751 static const struct s5p_gpio_group group_y4[] __initdata = {
752 /* Xm0ADDR[8] FUEL_SDA_1.8V PU by VCC_1.8V_PDA */
753 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
754 /* Xm0ADDR[9] FUAL_SCL_1.8V PU by VCC_1.8V_PDA */
755 PIN(1, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
756 /* Xm0ADDR[10] PDA_ACTIVE */
757 PIN(2, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
758 /* Xm0ADDR[11] LCD_nCS */
759 PIN(3, SFN(0x1), NONE, NOP, DRV1X, OUTPUT0, NOP),
760 /* Xm0ADDR[12] LCD_SDO(rev03), NC(rev04) */
762 /* Xm0ADDR[13] MLCD_RST */
763 PIN(5, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
764 /* Xm0ADDR[14] RESET_REQ_N */
765 PIN(6, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
766 /* Xm0ADDR[15] UART_SEL */
767 PIN(7, SKIP_SFN, NONE, NOP, DRV1X, KEEP, NOP),
771 static const struct s5p_gpio_group group_y5[] __initdata = {
790 static const struct s5p_gpio_group group_y6[] __initdata = {
809 static const struct s5p_gpio_group group_z[] __initdata = {
810 /* Xi2s0SCLK MM_I2S_CLK */
811 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
814 /* Xi2s0LRCK MM_I2S_SYNC */
815 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
816 /* Xi2s0SDI MM_I2S_DI */
817 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
818 /* Xi2s0SDO[0] MM_I2S_DO */
819 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
826 /* Note: It contains the latest borad revision configuration */
827 static struct s5p_gpio_group_info c1_gpios[] __refdata = {
829 GPIO_(GROUP_A0, S5P_VA_GPIO, 0x000, group_a0),
830 GPIO_(GROUP_A1, S5P_VA_GPIO, 0x020, group_a1),
831 GPIO_(GROUP_B, S5P_VA_GPIO, 0x040, group_b),
832 GPIO_(GROUP_C0, S5P_VA_GPIO, 0x060, group_c0),
833 GPIO_(GROUP_C1, S5P_VA_GPIO, 0x080, group_c1),
834 GPIO_(GROUP_D0, S5P_VA_GPIO, 0x0A0, group_d0),
835 GPIO_(GROUP_D1, S5P_VA_GPIO, 0x0C0, group_d1),
836 GPIO_(GROUP_E0, S5P_VA_GPIO, 0x0E0, group_e0),
837 GPIO_(GROUP_E1, S5P_VA_GPIO, 0x100, group_e1),
838 GPIO_(GROUP_E2, S5P_VA_GPIO, 0x120, group_e2),
839 GPIO_(GROUP_E3, S5P_VA_GPIO, 0x140, group_e3),
840 GPIO_(GROUP_E4, S5P_VA_GPIO, 0x160, group_e4),
841 GPIO_(GROUP_F0, S5P_VA_GPIO, 0x180, group_f0),
842 GPIO_(GROUP_F1, S5P_VA_GPIO, 0x1A0, group_f1),
843 GPIO_(GROUP_F2, S5P_VA_GPIO, 0x1C0, group_f2),
844 GPIO_(GROUP_F3, S5P_VA_GPIO, 0x1E0, group_f3),
846 GPIO_(GROUP_J0, S5P_VA_GPIO2, 0x000, group_j0),
847 GPIO_(GROUP_J1, S5P_VA_GPIO2, 0x020, group_j1),
848 GPIO_(GROUP_K0, S5P_VA_GPIO2, 0x040, group_k0),
849 GPIO_(GROUP_K1, S5P_VA_GPIO2, 0x060, group_k1),
850 GPIO_(GROUP_K2, S5P_VA_GPIO2, 0x080, group_k2),
851 GPIO_(GROUP_K3, S5P_VA_GPIO2, 0x0A0, group_k3),
852 GPIO_(GROUP_L0, S5P_VA_GPIO2, 0x0C0, group_l0),
853 GPIO_(GROUP_L1, S5P_VA_GPIO2, 0x0E0, group_l1),
854 GPIO_(GROUP_L2, S5P_VA_GPIO2, 0x100, group_l2),
855 GPIO_(GROUP_Y0, S5P_VA_GPIO2, 0x120, group_y0),
856 GPIO_(GROUP_Y1, S5P_VA_GPIO2, 0x140, group_y1),
857 GPIO_(GROUP_Y2, S5P_VA_GPIO2, 0x160, group_y2),
858 GPIO_(GROUP_Y3, S5P_VA_GPIO2, 0x180, group_y3),
859 GPIO_(GROUP_Y4, S5P_VA_GPIO2, 0x1A0, group_y4),
860 GPIO_(GROUP_Y5, S5P_VA_GPIO2, 0x1C0, group_y5),
861 GPIO_(GROUP_Y6, S5P_VA_GPIO2, 0x1E0, group_y6),
862 /* External GPIOs & Alive block */
863 GPIO_(GROUP_X0, S5P_VA_GPIO2, 0xC00, group_x0),
864 GPIO_(GROUP_X1, S5P_VA_GPIO2, 0xC20, group_x1),
865 GPIO_(GROUP_X2, S5P_VA_GPIO2, 0xC40, group_x2),
866 GPIO_(GROUP_X3, S5P_VA_GPIO2, 0xC60, group_x3),
868 GPIO_(GROUP_Z, S5P_VA_GPIO3, 0x000, group_z),
871 static int mobile_gpios[] = {
872 [GPIO_MICBIAS_EN] = S5PV310_GPE1(4),
873 [GPIO_EAR_MICBIAS_EN] = S5PV310_GPE2(4),
874 [GPIO_DET_3_5] = S5PV310_GPX3(2),
875 [GPIO_EAR_SEND_END] = S5PV310_GPX3(6),
876 [GPIO_CP_ON] = S5PV310_GPC1(1),
877 [GPIO_IPC_SLAVE_WAKEUP] = S5PV310_GPX1(0),
878 [GPIO_IPC_HOST_WAKEUP] = S5PV310_GPX1(1),
879 [GPIO_CP_DUMP_INT] = S5PV310_GPX1(2),
880 [GPIO_SUSPEND_REQUEST_HSIC] = S5PV310_GPX1(3),
881 [GPIO_CP_PMU_RST] = S5PV310_GPX1(4),
882 [GPIO_PHONE_ACTIVE] = S5PV310_GPX1(6),
883 [GPIO_ACTIVE_STATE_HSIC] = S5PV310_GPY3(5),
884 [GPIO_PDA_ACTIVE] = S5PV310_GPY4(2),
885 [GPIO_RESET_REQ_N] = S5PV310_GPY4(6),
886 [GPIO_UART_SEL] = S5PV310_GPY4(7),
889 struct mobile_gpios_data c1_data;
891 void __init mobile_gpios_init_c1(void)
893 int hwrev = system_rev & 0xFF;
895 printk("Mobile GPIOs init - HW Rev %d\n", hwrev);
898 hwrev = 0x3; /* TEMP : Set as 0x2 or higher for phone booting */
905 c1_data.infos = c1_gpios;
906 c1_data.x0 = (struct s5p_gpio_group *)group_x0;
907 c1_data.x1 = (struct s5p_gpio_group *)group_x1;
908 c1_data.x2 = (struct s5p_gpio_group *)group_x2;
909 c1_data.x3 = (struct s5p_gpio_group *)group_x3;
910 c1_data.gpios = mobile_gpios;
912 c1_data.infos_size = ARRAY_SIZE(c1_gpios);
913 c1_data.x0_size = ARRAY_SIZE(group_x0);
914 c1_data.x1_size = ARRAY_SIZE(group_x1);
915 c1_data.x2_size = ARRAY_SIZE(group_x2);
916 c1_data.x3_size = ARRAY_SIZE(group_x3);
917 c1_data.gpios_size = ARRAY_SIZE(mobile_gpios);
922 c1_gpios[GROUP_B].group = group_b_rev04;
923 c1_gpios[GROUP_E1].group = group_e1_rev04;
924 c1_gpios[GROUP_E2].group = group_e2_rev04;
925 c1_gpios[GROUP_F3].group = group_f3_rev04;
926 c1_gpios[GROUP_J0].group = group_j0_rev04;
927 c1_gpios[GROUP_J1].group = group_j1_rev04;
928 c1_gpios[GROUP_K1].group = group_k1_rev04;
929 c1_gpios[GROUP_K2].group = group_k2_rev04;
930 c1_gpios[GROUP_L2].group = group_l2_rev04;
931 c1_data.infos = c1_gpios;
933 c1_data.x0 = (struct s5p_gpio_group *)group_x0;
934 c1_data.x1 = (struct s5p_gpio_group *)group_x1;
935 c1_data.x2 = (struct s5p_gpio_group *)group_x2;
936 c1_data.x3 = (struct s5p_gpio_group *)group_x3_rev04;
937 c1_data.gpios = mobile_gpios;
939 c1_data.infos_size = ARRAY_SIZE(c1_gpios);
940 c1_data.x0_size = ARRAY_SIZE(group_x0);
941 c1_data.x1_size = ARRAY_SIZE(group_x1);
942 c1_data.x2_size = ARRAY_SIZE(group_x2);
943 c1_data.x3_size = ARRAY_SIZE(group_x3);
944 c1_data.gpios_size = ARRAY_SIZE(mobile_gpios);
948 mobile_gpios_register(&c1_data);