2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Linux Kernel Configuration"
15 select SYS_SUPPORTS_APM_EMULATION
16 select GENERIC_ATOMIC64 if (!CPU_32v6K)
17 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
19 select HAVE_KPROBES if (!XIP_KERNEL)
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO
25 select HAVE_KERNEL_LZMA
26 select HAVE_PERF_EVENTS
27 select PERF_USE_VMALLOC
28 select HAVE_REGS_AND_STACK_ACCESS_API
30 The ARM series is a line of low-power-consumption RISC chip designs
31 licensed by ARM Ltd and targeted at embedded applications and
32 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
33 manufactured, but legacy ARM-based PC hardware remains popular in
34 Europe. There is an ARM Linux project with a web page at
35 <http://www.arm.linux.org.uk/>.
40 config SYS_SUPPORTS_APM_EMULATION
46 config ARCH_USES_GETTIMEOFFSET
50 config GENERIC_CLOCKEVENTS
53 config GENERIC_CLOCKEVENTS_BROADCAST
55 depends on GENERIC_CLOCKEVENTS
58 config ARCH_HAS_CPU_IDLE_WAIT
65 select GENERIC_ALLOCATOR
76 The Extended Industry Standard Architecture (EISA) bus was
77 developed as an open alternative to the IBM MicroChannel bus.
79 The EISA bus provided some of the features of the IBM MicroChannel
80 bus while maintaining backward compatibility with cards made for
81 the older ISA bus. The EISA bus saw limited use between 1988 and
82 1995 when it was made obsolete by the PCI bus.
84 Say Y here if you are building a kernel for an EISA-based machine.
94 MicroChannel Architecture is found in some IBM PS/2 machines and
95 laptops. It is a bus system similar to PCI or ISA. See
96 <file:Documentation/mca.txt> (and especially the web page given
97 there) before attempting to build an MCA bus kernel.
99 config GENERIC_HARDIRQS
103 config STACKTRACE_SUPPORT
107 config HAVE_LATENCYTOP_SUPPORT
112 config LOCKDEP_SUPPORT
116 config TRACE_IRQFLAGS_SUPPORT
120 config HARDIRQS_SW_RESEND
124 config GENERIC_IRQ_PROBE
128 config GENERIC_LOCKBREAK
131 depends on SMP && PREEMPT
133 config RWSEM_GENERIC_SPINLOCK
137 config RWSEM_XCHGADD_ALGORITHM
140 config ARCH_HAS_ILOG2_U32
143 config ARCH_HAS_ILOG2_U64
146 config ARCH_HAS_CPUFREQ
149 Internal node to signify that the ARCH has CPUFREQ support
150 and that the relevant menu configurations are displayed for
153 config GENERIC_HWEIGHT
157 config GENERIC_CALIBRATE_DELAY
161 config ARCH_MAY_HAVE_PC_FDC
167 config NEED_DMA_MAP_STATE
170 config GENERIC_ISA_DMA
179 config GENERIC_HARDIRQS_NO__DO_IRQ
182 config ARM_L1_CACHE_SHIFT_6
185 Setting ARM L1 cache line size to 64 Bytes.
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARCH_HIBERNATION_POSSIBLE
199 source "init/Kconfig"
201 source "kernel/Kconfig.freezer"
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
210 support by paged memory management. If unsure, say 'Y'.
213 # The "ARM system type" choice list is ordered alphabetically by option
214 # text. Please add new entries in the option alphabetic order.
217 prompt "ARM system type"
218 default ARCH_VERSATILE
221 bool "Agilent AAEC-2000 based"
225 select ARCH_USES_GETTIMEOFFSET
227 This enables support for systems based on the Agilent AAEC-2000
229 config ARCH_INTEGRATOR
230 bool "ARM Ltd. Integrator family"
232 select ARCH_HAS_CPUFREQ
235 select GENERIC_CLOCKEVENTS
236 select PLAT_VERSATILE
238 Support for ARM's Integrator platform.
241 bool "ARM Ltd. RealView family"
245 select GENERIC_CLOCKEVENTS
246 select ARCH_WANT_OPTIONAL_GPIOLIB
247 select PLAT_VERSATILE
248 select ARM_TIMER_SP804
249 select GPIO_PL061 if GPIOLIB
251 This enables support for ARM Ltd RealView boards.
253 config ARCH_VERSATILE
254 bool "ARM Ltd. Versatile family"
259 select GENERIC_CLOCKEVENTS
260 select ARCH_WANT_OPTIONAL_GPIOLIB
261 select PLAT_VERSATILE
262 select ARM_TIMER_SP804
264 This enables support for ARM Ltd Versatile board.
267 bool "ARM Ltd. Versatile Express family"
268 select ARCH_WANT_OPTIONAL_GPIOLIB
270 select ARM_TIMER_SP804
272 select GENERIC_CLOCKEVENTS
275 select PLAT_VERSATILE
277 This enables support for the ARM Ltd Versatile Express boards.
281 select ARCH_REQUIRE_GPIOLIB
284 This enables support for systems based on the Atmel AT91RM9200,
285 AT91SAM9 and AT91CAP9 processors.
288 bool "Broadcom BCMRING"
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 Support for Broadcom's BCMRing platform.
299 bool "Cirrus Logic CLPS711x/EP721x-based"
301 select ARCH_USES_GETTIMEOFFSET
303 Support for Cirrus Logic 711x/721x based boards.
306 bool "Cavium Networks CNS3XXX family"
308 select GENERIC_CLOCKEVENTS
310 select PCI_DOMAINS if PCI
312 Support for Cavium Networks CNS3XXX platform.
315 bool "Cortina Systems Gemini"
317 select ARCH_REQUIRE_GPIOLIB
318 select ARCH_USES_GETTIMEOFFSET
320 Support for the Cortina Systems Gemini family SoCs
327 select ARCH_USES_GETTIMEOFFSET
329 This is an evaluation board for the StrongARM processor available
330 from Digital. It has limited hardware on-board, including an
331 Ethernet interface, two PCMCIA sockets, two serial ports and a
340 select ARCH_REQUIRE_GPIOLIB
341 select ARCH_HAS_HOLES_MEMORYMODEL
342 select ARCH_USES_GETTIMEOFFSET
344 This enables support for the Cirrus EP93xx series of CPUs.
346 config ARCH_FOOTBRIDGE
350 select ARCH_USES_GETTIMEOFFSET
352 Support for systems based on the DC21285 companion chip
353 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
356 bool "Freescale MXC/iMX-based"
357 select GENERIC_CLOCKEVENTS
358 select ARCH_REQUIRE_GPIOLIB
361 Support for Freescale MXC/iMX-based family of processors
364 bool "Freescale STMP3xxx"
367 select ARCH_REQUIRE_GPIOLIB
368 select GENERIC_CLOCKEVENTS
369 select USB_ARCH_HAS_EHCI
371 Support for systems based on the Freescale 3xxx CPUs.
374 bool "Hilscher NetX based"
377 select GENERIC_CLOCKEVENTS
379 This enables support for systems based on the Hilscher NetX Soc
382 bool "Hynix HMS720x-based"
385 select ARCH_USES_GETTIMEOFFSET
387 This enables support for systems based on the Hynix HMS720x
395 select ARCH_SUPPORTS_MSI
398 Support for Intel's IOP13XX (XScale) family of processors.
406 select ARCH_REQUIRE_GPIOLIB
408 Support for Intel's 80219 and IOP32X (XScale) family of
417 select ARCH_REQUIRE_GPIOLIB
419 Support for Intel's IOP33X (XScale) family of processors.
426 select ARCH_USES_GETTIMEOFFSET
428 Support for Intel's IXP23xx (XScale) family of processors.
431 bool "IXP2400/2800-based"
435 select ARCH_USES_GETTIMEOFFSET
437 Support for Intel's IXP2400/2800 (XScale) family of processors.
444 select GENERIC_CLOCKEVENTS
445 select DMABOUNCE if PCI
447 Support for Intel's IXP4XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
453 select GENERIC_CLOCKEVENTS
456 Support for the Marvell Dove SoC 88AP510
459 bool "Marvell Kirkwood"
462 select ARCH_REQUIRE_GPIOLIB
463 select GENERIC_CLOCKEVENTS
466 Support for the following Marvell Kirkwood series SoCs:
467 88F6180, 88F6192 and 88F6281.
470 bool "Marvell Loki (88RC8480)"
472 select GENERIC_CLOCKEVENTS
475 Support for the Marvell Loki (88RC8480) SoC.
480 select ARCH_REQUIRE_GPIOLIB
483 select USB_ARCH_HAS_OHCI
486 select GENERIC_CLOCKEVENTS
488 Support for the NXP LPC32XX family of processors
491 bool "Marvell MV78xx0"
494 select ARCH_REQUIRE_GPIOLIB
495 select GENERIC_CLOCKEVENTS
498 Support for the following Marvell MV78xx0 series SoCs:
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
510 Support for the following Marvell Orion 5x series SoCs:
511 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
512 Orion-2 (5281), Orion-1-90 (6183).
515 bool "Marvell PXA168/910/MMP2"
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
523 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
526 bool "Micrel/Kendin KS8695"
528 select ARCH_REQUIRE_GPIOLIB
529 select ARCH_USES_GETTIMEOFFSET
531 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
532 System-on-Chip devices.
535 bool "NetSilicon NS9xxx"
538 select GENERIC_CLOCKEVENTS
541 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
544 <http://www.digi.com/products/microprocessors/index.jsp>
547 bool "Nuvoton W90X900 CPU"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
553 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
554 At present, the w90x900 has been renamed nuc900, regarding
555 the ARM series product line, you can login the following
556 link address to know more.
558 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
559 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
562 bool "Nuvoton NUC93X CPU"
566 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
567 low-power and high performance MPEG-4/JPEG multimedia controller chip.
572 select GENERIC_CLOCKEVENTS
576 select ARCH_HAS_BARRIERS if CACHE_L2X0
578 This enables support for NVIDIA Tegra based systems (Tegra APX,
579 Tegra 6xx and Tegra 2 series).
582 bool "Philips Nexperia PNX4008 Mobile"
585 select ARCH_USES_GETTIMEOFFSET
587 This enables support for Philips PNX4008 mobile platform.
590 bool "PXA2xx/PXA3xx-based"
593 select ARCH_HAS_CPUFREQ
595 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
600 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
605 select GENERIC_CLOCKEVENTS
606 select ARCH_REQUIRE_GPIOLIB
608 Support for Qualcomm MSM/QSD based systems. This runs on the
609 apps processor of the MSM/QSD and depends on a shared memory
610 interface to the modem processor which runs the baseband
611 stack and controls some vital subsystems
612 (clock and power control, etc).
615 bool "Renesas SH-Mobile"
617 Support for Renesas's SH-Mobile ARM platforms
624 select ARCH_MAY_HAVE_PC_FDC
625 select HAVE_PATA_PLATFORM
628 select ARCH_SPARSEMEM_ENABLE
629 select ARCH_USES_GETTIMEOFFSET
631 On the Acorn Risc-PC, Linux can support the internal IDE disk and
632 CD-ROM interface, serial and parallel port, and the floppy drive.
638 select ARCH_SPARSEMEM_ENABLE
640 select ARCH_HAS_CPUFREQ
642 select GENERIC_CLOCKEVENTS
645 select ARCH_REQUIRE_GPIOLIB
647 Support for StrongARM 11x0 based boards.
650 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
652 select ARCH_HAS_CPUFREQ
654 select ARCH_USES_GETTIMEOFFSET
655 select HAVE_S3C2410_I2C
657 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
658 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
659 the Samsung SMDK2410 development board (and derivatives).
661 Note, the S3C2416 and the S3C2450 are so close that they even share
662 the same SoC ID code. This means that there is no seperate machine
663 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
666 bool "Samsung S3C64XX"
672 select ARCH_USES_GETTIMEOFFSET
673 select ARCH_HAS_CPUFREQ
674 select ARCH_REQUIRE_GPIOLIB
675 select SAMSUNG_CLKSRC
676 select SAMSUNG_IRQ_VIC_TIMER
677 select SAMSUNG_IRQ_UART
678 select S3C_GPIO_TRACK
679 select S3C_GPIO_PULL_UPDOWN
680 select S3C_GPIO_CFG_S3C24XX
681 select S3C_GPIO_CFG_S3C64XX
683 select USB_ARCH_HAS_OHCI
684 select SAMSUNG_GPIOLIB_4BIT
685 select HAVE_S3C2410_I2C
686 select HAVE_S3C2410_WATCHDOG
688 Samsung S3C64XX series based systems
691 bool "Samsung S5P6440"
695 select HAVE_S3C2410_WATCHDOG
696 select ARCH_USES_GETTIMEOFFSET
697 select HAVE_S3C2410_I2C
700 Samsung S5P6440 CPU based systems
703 bool "Samsung S5P6442"
707 select ARCH_USES_GETTIMEOFFSET
708 select HAVE_S3C2410_WATCHDOG
710 Samsung S5P6442 CPU based systems
713 bool "Samsung S5PC100"
717 select ARM_L1_CACHE_SHIFT_6
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C
721 select HAVE_S3C2410_WATCHDOG
723 Samsung S5PC100 series based systems
726 bool "Samsung S5PV210/S5PC110"
730 select GENERIC_CLOCKEVENTS
731 select ARM_L1_CACHE_SHIFT_6
732 select HAVE_S3C2410_I2C
734 select HAVE_S3C2410_WATCHDOG
736 Samsung S5PV210/S5PC110 series based systems
739 bool "Samsung S5PV310/S5PC210"
743 select GENERIC_CLOCKEVENTS
744 select HAVE_S3C2410_I2C
747 Samsung S5PV310 series based systems
756 select ARCH_USES_GETTIMEOFFSET
758 Support for the StrongARM based Digital DNARD machine, also known
759 as "Shark" (<http://www.shark-linux.de/shark.html>).
764 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
765 select ARCH_USES_GETTIMEOFFSET
767 Say Y here for systems based on one of the Sharp LH7A40X
768 System on a Chip processors. These CPUs include an ARM922T
769 core with a wide array of integrated devices for
770 hand-held and low-power applications.
773 bool "ST-Ericsson U300 Series"
779 select GENERIC_CLOCKEVENTS
783 Support for ST-Ericsson U300 series mobile platforms.
786 bool "ST-Ericsson U8500 Series"
789 select GENERIC_CLOCKEVENTS
791 select ARCH_REQUIRE_GPIOLIB
793 Support for ST-Ericsson's Ux500 architecture
796 bool "STMicroelectronics Nomadik"
801 select GENERIC_CLOCKEVENTS
802 select ARCH_REQUIRE_GPIOLIB
804 Support for the Nomadik platform by ST-Ericsson
808 select GENERIC_CLOCKEVENTS
809 select ARCH_REQUIRE_GPIOLIB
813 select GENERIC_ALLOCATOR
814 select ARCH_HAS_HOLES_MEMORYMODEL
816 Support for TI's DaVinci platform.
821 select ARCH_REQUIRE_GPIOLIB
822 select ARCH_HAS_CPUFREQ
823 select GENERIC_CLOCKEVENTS
824 select ARCH_HAS_HOLES_MEMORYMODEL
826 Support for TI's OMAP platform (OMAP1 and OMAP2).
831 select ARCH_REQUIRE_GPIOLIB
833 select GENERIC_CLOCKEVENTS
836 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
841 # This is sorted alphabetically by mach-* pathname. However, plat-*
842 # Kconfigs may be included either alphabetically (according to the
843 # plat- suffix) or along side the corresponding mach-* source.
845 source "arch/arm/mach-aaec2000/Kconfig"
847 source "arch/arm/mach-at91/Kconfig"
849 source "arch/arm/mach-bcmring/Kconfig"
851 source "arch/arm/mach-clps711x/Kconfig"
853 source "arch/arm/mach-cns3xxx/Kconfig"
855 source "arch/arm/mach-davinci/Kconfig"
857 source "arch/arm/mach-dove/Kconfig"
859 source "arch/arm/mach-ep93xx/Kconfig"
861 source "arch/arm/mach-footbridge/Kconfig"
863 source "arch/arm/mach-gemini/Kconfig"
865 source "arch/arm/mach-h720x/Kconfig"
867 source "arch/arm/mach-integrator/Kconfig"
869 source "arch/arm/mach-iop32x/Kconfig"
871 source "arch/arm/mach-iop33x/Kconfig"
873 source "arch/arm/mach-iop13xx/Kconfig"
875 source "arch/arm/mach-ixp4xx/Kconfig"
877 source "arch/arm/mach-ixp2000/Kconfig"
879 source "arch/arm/mach-ixp23xx/Kconfig"
881 source "arch/arm/mach-kirkwood/Kconfig"
883 source "arch/arm/mach-ks8695/Kconfig"
885 source "arch/arm/mach-lh7a40x/Kconfig"
887 source "arch/arm/mach-loki/Kconfig"
889 source "arch/arm/mach-lpc32xx/Kconfig"
891 source "arch/arm/mach-msm/Kconfig"
893 source "arch/arm/mach-mv78xx0/Kconfig"
895 source "arch/arm/plat-mxc/Kconfig"
897 source "arch/arm/mach-netx/Kconfig"
899 source "arch/arm/mach-nomadik/Kconfig"
900 source "arch/arm/plat-nomadik/Kconfig"
902 source "arch/arm/mach-ns9xxx/Kconfig"
904 source "arch/arm/mach-nuc93x/Kconfig"
906 source "arch/arm/plat-omap/Kconfig"
908 source "arch/arm/mach-omap1/Kconfig"
910 source "arch/arm/mach-omap2/Kconfig"
912 source "arch/arm/mach-orion5x/Kconfig"
914 source "arch/arm/mach-pxa/Kconfig"
915 source "arch/arm/plat-pxa/Kconfig"
917 source "arch/arm/mach-mmp/Kconfig"
919 source "arch/arm/mach-realview/Kconfig"
921 source "arch/arm/mach-sa1100/Kconfig"
923 source "arch/arm/plat-samsung/Kconfig"
924 source "arch/arm/plat-s3c24xx/Kconfig"
925 source "arch/arm/plat-s5p/Kconfig"
927 source "arch/arm/plat-spear/Kconfig"
930 source "arch/arm/mach-s3c2400/Kconfig"
931 source "arch/arm/mach-s3c2410/Kconfig"
932 source "arch/arm/mach-s3c2412/Kconfig"
933 source "arch/arm/mach-s3c2416/Kconfig"
934 source "arch/arm/mach-s3c2440/Kconfig"
935 source "arch/arm/mach-s3c2443/Kconfig"
939 source "arch/arm/mach-s3c64xx/Kconfig"
942 source "arch/arm/mach-s5p6440/Kconfig"
944 source "arch/arm/mach-s5p6442/Kconfig"
946 source "arch/arm/mach-s5pc100/Kconfig"
948 source "arch/arm/mach-s5pv210/Kconfig"
950 source "arch/arm/mach-s5pv310/Kconfig"
952 source "arch/arm/mach-shmobile/Kconfig"
954 source "arch/arm/plat-stmp3xxx/Kconfig"
956 source "arch/arm/mach-tegra/Kconfig"
958 source "arch/arm/mach-u300/Kconfig"
960 source "arch/arm/mach-ux500/Kconfig"
962 source "arch/arm/mach-versatile/Kconfig"
964 source "arch/arm/mach-vexpress/Kconfig"
966 source "arch/arm/mach-w90x900/Kconfig"
968 # Definitions to make life easier
974 select GENERIC_CLOCKEVENTS
982 config PLAT_VERSATILE
985 config ARM_TIMER_SP804
988 source arch/arm/mm/Kconfig
991 bool "Enable iWMMXt support"
992 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
993 default y if PXA27x || PXA3xx || ARCH_MMP
995 Enable support for iWMMXt context switching at run time if
996 running on a CPU that supports it.
998 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1001 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1005 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1006 (!ARCH_OMAP3 || OMAP3_EMU)
1010 config CPU_DYNAMIC_CLOCK_GATING
1011 bool "Enable dynamic clock gating for Cortex-A9"
1014 Enable dynamic high level clock gating of the integer core,
1015 the system control block and the Data Engine, if implemented.
1018 source "arch/arm/Kconfig-nommu"
1021 config ARM_ERRATA_411920
1022 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1023 depends on CPU_V6 && !SMP
1025 Invalidation of the Instruction Cache operation can
1026 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1027 It does not affect the MPCore. This option enables the ARM Ltd.
1028 recommended workaround.
1030 config ARM_ERRATA_430973
1031 bool "ARM errata: Stale prediction on replaced interworking branch"
1034 This option enables the workaround for the 430973 Cortex-A8
1035 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1036 interworking branch is replaced with another code sequence at the
1037 same virtual address, whether due to self-modifying code or virtual
1038 to physical address re-mapping, Cortex-A8 does not recover from the
1039 stale interworking branch prediction. This results in Cortex-A8
1040 executing the new code sequence in the incorrect ARM or Thumb state.
1041 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1042 and also flushes the branch target cache at every context switch.
1043 Note that setting specific bits in the ACTLR register may not be
1044 available in non-secure mode.
1046 config ARM_ERRATA_458693
1047 bool "ARM errata: Processor deadlock when a false hazard is created"
1050 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1051 erratum. For very specific sequences of memory operations, it is
1052 possible for a hazard condition intended for a cache line to instead
1053 be incorrectly associated with a different cache line. This false
1054 hazard might then cause a processor deadlock. The workaround enables
1055 the L1 caching of the NEON accesses and disables the PLD instruction
1056 in the ACTLR register. Note that setting specific bits in the ACTLR
1057 register may not be available in non-secure mode.
1059 config ARM_ERRATA_460075
1060 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1063 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1064 erratum. Any asynchronous access to the L2 cache may encounter a
1065 situation in which recent store transactions to the L2 cache are lost
1066 and overwritten with stale memory contents from external memory. The
1067 workaround disables the write-allocate mode for the L2 cache via the
1068 ACTLR register. Note that setting specific bits in the ACTLR register
1069 may not be available in non-secure mode.
1071 config ARM_ERRATA_742230
1072 bool "ARM errata: DMB operation may be faulty"
1073 depends on CPU_V7 && SMP
1075 This option enables the workaround for the 742230 Cortex-A9
1076 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1077 between two write operations may not ensure the correct visibility
1078 ordering of the two writes. This workaround sets a specific bit in
1079 the diagnostic register of the Cortex-A9 which causes the DMB
1080 instruction to behave as a DSB, ensuring the correct behaviour of
1083 config ARM_ERRATA_742231
1084 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1085 depends on CPU_V7 && SMP
1087 This option enables the workaround for the 742231 Cortex-A9
1088 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1089 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1090 accessing some data located in the same cache line, may get corrupted
1091 data due to bad handling of the address hazard when the line gets
1092 replaced from one of the CPUs at the same time as another CPU is
1093 accessing it. This workaround sets specific bits in the diagnostic
1094 register of the Cortex-A9 which reduces the linefill issuing
1095 capabilities of the processor.
1097 config PL310_ERRATA_588369
1098 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1099 depends on CACHE_L2X0 && ARCH_OMAP4
1101 The PL310 L2 cache controller implements three types of Clean &
1102 Invalidate maintenance operations: by Physical Address
1103 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1104 They are architecturally defined to behave as the execution of a
1105 clean operation followed immediately by an invalidate operation,
1106 both performing to the same memory location. This functionality
1107 is not correctly implemented in PL310 as clean lines are not
1108 invalidated as a result of these operations. Note that this errata
1109 uses Texas Instrument's secure monitor api.
1111 config ARM_ERRATA_720789
1112 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1113 depends on CPU_V7 && SMP
1115 This option enables the workaround for the 720789 Cortex-A9 (prior to
1116 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1117 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1118 As a consequence of this erratum, some TLB entries which should be
1119 invalidated are not, resulting in an incoherency in the system page
1120 tables. The workaround changes the TLB flushing routines to invalidate
1121 entries regardless of the ASID.
1123 config ARM_ERRATA_743622
1124 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1127 This option enables the workaround for the 743622 Cortex-A9
1128 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1129 optimisation in the Cortex-A9 Store Buffer may lead to data
1130 corruption. This workaround sets a specific bit in the diagnostic
1131 register of the Cortex-A9 which disables the Store Buffer
1132 optimisation, preventing the defect from occurring. This has no
1133 visible impact on the overall performance or power consumption of the
1136 config ARM_ERRATA_751472
1137 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1138 depends on CPU_V7 && SMP
1140 This option enables the workaround for the 751472 Cortex-A9 (prior
1141 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1142 completion of a following broadcasted operation if the second
1143 operation is received by a CPU before the ICIALLUIS has completed,
1144 potentially leading to corrupted entries in the cache or TLB.
1146 config ARM_ERRATA_753970
1147 bool "ARM errata: cache sync operation may be faulty"
1148 depends on CACHE_PL310
1150 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1152 Under some condition the effect of cache sync operation on
1153 the store buffer still remains when the operation completes.
1154 This means that the store buffer is always asked to drain and
1155 this prevents it from merging any further writes. The workaround
1156 is to replace the normal offset of cache sync operation (0x730)
1157 by another offset targeting an unmapped PL310 register 0x740.
1158 This has the same effect as the cache sync operation: store buffer
1159 drain and waiting for all buffers empty.
1161 config ARM_ERRATA_764369
1162 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1163 depends on CPU_V7 && SMP
1165 This option enables the workaround for erratum 764369
1166 affecting Cortex-A9 MPCore with two or more processors (all
1167 current revisions). Under certain timing circumstances, a data
1168 cache line maintenance operation by MVA targeting an Inner
1169 Shareable memory region may fail to proceed up to either the
1170 Point of Coherency or to the Point of Unification of the
1171 system. This workaround adds a DSB instruction before the
1172 relevant cache maintenance functions and sets a specific bit
1173 in the diagnostic control register of the SCU.
1177 source "arch/arm/common/Kconfig"
1187 Find out whether you have ISA slots on your motherboard. ISA is the
1188 name of a bus system, i.e. the way the CPU talks to the other stuff
1189 inside your box. Other bus systems are PCI, EISA, MicroChannel
1190 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1191 newer boards don't support it. If you have ISA, say Y, otherwise N.
1193 # Select ISA DMA controller support
1198 # Select ISA DMA interface
1203 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1205 Find out whether you have a PCI motherboard. PCI is the name of a
1206 bus system, i.e. the way the CPU talks to the other stuff inside
1207 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1208 VESA. If you have PCI, say Y, otherwise N.
1217 # Select the host bridge type
1218 config PCI_HOST_VIA82C505
1220 depends on PCI && ARCH_SHARK
1223 config PCI_HOST_ITE8152
1225 depends on PCI && MACH_ARMCORE
1229 source "drivers/pci/Kconfig"
1231 source "drivers/pcmcia/Kconfig"
1235 menu "Kernel Features"
1237 source "kernel/time/Kconfig"
1240 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1241 depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
1242 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
1243 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1244 depends on GENERIC_CLOCKEVENTS
1245 select USE_GENERIC_SMP_HELPERS
1246 select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\
1247 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
1249 This enables support for systems with more than one CPU. If you have
1250 a system with only one CPU, like most personal computers, say N. If
1251 you have a system with more than one CPU, say Y.
1253 If you say N here, the kernel will run on single and multiprocessor
1254 machines, but will use only one CPU of a multiprocessor machine. If
1255 you say Y here, the kernel will run on many, but not all, single
1256 processor machines. On a single processor machine, the kernel will
1257 run faster if you say N here.
1259 See also <file:Documentation/i386/IO-APIC.txt>,
1260 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1261 <http://www.linuxdoc.org/docs.html#howto>.
1263 If you don't know what to do here, say N.
1269 This option enables support for the ARM system coherency unit
1275 This options enables support for the ARM timer and watchdog unit
1278 prompt "Memory split"
1281 Select the desired split between kernel and user memory.
1283 If you are not absolutely sure what you are doing, leave this
1287 bool "3G/1G user/kernel split"
1289 bool "2G/2G user/kernel split"
1291 bool "1G/3G user/kernel split"
1296 default 0x40000000 if VMSPLIT_1G
1297 default 0x80000000 if VMSPLIT_2G
1301 int "Maximum number of CPUs (2-32)"
1307 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1308 depends on SMP && HOTPLUG && EXPERIMENTAL
1310 Say Y here to experiment with turning CPUs off and on. CPUs
1311 can be controlled through /sys/devices/system/cpu.
1314 bool "Use local timer interrupts"
1315 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
1316 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1317 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1319 select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || \
1320 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS
1322 Enable support for local timers on SMP platforms, rather then the
1323 legacy IPI broadcast method. Local timers allows the system
1324 accounting to be spread across the timer interval, preventing a
1325 "thundering herd" at every timer tick.
1327 source kernel/Kconfig.preempt
1331 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
1332 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1333 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1334 default AT91_TIMER_HZ if ARCH_AT91
1335 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1338 config THUMB2_KERNEL
1339 bool "Compile the kernel in Thumb-2 mode"
1340 depends on CPU_V7 && EXPERIMENTAL
1342 select ARM_ASM_UNIFIED
1344 By enabling this option, the kernel will be compiled in
1345 Thumb-2 mode. A compiler/assembler that understand the unified
1346 ARM-Thumb syntax is needed.
1350 config ARM_ASM_UNIFIED
1354 bool "Use the ARM EABI to compile the kernel"
1356 This option allows for the kernel to be compiled using the latest
1357 ARM ABI (aka EABI). This is only useful if you are using a user
1358 space environment that is also compiled with EABI.
1360 Since there are major incompatibilities between the legacy ABI and
1361 EABI, especially with regard to structure member alignment, this
1362 option also changes the kernel syscall calling convention to
1363 disambiguate both ABIs and allow for backward compatibility support
1364 (selected with CONFIG_OABI_COMPAT).
1366 To use this you need GCC version 4.0.0 or later.
1369 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1370 depends on AEABI && EXPERIMENTAL
1373 This option preserves the old syscall interface along with the
1374 new (ARM EABI) one. It also provides a compatibility layer to
1375 intercept syscalls that have structure arguments which layout
1376 in memory differs between the legacy ABI and the new ARM EABI
1377 (only for non "thumb" binaries). This option adds a tiny
1378 overhead to all syscalls and produces a slightly larger kernel.
1379 If you know you'll be using only pure EABI user space then you
1380 can say N here. If this option is not selected and you attempt
1381 to execute a legacy ABI binary then the result will be
1382 UNPREDICTABLE (in fact it can be predicted that it won't work
1383 at all). If in doubt say Y.
1385 config ARCH_HAS_HOLES_MEMORYMODEL
1388 config ARCH_SPARSEMEM_ENABLE
1391 config ARCH_SPARSEMEM_DEFAULT
1392 def_bool ARCH_SPARSEMEM_ENABLE
1394 config ARCH_SELECT_MEMORY_MODEL
1395 def_bool ARCH_SPARSEMEM_ENABLE
1398 bool "High Memory Support (EXPERIMENTAL)"
1399 depends on MMU && EXPERIMENTAL
1401 The address space of ARM processors is only 4 Gigabytes large
1402 and it has to accommodate user address space, kernel address
1403 space as well as some memory mapped IO. That means that, if you
1404 have a large amount of physical memory and/or IO, not all of the
1405 memory can be "permanently mapped" by the kernel. The physical
1406 memory that is not permanently mapped is called "high memory".
1408 Depending on the selected kernel/user memory split, minimum
1409 vmalloc space and actual amount of RAM, you may not need this
1410 option which should result in a slightly faster kernel.
1415 bool "Allocate 2nd-level pagetables from highmem"
1417 depends on !OUTER_CACHE
1419 config HW_PERF_EVENTS
1420 bool "Enable hardware performance counter support for perf events"
1421 depends on PERF_EVENTS && CPU_HAS_PMU
1424 Enable hardware performance counter support for perf events. If
1425 disabled, perf events will use software events only.
1430 This enables support for sparse irqs. This is useful in general
1431 as most CPUs have a fairly sparse array of IRQ vectors, which
1432 the irq_desc then maps directly on to. Systems with a high
1433 number of off-chip IRQs will want to treat this as
1434 experimental until they have been independently verified.
1438 config FORCE_MAX_ZONEORDER
1439 int "Maximum zone order" if ARCH_SHMOBILE
1440 range 11 64 if ARCH_SHMOBILE
1441 default "9" if SA1111
1444 The kernel memory allocator divides physically contiguous memory
1445 blocks into "zones", where each zone is a power of two number of
1446 pages. This option selects the largest power of two that the kernel
1447 keeps in the memory allocator. If you need to allocate very large
1448 blocks of physically contiguous memory, then you may need to
1449 increase this value.
1451 This config option is actually maximum order plus one. For example,
1452 a value of 11 means that the largest free memory block is 2^10 pages.
1455 bool "Timer and CPU usage LEDs"
1456 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1457 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1458 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1459 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1460 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1461 ARCH_AT91 || ARCH_DAVINCI || \
1462 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1464 If you say Y here, the LEDs on your machine will be used
1465 to provide useful information about your current system status.
1467 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1468 be able to select which LEDs are active using the options below. If
1469 you are compiling a kernel for the EBSA-110 or the LART however, the
1470 red LED will simply flash regularly to indicate that the system is
1471 still functional. It is safe to say Y here if you have a CATS
1472 system, but the driver will do nothing.
1475 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1476 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1477 || MACH_OMAP_PERSEUS2
1479 depends on !GENERIC_CLOCKEVENTS
1480 default y if ARCH_EBSA110
1482 If you say Y here, one of the system LEDs (the green one on the
1483 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1484 will flash regularly to indicate that the system is still
1485 operational. This is mainly useful to kernel hackers who are
1486 debugging unstable kernels.
1488 The LART uses the same LED for both Timer LED and CPU usage LED
1489 functions. You may choose to use both, but the Timer LED function
1490 will overrule the CPU usage LED.
1493 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1495 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1496 || MACH_OMAP_PERSEUS2
1499 If you say Y here, the red LED will be used to give a good real
1500 time indication of CPU usage, by lighting whenever the idle task
1501 is not currently executing.
1503 The LART uses the same LED for both Timer LED and CPU usage LED
1504 functions. You may choose to use both, but the Timer LED function
1505 will overrule the CPU usage LED.
1507 config ALIGNMENT_TRAP
1509 depends on CPU_CP15_MMU
1510 default y if !ARCH_EBSA110
1511 select HAVE_PROC_CPU if PROC_FS
1513 ARM processors cannot fetch/store information which is not
1514 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1515 address divisible by 4. On 32-bit ARM processors, these non-aligned
1516 fetch/store instructions will be emulated in software if you say
1517 here, which has a severe performance impact. This is necessary for
1518 correct operation of some network protocols. With an IP-only
1519 configuration it is safe to say N, otherwise say Y.
1521 config UACCESS_WITH_MEMCPY
1522 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1523 depends on MMU && EXPERIMENTAL
1524 default y if CPU_FEROCEON
1526 Implement faster copy_to_user and clear_user methods for CPU
1527 cores where a 8-word STM instruction give significantly higher
1528 memory write throughput than a sequence of individual 32bit stores.
1530 A possible side effect is a slight increase in scheduling latency
1531 between threads sharing the same address space if they invoke
1532 such copy operations with large buffers.
1534 However, if the CPU data cache is using a write-allocate mode,
1535 this option is unlikely to provide any performance gain.
1537 config CC_STACKPROTECTOR
1538 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1540 This option turns on the -fstack-protector GCC feature. This
1541 feature puts, at the beginning of functions, a canary value on
1542 the stack just before the return address, and validates
1543 the value just before actually returning. Stack based buffer
1544 overflows (that need to overwrite this return address) now also
1545 overwrite the canary, which gets detected and the attack is then
1546 neutralized via a kernel panic.
1547 This feature requires gcc version 4.2 or above.
1549 config DEPRECATED_PARAM_STRUCT
1550 bool "Provide old way to pass kernel parameters"
1552 This was deprecated in 2001 and announced to live on for 5 years.
1553 Some old boot loaders still use this way.
1559 # Compressed boot loader in ROM. Yes, we really want to ask about
1560 # TEXT and BSS so we preserve their values in the config files.
1561 config ZBOOT_ROM_TEXT
1562 hex "Compressed ROM boot loader base address"
1565 The physical address at which the ROM-able zImage is to be
1566 placed in the target. Platforms which normally make use of
1567 ROM-able zImage formats normally set this to a suitable
1568 value in their defconfig file.
1570 If ZBOOT_ROM is not enabled, this has no effect.
1572 config ZBOOT_ROM_BSS
1573 hex "Compressed ROM boot loader BSS address"
1576 The base address of an area of read/write memory in the target
1577 for the ROM-able zImage which must be available while the
1578 decompressor is running. It must be large enough to hold the
1579 entire decompressed kernel plus an additional 128 KiB.
1580 Platforms which normally make use of ROM-able zImage formats
1581 normally set this to a suitable value in their defconfig file.
1583 If ZBOOT_ROM is not enabled, this has no effect.
1586 bool "Compressed boot loader in ROM/flash"
1587 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1589 Say Y here if you intend to execute your compressed kernel image
1590 (zImage) directly from ROM or flash. If unsure, say N.
1593 string "Default kernel command string"
1596 On some architectures (EBSA110 and CATS), there is currently no way
1597 for the boot loader to pass arguments to the kernel. For these
1598 architectures, you should supply some command-line options at build
1599 time by entering them here. As a minimum, you should specify the
1600 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1602 config CMDLINE_FORCE
1603 bool "Always use the default kernel command string"
1604 depends on CMDLINE != ""
1606 Always use the default kernel command string, even if the boot
1607 loader passes other arguments to the kernel.
1608 This is useful if you cannot or don't want to change the
1609 command-line options your boot loader passes to the kernel.
1614 bool "Kernel Execute-In-Place from ROM"
1615 depends on !ZBOOT_ROM
1617 Execute-In-Place allows the kernel to run from non-volatile storage
1618 directly addressable by the CPU, such as NOR flash. This saves RAM
1619 space since the text section of the kernel is not loaded from flash
1620 to RAM. Read-write sections, such as the data section and stack,
1621 are still copied to RAM. The XIP kernel is not compressed since
1622 it has to run directly from flash, so it will take more space to
1623 store it. The flash address used to link the kernel object files,
1624 and for storing it, is configuration dependent. Therefore, if you
1625 say Y here, you must know the proper physical address where to
1626 store the kernel image depending on your own flash memory usage.
1628 Also note that the make target becomes "make xipImage" rather than
1629 "make zImage" or "make Image". The final kernel binary to put in
1630 ROM memory will be arch/arm/boot/xipImage.
1634 config XIP_PHYS_ADDR
1635 hex "XIP Kernel Physical Location"
1636 depends on XIP_KERNEL
1637 default "0x00080000"
1639 This is the physical address in your flash memory the kernel will
1640 be linked for and stored to. This address is dependent on your
1644 bool "Kexec system call (EXPERIMENTAL)"
1645 depends on EXPERIMENTAL
1647 kexec is a system call that implements the ability to shutdown your
1648 current kernel, and to start another kernel. It is like a reboot
1649 but it is independent of the system firmware. And like a reboot
1650 you can start any kernel with it, not just Linux.
1652 It is an ongoing process to be certain the hardware in a machine
1653 is properly shutdown, so do not be surprised if this code does not
1654 initially work for you. It may help to enable device hotplugging
1658 bool "Export atags in procfs"
1662 Should the atags used to boot the kernel be exported in an "atags"
1663 file in procfs. Useful with kexec.
1665 config AUTO_ZRELADDR
1666 bool "Auto calculation of the decompressed kernel image address"
1667 depends on !ZBOOT_ROM && !ARCH_U300
1669 ZRELADDR is the physical address where the decompressed kernel
1670 image will be placed. If AUTO_ZRELADDR is selected, the address
1671 will be determined at run-time by masking the current IP with
1672 0xf8000000. This assumes the zImage being placed in the first 128MB
1673 from start of memory.
1676 hex "Physical address of the decompressed kernel image"
1677 depends on !AUTO_ZRELADDR
1678 default 0x00008000 if ARCH_BCMRING ||\
1703 default 0x08008000 if ARCH_MX1 ||\
1705 default 0x10008000 if ARCH_MSM ||\
1708 default 0x20008000 if ARCH_S5P6440 ||\
1711 default 0x30008000 if ARCH_S3C2410 ||\
1718 default 0x40008000 if ARCH_STMP378X ||\
1723 default 0x50008000 if ARCH_S3C64XX ||\
1725 default 0x60008000 if ARCH_VEXPRESS
1726 default 0x80008000 if ARCH_MX25 ||\
1731 default 0x90008000 if ARCH_MX5 ||\
1733 default 0xa0008000 if ARCH_IOP32X ||\
1736 default 0xc0008000 if ARCH_LH7A40X ||\
1738 default 0xf0008000 if ARCH_AAEC2000 ||\
1740 default 0xc0028000 if ARCH_CLPS711X
1741 default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
1742 default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
1743 default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
1744 default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
1745 default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
1746 default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
1747 default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
1748 default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
1749 default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
1750 default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
1751 default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
1752 default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
1753 default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
1754 default 0xc0208000 if ARCH_SA1100 && SA1111
1755 default 0xc0008000 if ARCH_SA1100 && !SA1111
1756 default 0x30108000 if ARCH_S3C2410 && PM_H1940
1757 default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
1758 default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
1760 ZRELADDR is the physical address where the decompressed kernel
1761 image will be placed. ZRELADDR has to be specified when the
1762 assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
1767 menu "CPU Power Management"
1771 source "drivers/cpufreq/Kconfig"
1773 config CPU_FREQ_SA1100
1776 config CPU_FREQ_SA1110
1779 config CPU_FREQ_INTEGRATOR
1780 tristate "CPUfreq driver for ARM Integrator CPUs"
1781 depends on ARCH_INTEGRATOR && CPU_FREQ
1784 This enables the CPUfreq driver for ARM Integrator CPUs.
1786 For details, take a look at <file:Documentation/cpu-freq>.
1792 depends on CPU_FREQ && ARCH_PXA && PXA25x
1794 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1796 config CPU_FREQ_S3C64XX
1797 bool "CPUfreq support for Samsung S3C64XX CPUs"
1798 depends on CPU_FREQ && CPU_S3C6410
1803 Internal configuration node for common cpufreq on Samsung SoC
1805 config CPU_FREQ_S3C24XX
1806 bool "CPUfreq driver for Samsung S3C24XX series CPUs"
1807 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1810 This enables the CPUfreq driver for the Samsung S3C24XX family
1813 For details, take a look at <file:Documentation/cpu-freq>.
1817 config CPU_FREQ_S3C24XX_PLL
1818 bool "Support CPUfreq changing of PLL frequency"
1819 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1821 Compile in support for changing the PLL frequency from the
1822 S3C24XX series CPUfreq driver. The PLL takes time to settle
1823 after a frequency change, so by default it is not enabled.
1825 This also means that the PLL tables for the selected CPU(s) will
1826 be built which may increase the size of the kernel image.
1828 config CPU_FREQ_S3C24XX_DEBUG
1829 bool "Debug CPUfreq Samsung driver core"
1830 depends on CPU_FREQ_S3C24XX
1832 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1834 config CPU_FREQ_S3C24XX_IODEBUG
1835 bool "Debug CPUfreq Samsung driver IO timing"
1836 depends on CPU_FREQ_S3C24XX
1838 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1840 config CPU_FREQ_S3C24XX_DEBUGFS
1841 bool "Export debugfs for CPUFreq"
1842 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1844 Export status information via debugfs.
1848 source "drivers/cpuidle/Kconfig"
1852 menu "Floating point emulation"
1854 comment "At least one emulation must be selected"
1857 bool "NWFPE math emulation"
1858 depends on !AEABI || OABI_COMPAT
1860 Say Y to include the NWFPE floating point emulator in the kernel.
1861 This is necessary to run most binaries. Linux does not currently
1862 support floating point hardware so you need to say Y here even if
1863 your machine has an FPA or floating point co-processor podule.
1865 You may say N here if you are going to load the Acorn FPEmulator
1866 early in the bootup.
1869 bool "Support extended precision"
1870 depends on FPE_NWFPE
1872 Say Y to include 80-bit support in the kernel floating-point
1873 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1874 Note that gcc does not generate 80-bit operations by default,
1875 so in most cases this option only enlarges the size of the
1876 floating point emulator without any good reason.
1878 You almost surely want to say N here.
1881 bool "FastFPE math emulation (EXPERIMENTAL)"
1882 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1884 Say Y here to include the FAST floating point emulator in the kernel.
1885 This is an experimental much faster emulator which now also has full
1886 precision for the mantissa. It does not support any exceptions.
1887 It is very simple, and approximately 3-6 times faster than NWFPE.
1889 It should be sufficient for most programs. It may be not suitable
1890 for scientific calculations, but you have to check this for yourself.
1891 If you do not feel you need a faster FP emulation you should better
1895 bool "VFP-format floating point maths"
1896 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1898 Say Y to include VFP support code in the kernel. This is needed
1899 if your hardware includes a VFP unit.
1901 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1902 release notes and additional status information.
1904 Say N if your target does not have VFP hardware.
1912 bool "Advanced SIMD (NEON) Extension support"
1913 depends on VFPv3 && CPU_V7
1915 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1920 menu "Userspace binary formats"
1922 source "fs/Kconfig.binfmt"
1925 tristate "RISC OS personality"
1928 Say Y here to include the kernel code necessary if you want to run
1929 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1930 experimental; if this sounds frightening, say N and sleep in peace.
1931 You can also say M here to compile this support as a module (which
1932 will be called arthur).
1936 menu "Power management options"
1938 source "kernel/power/Kconfig"
1940 config ARCH_SUSPEND_POSSIBLE
1945 source "net/Kconfig"
1947 source "drivers/Kconfig"
1951 source "arch/arm/Kconfig.debug"
1953 source "security/Kconfig"
1955 source "crypto/Kconfig"
1957 source "lib/Kconfig"