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Upload Tizen:Base source
[framework/base/util-linux-ng.git]
/
tests
/
expected
/
lscpu
/
lscpu-ia64-hpmatterhorn
1
CPU(s): 8
2
Thread(s) per core: 1
3
Core(s) per socket: 1
4
CPU socket(s): 8
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NUMA node(s): 3
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Vendor ID: GenuineIntel
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CPU family: Itanium 2
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Model: 1
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CPU MHz: 1300.000000
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L1d cache: 16K
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L1i cache: 16K
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L2 cache: 256K
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L3 cache: 3072K
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# The following is the parsable format, which can be fed to other
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# programs. Each different item in every column has an unique ID
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# starting from zero.
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# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
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0,0,0,0,,0,0,0,0
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1,1,1,0,,1,1,1,1
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2,2,2,0,,2,2,2,2
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3,3,3,0,,3,3,3,3
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4,4,4,1,,4,4,4,4
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5,5,5,1,,5,5,5,5
25
6,6,6,1,,6,6,6,6
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7,7,7,1,,7,7,7,7