#include "acpi.h" // struct rsdp_descriptor
#include "util.h" // memcpy
-#include "pci.h" // pci_find_device
-#include "biosvar.h" // GET_EBDA
+#include "byteorder.h" // cpu_to_le16
+#include "pci.h" // pci_find_init_device
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_INTERRUPT_LINE
-#include "paravirt.h"
-#include "dev-i440fx.h" // piix4_fadt_init
+#include "ioport.h" // inl
+#include "paravirt.h" // qemu_cfg_irq0_override
+#include "dev-q35.h" // qemu_cfg_irq0_override
/****************************************************/
/* ACPI tables init */
/*
+ * Differentiated System Description Table (DSDT)
+ */
+#define DSDT_SIGNATURE 0x54445344 // DSDT
+
+/*
* MADT values and structures
*/
u16 flags;
} PACKED;
+struct madt_local_nmi {
+ ACPI_SUB_HEADER_DEF
+ u8 processor_id; /* ACPI processor id */
+ u16 flags; /* MPS INTI flags */
+ u8 lint; /* Local APIC LINT# */
+} PACKED;
+
+
/*
* ACPI 2.0 Generic Address Space definition.
*/
u16 min_tick;
u8 page_protect;
} PACKED;
-#define ACPI_HPET_ADDRESS 0xFED00000UL
+
+#define HPET_ID 0x000
+#define HPET_PERIOD 0x004
/*
* SRAT (NUMA topology description) table
h->revision = rev;
memcpy(h->oem_id, CONFIG_APPNAME6, 6);
memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
- memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
memcpy(h->oem_table_id + 4, (void*)&sig, 4);
h->oem_revision = cpu_to_le32(1);
+ memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
h->asl_compiler_revision = cpu_to_le32(1);
h->checksum -= checksum(h, len);
}
+#define PIIX4_ACPI_ENABLE 0xf1
+#define PIIX4_ACPI_DISABLE 0xf0
+#define PIIX4_GPE0_BLK 0xafe0
+#define PIIX4_GPE0_BLK_LEN 4
+
+#define PIIX4_PM_INTRRUPT 9 // irq 9
+
+static void piix4_fadt_init(struct pci_device *pci, void *arg)
+{
+ struct fadt_descriptor_rev1 *fadt = arg;
+
+ fadt->model = 1;
+ fadt->reserved1 = 0;
+ fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT);
+ fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
+ fadt->acpi_enable = PIIX4_ACPI_ENABLE;
+ fadt->acpi_disable = PIIX4_ACPI_DISABLE;
+ fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+ fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
+ fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
+ fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+ fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+ /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
+ fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
+ (1 << 15));
+}
+
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_fadt_init(struct pci_device *dev, void *arg)
+{
+ struct fadt_descriptor_rev1 *fadt = arg;
+
+ fadt->model = 1;
+ fadt->reserved1 = 0;
+ fadt->sci_int = cpu_to_le16(9);
+ fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
+ fadt->acpi_enable = ICH9_ACPI_ENABLE;
+ fadt->acpi_disable = ICH9_ACPI_DISABLE;
+ fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+ fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
+ fadt->gpe0_blk = cpu_to_le32(PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS);
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN;
+ fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+ fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+ /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
+ fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) |
+ (1 << 7));
+}
+
static const struct pci_device_id fadt_init_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
piix4_fadt_init),
-
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+ ich9_lpc_fadt_init),
PCI_DEVICE_END
};
-static void*
-build_fadt(int bdf)
+static void fill_dsdt(struct fadt_descriptor_rev1 *fadt, void *dsdt)
+{
+ if (fadt->dsdt) {
+ free((void *)le32_to_cpu(fadt->dsdt));
+ }
+ fadt->dsdt = cpu_to_le32((u32)dsdt);
+ fadt->checksum -= checksum(fadt, sizeof(*fadt));
+ dprintf(1, "ACPI DSDT=%p\n", dsdt);
+}
+
+static void *
+build_fadt(struct pci_device *pci)
{
struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
- void *dsdt = malloc_high(sizeof(AmlCode));
- if (!fadt || !facs || !dsdt) {
+ if (!fadt || !facs) {
warn_noalloc();
return NULL;
}
facs->signature = FACS_SIGNATURE;
facs->length = cpu_to_le32(sizeof(*facs));
- /* DSDT */
- memcpy(dsdt, AmlCode, sizeof(AmlCode));
-
/* FADT */
memset(fadt, 0, sizeof(*fadt));
fadt->firmware_ctrl = cpu_to_le32((u32)facs);
- fadt->dsdt = cpu_to_le32((u32)dsdt);
- fadt->model = 1;
- fadt->reserved1 = 0;
- int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
- fadt->sci_int = cpu_to_le16(pm_sci_int);
- fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
- fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
- fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
- fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm_tmr_len = 4;
- fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
- fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
- pci_init_device(fadt_init_tbl, bdf, fadt);
- /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
- fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
+ fadt->dsdt = 0; /* dsdt will be filled later in acpi_bios_init()
+ by fill_dsdt() */
+ pci_init_device(fadt_init_tbl, pci, fadt);
build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
int madt_size = (sizeof(struct multiple_apic_table)
+ sizeof(struct madt_processor_apic) * MaxCountCPUs
+ sizeof(struct madt_io_apic)
- + sizeof(struct madt_intsrcovr) * 16);
+ + sizeof(struct madt_intsrcovr) * 16
+ + sizeof(struct madt_local_nmi));
+
struct multiple_apic_table *madt = malloc_high(madt_size);
if (!madt) {
warn_noalloc();
apic->length = sizeof(*apic);
apic->processor_id = i;
apic->local_apic_id = i;
- if (i < CountCPUs)
+ if (apic_id_is_present(apic->local_apic_id))
apic->flags = cpu_to_le32(1);
else
apic->flags = cpu_to_le32(0);
struct madt_io_apic *io_apic = (void*)apic;
io_apic->type = APIC_IO;
io_apic->length = sizeof(*io_apic);
- io_apic->io_apic_id = CountCPUs;
+ io_apic->io_apic_id = BUILD_IOAPIC_ID;
io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
io_apic->interrupt = cpu_to_le32(0);
intsrcovr++;
}
- build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
+ struct madt_local_nmi *local_nmi = (void*)intsrcovr;
+ local_nmi->type = APIC_LOCAL_NMI;
+ local_nmi->length = sizeof(*local_nmi);
+ local_nmi->processor_id = 0xff; /* all processors */
+ local_nmi->flags = 0;
+ local_nmi->lint = 1; /* LINT1 */
+ local_nmi++;
+
+ build_header((void*)madt, APIC_SIGNATURE, (void*)local_nmi - (void*)madt, 1);
return madt;
}
return ssdt_ptr + bytes;
}
-// AML Processor() object. See src/ssdt-proc.dsl for info.
-static unsigned char ssdt_proc[] = {
- 0x5b,0x83,0x42,0x05,0x43,0x50,0x41,0x41,
- 0xaa,0x10,0xb0,0x00,0x00,0x06,0x08,0x49,
- 0x44,0x5f,0x5f,0x0a,0xaa,0x08,0x5f,0x48,
- 0x49,0x44,0x0d,0x41,0x43,0x50,0x49,0x30,
- 0x30,0x30,0x37,0x00,0x14,0x0f,0x5f,0x4d,
- 0x41,0x54,0x00,0xa4,0x43,0x50,0x4d,0x41,
- 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x53,
- 0x54,0x41,0x00,0xa4,0x43,0x50,0x53,0x54,
- 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x45,
- 0x4a,0x30,0x01,0x43,0x50,0x45,0x4a,0x49,
- 0x44,0x5f,0x5f,0x68
-};
-#define SD_OFFSET_CPUHEX 6
-#define SD_OFFSET_CPUID1 8
-#define SD_OFFSET_CPUID2 20
+#include "ssdt-proc.hex"
+
+/* 0x5B 0x83 ProcessorOp PkgLength NameString ProcID */
+#define PROC_OFFSET_CPUHEX (*ssdt_proc_name - *ssdt_proc_start + 2)
+#define PROC_OFFSET_CPUID1 (*ssdt_proc_name - *ssdt_proc_start + 4)
+#define PROC_OFFSET_CPUID2 (*ssdt_proc_id - *ssdt_proc_start)
+#define PROC_SIZEOF (*ssdt_proc_end - *ssdt_proc_start)
+#define PROC_AML (ssdp_proc_aml + *ssdt_proc_start)
+
+/* 0x5B 0x82 DeviceOp PkgLength NameString */
+#define PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
+#define PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
+#define PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
+#define PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
+#define PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
+#define PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
+#define PCI_SLOTS 32
#define SSDT_SIGNATURE 0x54445353 // SSDT
+#define SSDT_HEADER_LENGTH 36
+
+#include "ssdt-susp.hex"
+#include "ssdt-pcihp.hex"
+
+#define PCI_RMV_BASE 0xae0c
+
+static u8*
+build_notify(u8 *ssdt_ptr, const char *name, int skip, int count,
+ const char *target, int ofs)
+{
+ count -= skip;
+
+ *(ssdt_ptr++) = 0x14; // MethodOp
+ ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*count), 2);
+ memcpy(ssdt_ptr, name, 4);
+ ssdt_ptr += 4;
+ *(ssdt_ptr++) = 0x02; // MethodOp
+
+ int i;
+ for (i = skip; count-- > 0; i++) {
+ *(ssdt_ptr++) = 0xA0; // IfOp
+ ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
+ *(ssdt_ptr++) = 0x93; // LEqualOp
+ *(ssdt_ptr++) = 0x68; // Arg0Op
+ *(ssdt_ptr++) = 0x0A; // BytePrefix
+ *(ssdt_ptr++) = i;
+ *(ssdt_ptr++) = 0x86; // NotifyOp
+ memcpy(ssdt_ptr, target, 4);
+ ssdt_ptr[ofs] = getHex(i >> 4);
+ ssdt_ptr[ofs + 1] = getHex(i);
+ ssdt_ptr += 4;
+ *(ssdt_ptr++) = 0x69; // Arg1Op
+ }
+ return ssdt_ptr;
+}
+
+static void patch_pcihp(int slot, u8 *ssdt_ptr, u32 eject)
+{
+ ssdt_ptr[PCIHP_OFFSET_HEX] = getHex(slot >> 4);
+ ssdt_ptr[PCIHP_OFFSET_HEX+1] = getHex(slot);
+ ssdt_ptr[PCIHP_OFFSET_ID] = slot;
+ ssdt_ptr[PCIHP_OFFSET_ADR + 2] = slot;
+
+ /* Runtime patching of EJ0: to disable hotplug for a slot,
+ * replace the method name: _EJ0 by EJ0_. */
+ /* Sanity check */
+ if (memcmp(ssdt_ptr + PCIHP_OFFSET_EJ0, "_EJ0", 4)) {
+ warn_internalerror();
+ }
+ if (!eject) {
+ memcpy(ssdt_ptr + PCIHP_OFFSET_EJ0, "EJ0_", 4);
+ }
+}
+
static void*
build_ssdt(void)
{
int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
- // length = ScopeOp + procs + NTYF method + CPON package
- int length = ((1+3+4)
- + (acpi_cpus * sizeof(ssdt_proc))
- + (1+2+5+(12*acpi_cpus))
- + (6+2+1+(1*acpi_cpus)));
- u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length);
+ int length = (sizeof(ssdp_susp_aml) // _S3_ / _S4_ / _S5_
+ + (1+3+4) // Scope(_SB_)
+ + (acpi_cpus * PROC_SIZEOF) // procs
+ + (1+2+5+(12*acpi_cpus)) // NTFY
+ + (6+2+1+(1*acpi_cpus)) // CPON
+ + 17 // BDAT
+ + (1+3+4) // Scope(PCI0)
+ + ((PCI_SLOTS - 1) * PCIHP_SIZEOF) // slots
+ + (1+2+5+(12*(PCI_SLOTS - 1)))); // PCNT
+ u8 *ssdt = malloc_high(length);
if (! ssdt) {
warn_noalloc();
return NULL;
}
- u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header);
+ u8 *ssdt_ptr = ssdt;
+
+ // Copy header and encode fwcfg values in the S3_ / S4_ / S5_ packages
+ int sys_state_size;
+ char *sys_states = romfile_loadfile("etc/system-states", &sys_state_size);
+ if (!sys_states || sys_state_size != 6)
+ sys_states = (char[]){128, 0, 0, 129, 128, 128};
+
+ memcpy(ssdt_ptr, ssdp_susp_aml, sizeof(ssdp_susp_aml));
+ if (!(sys_states[3] & 128))
+ ssdt_ptr[acpi_s3_name[0]] = 'X';
+ if (!(sys_states[4] & 128))
+ ssdt_ptr[acpi_s4_name[0]] = 'X';
+ else
+ ssdt_ptr[acpi_s4_pkg[0] + 1] = ssdt[acpi_s4_pkg[0] + 3] = sys_states[4] & 127;
+ ssdt_ptr += sizeof(ssdp_susp_aml);
// build Scope(_SB_) header
*(ssdt_ptr++) = 0x10; // ScopeOp
- ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3);
+ ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3);
*(ssdt_ptr++) = '_';
*(ssdt_ptr++) = 'S';
*(ssdt_ptr++) = 'B';
// build Processor object for each processor
int i;
for (i=0; i<acpi_cpus; i++) {
- memcpy(ssdt_ptr, ssdt_proc, sizeof(ssdt_proc));
- ssdt_ptr[SD_OFFSET_CPUHEX] = getHex(i >> 4);
- ssdt_ptr[SD_OFFSET_CPUHEX+1] = getHex(i);
- ssdt_ptr[SD_OFFSET_CPUID1] = i;
- ssdt_ptr[SD_OFFSET_CPUID2] = i;
- ssdt_ptr += sizeof(ssdt_proc);
+ memcpy(ssdt_ptr, PROC_AML, PROC_SIZEOF);
+ ssdt_ptr[PROC_OFFSET_CPUHEX] = getHex(i >> 4);
+ ssdt_ptr[PROC_OFFSET_CPUHEX+1] = getHex(i);
+ ssdt_ptr[PROC_OFFSET_CPUID1] = i;
+ ssdt_ptr[PROC_OFFSET_CPUID2] = i;
+ ssdt_ptr += PROC_SIZEOF;
}
// build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
- *(ssdt_ptr++) = 0x14; // MethodOp
- ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*acpi_cpus), 2);
- *(ssdt_ptr++) = 'N';
- *(ssdt_ptr++) = 'T';
- *(ssdt_ptr++) = 'F';
- *(ssdt_ptr++) = 'Y';
- *(ssdt_ptr++) = 0x02;
- for (i=0; i<acpi_cpus; i++) {
- *(ssdt_ptr++) = 0xA0; // IfOp
- ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
- *(ssdt_ptr++) = 0x93; // LEqualOp
- *(ssdt_ptr++) = 0x68; // Arg0Op
- *(ssdt_ptr++) = 0x0A; // BytePrefix
- *(ssdt_ptr++) = i;
- *(ssdt_ptr++) = 0x86; // NotifyOp
- *(ssdt_ptr++) = 'C';
- *(ssdt_ptr++) = 'P';
- *(ssdt_ptr++) = getHex(i >> 4);
- *(ssdt_ptr++) = getHex(i);
- *(ssdt_ptr++) = 0x69; // Arg1Op
- }
+ // Arg0 = Processor ID = APIC ID
+ ssdt_ptr = build_notify(ssdt_ptr, "NTFY", 0, acpi_cpus, "CP00", 2);
// build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
*(ssdt_ptr++) = 0x08; // NameOp
ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
*(ssdt_ptr++) = acpi_cpus;
for (i=0; i<acpi_cpus; i++)
- *(ssdt_ptr++) = (i < CountCPUs) ? 0x01 : 0x00;
+ *(ssdt_ptr++) = (apic_id_is_present(i)) ? 0x01 : 0x00;
+
+ // store pci io windows: start, end, length
+ // this way we don't have to do the math in the dsdt
+ struct bfld *bfld = malloc_high(sizeof(struct bfld));
+ bfld->p0s = pcimem_start;
+ bfld->p0e = pcimem_end - 1;
+ bfld->p0l = pcimem_end - pcimem_start;
+ bfld->p1s = pcimem64_start;
+ bfld->p1e = pcimem64_end - 1;
+ bfld->p1l = pcimem64_end - pcimem64_start;
+
+ // build "OperationRegion(BDAT, SystemMemory, 0x12345678, 0x87654321)"
+ *(ssdt_ptr++) = 0x5B; // ExtOpPrefix
+ *(ssdt_ptr++) = 0x80; // OpRegionOp
+ *(ssdt_ptr++) = 'B';
+ *(ssdt_ptr++) = 'D';
+ *(ssdt_ptr++) = 'A';
+ *(ssdt_ptr++) = 'T';
+ *(ssdt_ptr++) = 0x00; // SystemMemory
+ *(ssdt_ptr++) = 0x0C; // DWordPrefix
+ *(u32*)ssdt_ptr = (u32)bfld;
+ ssdt_ptr += 4;
+ *(ssdt_ptr++) = 0x0C; // DWordPrefix
+ *(u32*)ssdt_ptr = sizeof(struct bfld);
+ ssdt_ptr += 4;
+
+ // build Scope(PCI0) opcode
+ *(ssdt_ptr++) = 0x10; // ScopeOp
+ ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3);
+ *(ssdt_ptr++) = 'P';
+ *(ssdt_ptr++) = 'C';
+ *(ssdt_ptr++) = 'I';
+ *(ssdt_ptr++) = '0';
+
+ // build Device object for each slot
+ u32 rmvc_pcrm = inl(PCI_RMV_BASE);
+ for (i=1; i<PCI_SLOTS; i++) {
+ u32 eject = rmvc_pcrm & (0x1 << i);
+ memcpy(ssdt_ptr, PCIHP_AML, PCIHP_SIZEOF);
+ patch_pcihp(i, ssdt_ptr, eject != 0);
+ ssdt_ptr += PCIHP_SIZEOF;
+ }
+
+ ssdt_ptr = build_notify(ssdt_ptr, "PCNT", 1, PCI_SLOTS, "S00_", 1);
build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
return ssdt;
}
-#define HPET_SIGNATURE 0x54455048 //HPET
+#define HPET_SIGNATURE 0x54455048 // HPET
static void*
build_hpet(void)
{
- struct acpi_20_hpet *hpet = malloc_high(sizeof(*hpet));
+ struct acpi_20_hpet *hpet;
+ const void *hpet_base = (void *)BUILD_HPET_ADDRESS;
+ u32 hpet_vendor = readl(hpet_base + HPET_ID) >> 16;
+ u32 hpet_period = readl(hpet_base + HPET_PERIOD);
+
+ if (hpet_vendor == 0 || hpet_vendor == 0xffff ||
+ hpet_period == 0 || hpet_period > 100000000)
+ return NULL;
+
+ hpet = malloc_high(sizeof(*hpet));
if (!hpet) {
warn_noalloc();
return NULL;
* emulated hpet
*/
hpet->timer_block_id = cpu_to_le32(0x8086a201);
- hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
+ hpet->addr.address = cpu_to_le32(BUILD_HPET_ADDRESS);
build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
return hpet;
{
numamem->type = SRAT_MEMORY;
numamem->length = sizeof(*numamem);
- memset (numamem->proximity, 0 ,4);
+ memset(numamem->proximity, 0 ,4);
numamem->proximity[0] = node;
numamem->flags = cpu_to_le32(!!enabled);
numamem->base_addr_low = base & 0xFFFFFFFF;
numamem->length_high = len >> 32;
}
-#define SRAT_SIGNATURE 0x54415253 //HPET
+#define SRAT_SIGNATURE 0x54415253 // SRAT
static void *
build_srat(void)
{
core->proximity_lo = curnode;
memset(core->proximity_hi, 0, 3);
core->local_sapic_eid = 0;
- if (i < CountCPUs)
+ if (apic_id_is_present(i))
core->flags = cpu_to_le32(1);
else
- core->flags = 0;
+ core->flags = cpu_to_le32(0);
core++;
}
return srat;
}
+static void *
+build_mcfg_q35(void)
+{
+ struct acpi_table_mcfg *mcfg;
+
+ int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+ mcfg = malloc_high(len);
+ if (!mcfg) {
+ warn_noalloc();
+ return NULL;
+ }
+ memset(mcfg, 0, len);
+ mcfg->allocation[0].address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+ mcfg->allocation[0].pci_segment = Q35_HOST_PCIE_PCI_SEGMENT;
+ mcfg->allocation[0].start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
+ mcfg->allocation[0].end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
+
+ build_header((void *)mcfg, MCFG_SIGNATURE, len, 1);
+ return mcfg;
+}
+
static const struct pci_device_id acpi_find_tbl[] = {
/* PIIX4 Power Management device. */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
-
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL),
PCI_DEVICE_END,
};
dprintf(3, "init ACPI tables\n");
// This code is hardcoded for PIIX4 Power Management device.
- int bdf = pci_find_init_device(acpi_find_tbl, NULL);
- if (bdf < 0)
+ struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
+ if (!pci)
// Device not found
return;
- // Create initial rsdt table
- struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
- if (!rsdp) {
- warn_noalloc();
- return;
- }
-
+ // Build ACPI tables
u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
#define ACPI_INIT_TABLE(X) \
tbl_idx++; \
} while(0)
- // Add tables
- ACPI_INIT_TABLE(build_fadt(bdf));
+ struct fadt_descriptor_rev1 *fadt = build_fadt(pci);
+ ACPI_INIT_TABLE(fadt);
ACPI_INIT_TABLE(build_ssdt());
ACPI_INIT_TABLE(build_madt());
ACPI_INIT_TABLE(build_hpet());
ACPI_INIT_TABLE(build_srat());
+ if (pci->device == PCI_DEVICE_ID_INTEL_ICH9_LPC)
+ ACPI_INIT_TABLE(build_mcfg_q35());
u16 i, external_tables = qemu_cfg_acpi_additional_tables();
- for(i = 0; i < external_tables; i++) {
+ for (i = 0; i < external_tables; i++) {
u16 len = qemu_cfg_next_acpi_table_len();
void *addr = malloc_high(len);
if (!addr) {
warn_noalloc();
continue;
}
- ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
+ struct acpi_table_header *header =
+ qemu_cfg_next_acpi_table_load(addr, len);
+ if (header->signature == DSDT_SIGNATURE) {
+ if (fadt) {
+ fill_dsdt(fadt, addr);
+ }
+ } else {
+ ACPI_INIT_TABLE(header);
+ }
if (tbl_idx == MAX_ACPI_TABLES) {
warn_noalloc();
break;
}
}
+ if (fadt && !fadt->dsdt) {
+ /* default DSDT */
+ void *dsdt = malloc_high(sizeof(AmlCode));
+ if (!dsdt) {
+ warn_noalloc();
+ return;
+ }
+ memcpy(dsdt, AmlCode, sizeof(AmlCode));
+ fill_dsdt(fadt, dsdt);
+ }
+ // Build final rsdt table
struct rsdt_descriptor_rev1 *rsdt;
size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
rsdt = malloc_high(rsdt_len);
-
if (!rsdt) {
warn_noalloc();
return;
}
memset(rsdt, 0, rsdt_len);
memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
-
build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
// Build rsdp pointer table
+ struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
+ if (!rsdp) {
+ warn_noalloc();
+ return;
+ }
memset(rsdp, 0, sizeof(*rsdp));
rsdp->signature = RSDP_SIGNATURE;
memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
projects / external / qemu.git / blobdiff